Prosecution Insights
Last updated: August 17, 2026
Application No. 19/435,199

Display Apparatus and Driving Method Thereof

Non-Final OA §103
Filed
Dec 29, 2025
Priority
Dec 31, 2024 — RE 10-2024-0203034
Examiner
MATTHEWS, ANDRE L
Art Unit
2621
Tech Center
2600 — Communications
Assignee
LG Display Co., Ltd.
OA Round
1 (Non-Final)
62%
Grant Probability
Moderate
1-2
OA Rounds
2y 10m
Est. Remaining
78%
With Interview

Examiner Intelligence

Grants 62% of resolved cases
62%
Career Allowance Rate
320 granted / 518 resolved
At TC average
Strong +16% interview lift
Without
With
+16.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
24 currently pending
Career history
552
Total Applications
across all art units

Statute-Specific Performance

§101
1.8%
-38.2% vs TC avg
§103
71.3%
+31.3% vs TC avg
§102
12.2%
-27.8% vs TC avg
§112
13.2%
-26.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 518 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-7, 9-11, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Lim (US 2020/0098315) in view of Park (US 2022/0157215). Regarding claim 1, Lim teaches A display apparatus, comprising: a display panel including a subpixel (Fig. 1); and a driver configured to drive the display panel (Fig. 1 drivers 20,30,40,50) , wherein the subpixel comprises: a sensing transistor configured to transfer a reference voltage, applied through a data line (Fig. 2A light sensor circuit 102 including sensing transistor St and light sensing unit LSU connected to data line Dlj), to an Node N1 for a first time included in a horizontal period (during sensing) ; and a switching transistor configured to transfer a data voltage, applied through the data line, to a first electrode of the capacitor for a second time included in the horizontal period (Fig. 2A ST1 [0071-0072]. Although Lim teaches the limitations as discussed above he fails to teach an second electrode of a capacitor receiving a voltage through the sensing transistor. However in the field of manufacturing a sensing pixel for a display device, Park teaches an second electrode of a capacitor receiving a voltage through the sensing transistor ([0087].). Therefore it would have been obvious to one of ordinary skill in the art to combine the device as taught by Lim with the device as taught by Park. This combination improves driving stability and reliability of the device by evaluating and compensating the driving capability of transistors in a sub-pixel as taught by Park [0007]. Regarding claim 2, Lim teaches wherein the sensing transistor comprises a first electrode connected to the data line, a gate electrode connected to a gate line, and a second electrode connected to the second electrode of the capacitor (Fig. 2A sensing transistor ST and LSU), and wherein the switching transistor comprises a first electrode connected to the data line, a gate electrode connected to a first scan line included in the first gate line, and a second electrode connected to the first electrode of the capacitor (Fig. 2A switching transistor ST1) and Park teaches a gate line including a sensing line and a scan line (Fig. 2 gate line GL1 includes sense line and scan line). Regarding claim 3, Lim teaches wherein the subpixel further comprises: a driving transistor including a gate electrode connected to the second electrode of the switching transistor and the first electrode of the capacitor (node N1), a first electrode connected to a high-level voltage line (Fig. 2A driving transistor DR connected to ELVDD), and a second electrode connected to the second electrode of the capacitor and the second electrode of the sensing transistor (Fig. 2A driving transistor DR connected to light sensing unit 102 and capacitor CSt); and a light emitting diode including an anode electrode and a cathode electrode, the anode electrode connected to the second electrode of the sensing transistor, the second electrode of the driving transistor, and the second electrode of the capacitor, the cathode electrode connected to a low-level voltage line (Fig. 2A OLED connected to low voltage ELVSS). Regarding claim 4, Park teaches wherein the sensing transistor and the switching transistor have a period where operations opposite to each other are performed in response to a first gate signal applied through a first gate line (Fig. 11 shows the switch transistor is turned on before the sense transistor and the switch transistor is turn off after the sense transistor is turned on. It is therefore opposite operations is reasonably interpretated as one transistor is on while the other transistor is off). Regarding claim 5, Park teaches wherein the sensing transistor and the switching transistor have a period where the sensing transistor and the switching transistor are simultaneously turned off in response to a first gate signal applied through a first gate line ([0048]. Regarding claim 6, Park teaches wherein each of the sensing transistor and the switching transistor is implemented as a CMOS type including a PMOS type and an NMOS type, wherein the sensing transistor is implemented as one of the PMOS type and the NMOS type, and wherein the switching transistor is implemented as the other of the PMOS type and the NMOS type ([0033-0034][0124] Based on these teachings it is obvious that transistors implemented can be any combination of Nmos type or Pmos type based on a design choice). Regarding claim 7, Lim teaches wherein the sensing transistor comprises a first electrode connected to the data line, a gate electrode connected to a gate line, and a second electrode connected to the second electrode of the capacitor (Fig. 2A sensing transistor ST and LSU), and wherein the switching transistor comprises a first electrode connected to the data line, a gate electrode connected to a first scan line included in the first gate line, and a second electrode connected to the first electrode of the capacitor (Fig. 2A switching transistor ST1) and Park teaches a gate line including a sensing line and a scan line (Fig. 2 gate line GL1 includes sense line and scan line). Regarding claim 9, Lim teaches A display apparatus, comprising: a display panel including a subpixel (Fig. 1); and a driver configured to drive the display panel (Fig. 1 drivers 20,30,40,50) , wherein the subpixel comprises: a sensing transistor configured to transfer a reference voltage, applied through a data line (Fig. 2A light sensor circuit 102 including sensing transistor St and light sensing unit LSU connected to data line Dlj), to an Node N1 for a first time included in a horizontal period (during sensing) ; and a switching transistor configured to transfer a data voltage, applied through the data line, to a first electrode of the capacitor for a second time included in the horizontal period (Fig. 2A ST1 [0071-0072]) driving a driving transistor, based on a voltage difference between the data voltage stored in the capacitor and the reference voltage, and allowing a light emitting diode to emit light, based on a driving current generated from the driving transistor ([0071-0072][0074]). Although Lim teaches the limitations as discussed above he fails to teach an second electrode of a capacitor receiving a voltage through the sensing transistor and . However in the field of manufacturing a sensing pixel for a display device, Park teaches an second electrode of a capacitor receiving a voltage through the sensing transistor ([0087].). Therefore it would have been obvious to one of ordinary skill in the art to combine the device as taught by Lim with the device as taught by Park. This combination improves driving stability and reliability of the device by evaluating and compensating the driving capability of transistors in a sub-pixel as taught by Park [0007]. Regarding claim 10, Lim teaches wherein the sensing transistor comprises a first electrode connected to the data line, a gate electrode connected to a gate line, and a second electrode connected to the second electrode of the capacitor (Fig. 2A sensing transistor ST and LSU), and wherein the switching transistor comprises a first electrode connected to the data line, a gate electrode connected to a first scan line included in the first gate line, and a second electrode connected to the first electrode of the capacitor (Fig. 2A switching transistor ST1) and Park teaches a gate line including a sensing line and a scan line (Fig. 2 gate line GL1 includes sense line and scan line). Regarding claim 11, wherein the sensing transistor comprises a first electrode connected to the data line, a gate electrode connected to a gate line, and a second electrode connected to the second electrode of the capacitor (Fig. 2A sensing transistor ST and LSU), and wherein the switching transistor comprises a first electrode connected to the data line, a gate electrode connected to a first scan line included in the first gate line, and a second electrode connected to the first electrode of the capacitor (Fig. 2A switching transistor ST1) and Park teaches the switching transistor and the sensing transistor connected to the same first gate line (Fig. 2 gate line GL1 includes sense line and scan line). Regarding claim 13, Lim teaches wherein the subpixel further comprises: a driving transistor including a gate electrode connected to the second electrode of the switching transistor and the first electrode of the capacitor (node N1), a first electrode connected to a high-level voltage line (Fig. 2A driving transistor DR connected to ELVDD), and a second electrode connected to the second electrode of the capacitor and the second electrode of the sensing transistor (Fig. 2A driving transistor DR connected to light sensing unit 102 and capacitor CSt); and a light emitting diode including an anode electrode and a cathode electrode, the anode electrode connected to the second electrode of the sensing transistor, the second electrode of the driving transistor, and the second electrode of the capacitor, the cathode electrode connected to a low-level voltage line (Fig. 2A OLED connected to low voltage ELVSS). Allowable Subject Matter Claims 8 and 12 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. These claims are objected to based on the driving method applied to the transistors through the connections expressed in the preceding and intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRE L MATTHEWS whose telephone number is (571)270-5806. The examiner can normally be reached Mon-Fri 9:00-6:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amr Awad can be reached at 571-272-7764. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANDRE L MATTHEWS/ Primary Examiner, Art Unit 2621
Read full office action

Prosecution Timeline

Dec 29, 2025
Application Filed
Jul 30, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
62%
Grant Probability
78%
With Interview (+16.1%)
3y 5m (~2y 10m remaining)
Median Time to Grant
Low
PTA Risk
Based on 518 resolved cases by this examiner. Grant probability derived from career allowance rate.

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