Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application filed December 30, 2025, claims 1-16 are presented for examination. Claims 1 and 11 are independent claims.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119(a)-(d), and based on application # 10-2025-0039978 filed in Korea on March 28, 2025 which papers have been placed of record in the file.
Oath/Declaration
The Office acknowledges receipt of a properly signed Oath/Declaration submitted December 30, 2025.
Information Disclosure Statement
The Applicant’s Information Disclosure Statements filed have been received, entered into the record, and considered.
Drawings
The drawings filed December 30, 2025 are accepted by the examiner.
Abstract
The abstract filed December 30, 2025 is accepted by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7-13 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20220084478 Al) in view of Hur et al. (US 20160180789 Al)
As to Claim 1:
Kim et al. discloses a display device (Kim, see Abstract, where Kim discloses a display apparatus includes a display panel including a plurality of horizontal lines each including a plurality of pixels, a timing controller configured to output a polarity control signal representing a polarity corresponding to each of the plurality of horizontal lines and having a value inverted by n horizontal line units, and a source driver configured to generate a timing pulse signal sequentially
representing a data charging time of each of the plurality of horizontal lines and to output a data voltage, having a polarity corresponding to each of the plurality of horizontal lines, to the display panel on the basis of the timing pulse signal. When a value of the polarity control signal is
inverted, the source driver generates the timing pulse signal including a data charging time corresponding to a count value obtained by counting a number of horizontal lines after a polarity is inverted) comprising: a display panel (Kim, see display panel 1200 in figure 1) including a plurality of data lines (Kim, see data lines DL1 and DL2 in figure 1 and paragraph [0027], where Kim discloses that the display panel 1200 may include a plurality of gate lines GLl to GLn (where n is an integer of 2 or more), a plurality of data lines DLl to DLm (where mis an integer of 2 or more) arranged in a direction intersecting with the plurality of gate lines GLl to GLn, and a plurality of pixels PX respectively provided in a plurality of areas defined by intersections of the gate lines GLl to GLn and the data lines DLl to DLm)), a plurality of gate lines (Kim, see CL1 and CL2 in figure 1 and paragraph [0027], where Kim discloses that the display panel 1200 may include a plurality of gate lines GLl to GLn (where n is an integer of 2 or more), a plurality of data lines DLl to DLm (where mis an integer of 2 or more) arranged in a direction intersecting with the plurality of gate lines GLl to GLn, and a plurality of pixels PX respectively provided in a plurality of areas defined by intersections of the gate lines GLl to GLn and the data lines DLl to DLm), and a plurality of pixels (Kim, see PX in figure 1 and paragraph [0027], where Kim discloses that the display panel 1200 may include a plurality of gate lines GLl to GLn (where n is an integer of 2 or more), a plurality of data lines DLl to DLm (where mis an integer of 2 or more) arranged in a direction intersecting with the plurality of gate lines GLl to GLn, and a plurality of pixels PX respectively provided in a plurality of areas defined by intersections of the gate lines GLl to GLn and the data lines DLl to DLm); a data driver (Kim, see source driver 200 in figure 1) electrically connected to the plurality of data lines (Kim, see DL1 through DLm in figure 1) and configured to output a data voltage having a polarity indicated by a polarity control signal (Kim, see paragraphs [0028] and [0033], where Kim discloses that when the display panel 1200 is a TFT-LCD, each of the pixels PX may include a thin film transistor (TFT) including a gate electrode and a source electrode respectively connected to a gate line and a data line corresponding thereto, a liquid crystal capacitor connected to a drain electrode of the TFT, and a storage capacitor. Also, when a gate line is selected from among the plurality of gate lines GLl to GLn, TFTs of pixels PX connected to the selected gate line may be turned on, and then a source driver 200 may apply data voltages to the plurality of data lines DLl to DLm. A data voltage may be applied to the liquid crystal capacitor and the storage capacitor via a TFT of a corresponding pixel PX, and the liquid crystal capacitor and the storage capacitor may be driven by the data voltage, whereby an image may be displayed. The timing controller 100 may output a first control signal CTRLl to the source driver 200, and may output a second control signal CTRL2 to the gate driver 300. The first control signal CTRLl may include a polarity control signal, and the second control signal CTRL2 may include a gate timing signal.); a gate driver (Kim, see 300 in figure 1) electrically connected to the plurality of gate lines (Kim, see CL1 through CLn in figure 1) and a timing controller configured to control operation timing of the data driver and the gate driver (Kim, see paragraph [0032], where Kim discloses that the timing controller 100 may control all operations of the display driving circuit 1100. For example, the timing controller 100 may control elements (for example, the source driver 200 and the gate driver 300) of the display driving circuit 1100 so that the display panel 1200 displays an image corresponding to the image data I_DATA received from the outside), and to generate the polarity control signal to control polarities of the plurality of pixels (Kim, see paragraph [0004], where Kim discloses that a timing controller configured to output a polarity control signal representing the polarity of the data voltage corresponding to each of the plurality of horizontal lines, the polarity control signal having a value that is inverted according to n (where n is a positive integer) horizontal line units), wherein the display panel (Kim, see 1200 in figure 1), causing the polarities of the pixels in the first pixel area and the pixels in the second pixel area to be inverted (Kim, see figure 5).
Kim differs from the claimed subject matter in that Kim does not explicitly disclose plurality of gate lines configured to output a gate pulse synchronized with the data voltage and a first pixel area configured to display an image at a first refresh rate; and a second pixel area configured to display an image at a second refresh rate lower than the first refresh rate, and wherein during a frame period in which pixel data is updated for the pixels in the second pixel area, the polarity of the data voltage is inverted.
However in an analogous art, Hur discloses a plurality of gate lines configured to output a gate pulse synchronized with the data voltage (Hur, see paragraph [0035], where Hur discloses generating a data voltage based on the output image data by the data driver to apply the data voltage to the data line; and applying gate-on voltage pulses to k adjacent gate lines by the gate driver corresponding to respective image data of the output image data) and a first pixel area configured to display an image at a first refresh rate; and a second pixel area configured to display an image at a second refresh rate lower than the first refresh rate (Hur, see paragraph [0035], where Hur discloses generating output image data by the signal controller by either reducing vertical resolution of input image data of one frame by 1/k (k is a natural number) or receiving input image data with its vertical resolution reduced by 1/k and processing the input image data to generate output image data; generating a data voltage based on the output image data by the data driver to apply the data
voltage to the data line; and applying gate-on voltage pulses to k adjacent gate lines by the gate driver corresponding to respective image data of the output image data, wherein the output image data corresponding to some pixel rows of the output image data are shifted to left or right by at least one pixel and are output to the data driver in a first frame), and wherein during a frame period in which pixel data is updated for the pixels in the second pixel area (Hur, see paragraph [0035], where Hur discloses applying gate-on voltage pulses to k adjacent gate lines by the gate driver corresponding to respective image data of the output image data, wherein the output image data corresponding to some pixel rows of the output image data are shifted to left or right by at least one
pixel and are output to the data driver in a first frame), the polarity of the data voltage is inverted (Hur, see paragraph [0180], where Hur discloses that the LCD, when polarities of the data
voltages V d with respect to the common voltage V com are constant for every frame, the polarities of the data voltages Vd may be reversed for every frame to remove a residual image that can occur due to a DC bias generated in the liquid crystal layer, and column inversion driving in which the polarities of the data voltages Vd applied to the adjacent pixel column are inverted may be performed).
It would have been obvious to one of ordinary skill in the art to modify the invention of Kim with Hur. One would be motivated to modify Kim by disclosing plurality of gate lines configured to output a gate pulse synchronized with the data voltage and a first pixel area configured to display an image at a first refresh rate; and a second pixel area configured to display an image at a second refresh rate lower than the first refresh rate, and wherein during a frame period in which pixel data is updated for the pixels in the second pixel area, the polarity of the data voltage is inverted as taught by Hur and thereby improving a response speed of the pixel and reducing crosstalk between adjacent frames (Hur, see paragraph [0019]).
As to Claim 2:
Kim in view of Hur discloses that the display device of claim 1, wherein, during a frame period in which pixel data is updated for the pixels in the second pixel area, the polarities of the pixels in the first pixel area and the pixels in the second pixel area are inverted (Kim, see figure 5).
As to Claim 3:
Kim in view of Hur discloses that the display device of claim 1, wherein, during a frame period in which pixel data is updated for the pixels in the first pixel area and the second pixel area, the polarities of the pixels in the first pixel area and the second pixel area are maintained (Kim, see paragraph [0064],where Kim discloses that the source driver 200 may generate the second timing pulse signal TP2 so as not to change a total time (i.e., 2TH) allocated to horizontal lines (for example, the Nth to
N +1th horizontal lines or the N + 2th to N +3th horizontal lines) having the same polarity. Thus, a total time allocated to positive horizontal lines and a total time allocated to negative horizontal lines may be the same in the first timing pulse signal TPl and the second timing pulse signal TP2).
As to Claim 4:
Kim in view of Hur discloses that the display device of claim 1, wherein, during a frame period in which pixel data is updated only in the first pixel area, the polarities of the pixels in the first pixel area and the second pixel area are maintained (Kim, see paragraph [0064],where Kim discloses that the source driver 200 may generate the second timing pulse signal TP2 so as not to change a total time (i.e., 2TH) allocated to horizontal lines (for example, the Nth to N +1th horizontal lines or the N + 2th to N +3th horizontal lines) having the same polarity. Thus, a total time allocated to positive horizontal lines and a total time allocated to negative horizontal lines may be the same in the first timing pulse signal TPl and the second timing pulse signal TP2).
As to Claim 7:
Kim in view of Hur discloses that the display device of claim 1, wherein a driving frequency of pixels arranged in the second pixel area is less than a driving frequency of pixels arranged in the first pixel area (Kim, see paragraph [0121], where Kim discloses that an operating frequency of an interface between the timing controller 100 and the source driver 200 may increase. Referring to FIG. 12, it can be seen that the end of a data charging time of an Nth horizontal line (or a rising edge of a pulse of an N+l th horizontal line) is included in a horizontal blank period HBP
of the packet data PD2. Therefore, driving of the display panel 1200 may be actively performed by the source driver 200).
As to Claim 8:
Kim in view of Hur discloses that the display device of claim 1, wherein a polarity inversion frequency of pixels arranged in the second pixel area is substantially equal to a polarity inversion frequency of pixels arranged in the first pixel area Kim, see paragraph [0064],where Kim discloses that the source driver 200 may generate the second timing pulse signal TP2 so as not to change a total time (i.e., 2TH) allocated to horizontal lines (for example, the Nth to N +1th horizontal lines or the N + 2th to N +3th horizontal lines) having the same polarity. Thus, a total time allocated to positive horizontal lines and a total time allocated to negative horizontal lines may be the same in the first timing pulse signal TPl and the second timing pulse signal TP2).
As to Claim 9:
Kim in view of Hur discloses that the display device of claim 1, wherein the plurality of pixels include liquid crystal (Kim, see paragraph [0026], where Kim discloses that the display panel 1200 may include a display unit that displays a real image and may include a display apparatus that receives an image signal electrically transferred thereto to display a two-dimensional (2D) image, such as an organic light emitting diode (OLED) display, a thin film transistor-liquid crystal display (TFT-LCD), a field emission display, and a plasma display panel (PDP) display. However, embodiments are not limited thereto, and the display panel 1200 may be implemented as a different kind of flat panel display or flexible display panel).
As to Claim 10:
Kim in view of Hur discloses that the display device of claim 1, wherein frequencies of the first refresh rate and the second refresh rate are different from each other (Hur, see paragraph [0103], where Hur discloses that when operated in the gate doubling driving, a scanning time for sequentially applying the gate-on voltage Von to the gate lines Gl to Gn of the entire display panel 300 may be reduced by 1/k, that is, 1/2, 1/3, and so on, compared with that operated in the gate doubling-off driving, and therefore the frame rate may be increased by k times, that is, 2 times, 3 times, or more).
As to Claim 11:
Kim et al. discloses a method of driving a display device (Kim, see Abstract, where Kim discloses a display apparatus includes a display panel including a plurality of horizontal lines each including a plurality of pixels, a timing controller configured to output a polarity control signal representing a polarity corresponding to each of the plurality of horizontal lines and having a value inverted by n horizontal line units, and a source driver configured to generate a timing pulse signal sequentially representing a data charging time of each of the plurality of horizontal lines and to output a data voltage, having a polarity corresponding to each of the plurality of horizontal lines, to the display panel on the basis of the timing pulse signal. When a value of the polarity control signal is inverted, the source driver generates the timing pulse signal including a data charging time corresponding to a count value obtained by counting a number of horizontal lines after a polarity is inverted), the method comprising: driving pixels in a first pixel area of a screen of the display device Kim, see paragraph [0032], where Kim discloses that the timing controller 100 may control all operations of the display driving circuit 1100. For example, the timing controller 100 may control elements (for example, the source driver 200 and the gate driver 300) of the display driving circuit 1100 so that the display panel 1200 displays an image corresponding to the image data I_DATA received from the outside) at a first driving frequency to display images in the first pixel area at a first refresh rate (Kim, see paragraph [0121], where Kim discloses that an operating frequency of an interface between the timing controller 100 and the source driver 200 may increase. Referring to FIG. 12, it can be seen that the end of a data charging time of an Nth horizontal line (or a rising edge of a pulse of an N+l th horizontal line) is included in a horizontal blank period HBP
of the packet data PD2. Therefore, driving of the display panel 1200 may be actively performed by the source driver 200).
Kim differs from the claimed subject matter in that Kim does not explicitly disclose driving pixels of a second pixel area of the screen at a second driving frequency to display images in the second pixel area at a second refresh rate lower than the first refresh rate; and inverting polarities of the pixels in the first pixel area and the pixels in the second pixel area during a frame period in which pixel data is updated for the pixels in the second pixel area.
However in an analogous art, Hur discloses driving pixels of a second pixel area of the screen at a second driving frequency to display images in the second pixel area at a second refresh rate lower than the first refresh rate (Hur, see paragraph [0103], where Hur discloses that when operated in the gate doubling driving, a scanning time for sequentially applying the gate-on voltage Von to the gate lines Gl to Gn of the entire display panel 300 may be reduced by 1/k, that is, 1/2, 1/3, and so on, compared with that operated in the gate doubling-off driving, and therefore the frame rate may be increased by k times, that is, 2 times, 3 times, or more); and inverting polarities (Hur, see paragraph [0180], where Hur discloses that the LCD, when polarities of the data voltages V d with respect to the common voltage V com are constant for every frame, the polarities of the data voltages Vd may be reversed for every frame to remove a residual image that can occur due to a DC bias generated in the liquid crystal layer, and column inversion driving in which the polarities of the data voltages Vd applied to the adjacent pixel column are inverted may be performed) of the pixels in the first pixel area and the pixels in the second pixel area (Hur, see paragraph [0035], where Hur discloses applying gate-on voltage pulses to k adjacent gate lines by the gate driver corresponding to respective image data of the output image data, wherein the output image data corresponding to some pixel rows of the output image data are shifted to left or right by at least one pixel and are output to the data driver in a first frame) during a frame period in which pixel data is updated for the pixels in the second pixel area (Hur, see paragraph [0035], where Hur discloses applying gate-on voltage pulses to k adjacent gate lines by the gate driver corresponding to respective image data of the output image data, wherein the output image data corresponding to some pixel rows of the output image data are shifted to left or right by at least one pixel and are output to the data driver in a first frame).
It would have been obvious to one of ordinary skill in the art to modify the invention of Kim with Hur. One would be motivated to modify Kim by disclosing driving pixels of a second pixel area of the screen at a second driving frequency to display images in the second pixel area at a second refresh rate lower than the first refresh rate; and inverting polarities of the pixels in the first pixel area and the pixels in the second pixel area during a frame period in which pixel data is updated for the pixels in the second pixel area as taught by Hur and thereby improving a response speed of the pixel and reducing crosstalk between adjacent frames (Hur, see paragraph [0019]).
As to Claim 12:
Kim in view of Hur discloses that the method of claim 11, further comprising maintaining polarities of the pixels in the first pixel area and the second pixel area during another frame period in which pixel data is updated for the pixels in the first pixel area and the second pixel area (Kim, see figure 5).
As to Claim 13:
Kim in view of Hur discloses that the method of claim 12, further comprising maintaining polarities of the pixels in the first pixel area and the second pixel area during a frame period in which pixel data is updated only in the first pixel area (Kim, see paragraph [0064],where Kim discloses that the source driver 200 may generate the second timing pulse signal TP2 so as not to change a total time (i.e., 2TH) allocated to horizontal lines (for example, the Nth to N +1th horizontal lines or the N + 2th to N +3th horizontal lines) having the same polarity. Thus, a total time allocated to positive horizontal lines and a total time allocated to negative horizontal lines may be the same in the first timing pulse signal TPl and the second timing pulse signal TP2).
As to Claim 15:
Kim in view of Hur discloses that the method of claim 11, further comprising controlling a driving frequency of the pixels arranged in the second pixel area to be less than a driving frequency of the pixels arranged in the first pixel area (Kim, see paragraph [0121], where Kim discloses that an operating frequency of an interface between the timing controller 100 and the source driver 200 may increase. Referring to FIG. 12, it can be seen that the end of a data charging time of an Nth horizontal line (or a rising edge of a pulse of an N+l th horizontal line) is included in a horizontal blank period HBP of the packet data PD2. Therefore, driving of the display panel 1200 may be actively performed by the source driver 200).
As to Claim 16:
Kim in view of Hur discloses that the method of claim 11, further comprising controlling a polarity inversion frequency of the pixels arranged in the second pixel area to be substantially equal to a polarity inversion frequency of the pixels arranged in the first pixel area (Kim, see paragraph [0064],where Kim discloses that the source driver 200 may generate the second timing pulse signal TP2 so as not to change a total time (i.e., 2TH) allocated to horizontal lines (for example, the Nth to N +1th horizontal lines or the N + 2th to N +3th horizontal lines) having the same polarity. Thus, a total time allocated to positive horizontal lines and a total time allocated to negative horizontal lines may be the same in the first timing pulse signal TPl and the second timing pulse signal TP2).
Allowable Subject Matter
Claims 5, 6 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Referring to claim 5, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “wherein the data driver is configured to: output the data voltage during a refresh period of a frame period in which pixel data is updated in the first pixel area and the second pixel area; and not output the data voltage during a skip period in which pixel data is not updated”.
Referring to claim 6, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “wherein the data driver is configured to: output the data voltage having a first polarity through odd-numbered output terminals and output the data voltage having a second polarity through even-numbered output terminals; and invert the polarity of the data voltage output through the odd-numbered output terminals and the polarity of the data voltage output through the even-numbered output terminals in response to the polarity control signal during the frame periods in which pixel data is updated for the pixels in the second pixel area”.
Referring to claim 14, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “outputting a data voltage from a data driver of the display device during a refresh period of a frame period in which the pixel data is updated in the first pixel area and the second pixel area; and controlling the data driver so that the data voltage is not output from the data driver during a skip period in which the pixel data is not updated”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to
applicant's disclosure. Kim (US 20090310077 A1) relates to a liquid crystal display device and a driving method thereof for reducing heat and electric consumption power of the data driving circuit. The exemplary embodiment includes: a liquid crystal display panel including a plurality of data lines crossing a plurality of gate lines and liquid crystal cells arranged in a matrix e; a timing controller generating a polarity control signal, deciding if a predetermined weak pattern data is input, and shifting a phase of the polarity control signal in a next frame period following a frame showing the weak pattern data when the weak pattern data is input; a data driving circuit reversing the polarity of the data voltage in response to the polarity control signal and supplying to the data lines; and a gate driving circuit supplying a gate pulse to the gate lines sequentially.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NELSON ROSARIO whose telephone number is (571)270-1866. The examiner can normally be reached on Monday through Friday, 7:30am- 5:00pm EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached on (571) 270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NELSON M ROSARIO/Primary Examiner, Art Unit 2624
