DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in the Republic of Korea on 12/24/2020.
Information Disclosure Statement
The Information Disclosure Statement has been considered and placed in the record on file and is in compliance with USPTO requirements.
Drawings
The Drawings have been considered and placed in the record on file and are in compliance with USPTO requirements.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 3-7, and 9-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 5-13, and 15-20 of U.S. Patent No. 12,573,346. Although the claims at issue are not identical, they are not patentably distinct from each other.
Application 19/438,786
Patent No. 12,573,346
1. A display apparatus, comprising:
a substrate including an active area and an inactive area adjacent to the active area, the active area in which an array of pixels is formed;
a driver IC disposed on the substrate in a first area, the driver IC having a first side extending along a first direction;
a plurality of pads disposed on the substrate in the first area, the plurality of pads including a first pad for low potential power disposed on a left side of the driver IC, a second pad for low potential power disposed on a right side of the driver IC, a third pad for high potential power disposed on the left side of the driver IC, and a fourth pad for high potential power disposed on the right side of the driver IC;
a low potential power line disposed on the substrate, the low potential power line electrically connected to at least one of the first pad and the second pad and at least a portion of the low potential power line extending a second direction different from the first direction; and
a high potential power line disposed on the substrate, the high potential power line electrically connected to at least one of the third pad and the fourth pad and at least a portion of the high potential power line disposed between the driver IC and the active area.
1. A display apparatus, comprising:
a substrate including an active area and an inactive area surrounding the active area, the active area in which an array of pixels is formed;
a driver IC disposed on a side of the substrate;
a gate driver disposed on a side of the substrate;
a pad for low-potential power disposed on a left side and a right side of the driver IC;
a pad for high-potential power disposed on the left side and the right side of the driver IC;
a low potential power line disposed on the substrate, the low potential power line surrounding at least three sides of the active area; and
a high potential power line disposed on the substrate, at least a portion of the high potential power line being parallel to the low potential power line.
Application 19/438,786
Claim 3
Claim 4
Claim 5
Claim 6
Claim 7
Claim 9
Patent No. 12,573,346
Claim 1
Claims 2, 3, and 6
Claim 9
Claim 10
Claim 12
Claim 15
Application 19/438,786
Claim 10
Claim 11
Claim 12
Claim 13
Claim 14
Claim 15
Patent No. 12,573,346
Claims 2 and 8
Claims 3 and 5
Claims 3 and 6
Claims 3 and 7
Claim 16
Claim 17
Application 19/438,786
Claim 16
Claim 17
Claim 18
Claim 19
Claim 20
Patent No. 12,573,346
Claim 18
Claim 19
Claims 10 and 11
Claims 12 and 13
Claim 20
Claims 1, 3, 4, and 9-17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-10 of U.S. Patent No. 12,217,700. Although the claims at issue are not identical, they are not patentably distinct from each other.
Application 19/438,786
Patent No. 12,217,700
1. A display apparatus, comprising:
a substrate including an active area and an inactive area adjacent to the active area, the active area in which an array of pixels is formed;
a driver IC disposed on the substrate in a first area, the driver IC having a first side extending along a first direction;
a plurality of pads disposed on the substrate in the first area, the plurality of pads including a first pad for low potential power disposed on a left side of the driver IC, a second pad for low potential power disposed on a right side of the driver IC, a third pad for high potential power disposed on the left side of the driver IC, and a fourth pad for high potential power disposed on the right side of the driver IC;
a low potential power line disposed on the substrate, the low potential power line electrically connected to at least one of the first pad and the second pad and at least a portion of the low potential power line extending a second direction different from the first direction; and
a high potential power line disposed on the substrate, the high potential power line electrically connected to at least one of the third pad and the fourth pad and at least a portion of the high potential power line disposed between the driver IC and the active area.
1. A display apparatus, comprising:
a substrate;
a driver IC disposed on a side of the substrate; and
a gate driver disposed on a side of the substrate;
a pad for low-potential power disposed on a left side and a right side of the driver IC; and
a pad for high-potential power disposed on the left side and the right side of the driver IC,
wherein the gate driver includes: a transistor T1 including a gate electrode electrically connected to a node Q and a capacitor CQ, and electrically connected between an input terminal of a gate low voltage and an output node; a transistor T2 including a gate electrode electrically connected to a node QB and electrically connected between an input terminal of a gate high voltage and the output node; a capacitor CB electrically connected between the input terminal of the gate high voltage and the gate electrode of the transistor T2; a transistor T3 including a gate electrode electrically connected to an input terminal of a clock signal, and electrically connected between an input terminal of a start signal and the node Q; a transistor T4 electrically connected the input terminal of the gate high voltage; a transistor T5 electrically connected between the input terminal of the clock signal and the transistor T2; a transistor T6 electrically connected between the input terminal of the gate high voltage and the transistor T2; and a transistor TA electrically connected between the transistor T3 and the transistor T1.
2. The display apparatus according to claim 1, further comprising:
a low potential power line disposed on the left side and the right side of the driver IC; and
a high potential power line disposed on the left side and the right side of the driver IC and a lower side of the driver IC.
Application 19/438,786
Claim 3
Claim 4
Claim 9
Claim 10
Claim 11
Claim 12
Patent No. 12,217,700
Claim 2
Claims 1, 2, and 6
Claim 2
Claim 4
Claim 5
Claim 6
Application 19/438,786
Claim 13
Claim 14
Claim 15
Claim 16
Claim 17
Patent No. 12,217,700
Claim 7
Claims 2 and 3
Claim 8
Claim 9
Claim 10
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER J KOHLMAN whose telephone number is (571)270-5503. The examiner can normally be reached 9-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, NITIN PATEL can be reached at (571) 272-7677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER J KOHLMAN/Primary Examiner, Art Unit 2628
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