Prosecution Insights
Last updated: October 27, 2026
Application No. 19/442,331

DISPLAY MODULE AND ELECTRONIC DEVICE

Non-Final OA §102§103
Filed
Jan 07, 2026
Priority
Mar 20, 2025 — RE 10-2025-0035956
Examiner
FIGUEROA-GIBSON, GLORYVID
Art Unit
2628
Tech Center
2600 — Communications
Assignee
Samsung Display Co., Ltd.
OA Round
1 (Non-Final)
66%
Grant Probability
Favorable
1-2
OA Rounds
1y 9m
Est. Remaining
77%
With Interview

Examiner Intelligence

Grants 66% — above average
66%
Career Allowance Rate
248 granted / 375 resolved
+4.1% vs TC avg
Moderate +11% lift
Without
With
+10.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
14 currently pending
Career history
394
Total Applications
across all art units

Statute-Specific Performance

§101
2.3%
-37.7% vs TC avg
§103
48.8%
+8.8% vs TC avg
§102
21.0%
-19.0% vs TC avg
§112
22.9%
-17.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 375 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Examiner cites particular columns or paragraphs, and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim Objections Claim 1 is objected to because of the following informalities: the claim recites “a plurality of second scan lines of the plurality of scan lines” in line 7, which appears to be “a second plurality of scan lines of the plurality of scan lines”, for consistency in the claims; and “the second drive frequency” in line 11, which appears to be “a second drive frequency”. Appropriate corrections are required. Claims 2-10 are objected based on their dependence from claim 1. In addition, claim 6 is objected to because of the following informalities: the claim recites “set a drive frequency of each of the plurality of second groups differently” in line 3, which appears to be “set the fourth drive frequency of each of the plurality of second groups differently”, for consistency in the claims. Appropriate correction is required. Claim 7 is additionally objected based on its dependence from claim 6. Claim 11 is objected to because of the following informalities: the claim recites “the second drive frequency” in line 17, which appears to be “a second drive frequency”. Appropriate correction is required. Claims 12-20 are objected based on their dependence from claim 1. In addition, claim 16 is objected to because of the following informalities: the claim recites “set a drive frequency of each of the plurality of second groups differently” in line 3, which appears to be “set the fourth drive frequency of each of the plurality of second groups differently”, for consistency in the claims. Appropriate correction is required. Claim 17 is additionally objected based on its dependence from claim 6. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-9 and 11-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US 2021/0027720), hereinafter Park ‘720. Regarding claim 1, Park ‘720 discloses a display module (see display device 100 in Fig. 1; para[0049]) comprising: a display panel including a plurality of pixels respectively connected to a plurality of data lines and a plurality of scan lines (as shown in Fig. 1, “display panel 110 may include a plurality of data lines, a plurality of scan lines, and a plurality of pixels PX connected to the plurality of data lines and the plurality of scan lines”; para[0054]); a data drive circuit configured to drive the plurality of data lines (see data driver 120 included in panel driver 190, as shown in Fig. 1; para[0057]); a first scan drive circuit configured to drive a first plurality of scan lines of the plurality of scan lines (see scan driver 130 included in panel driver 190, as shown in Fig. 1, performing as the claimed first scan drive circuit, and which “may be integrated with or formed in a peripheral portion of the display panel 110”, and “may be implemented with one or more integrated circuits”; “the scan driver 130 may provide the scan signals SS to the… partial panel region PPR1 at the… driving frequency DF1, may provide the scan signals SS to the… partial panel region PPR2 at the… driving frequency DF2, and may provide the scan signals SS to the boundary portion BP at the… driving frequency DF3” through scan lines SL as shown in Fig. 14; para[0058]; para[0070]; para[0086]-para[0087]); and a second scan drive circuit configured to drive a plurality of second scan lines of the plurality of scan lines (see scan driver 130 included in panel driver 190, as shown in Fig. 1, also performing as the claimed second scan drive circuit, and which “may be integrated with or formed in a peripheral portion of the display panel 110”, and “may be implemented with one or more integrated circuits”; “the scan driver 130 may provide the scan signals SS to the… partial panel region PPR1 at the… driving frequency DF1, may provide the scan signals SS to the… partial panel region PPR2 at the… driving frequency DF2, and may provide the scan signals SS to the boundary portion BP at the… driving frequency DF3” through scan lines SL as shown in Fig. 14; para[0058]; para[0070]; para[0086]-para[0087]), wherein during a multi-frequency mode: the display panel is divided into a first display region driven at a first drive frequency and a second display region driven at the second drive frequency (regarding Figs. 1 and 14, see e.g. the claimed first display region comprising partial panel region PPR2, and the claimed second display region comprising partial panel region PPR1 and boundary portion BP, based on the broadest reasonable interpretation of the claimed limitations; “The panel driver 190 of the display device 100 according to example embodiments may perform multi-frequency driving (MFD) that drives the… partial panel region PPR1 and the… partial panel region PPR2 of the display panel 110 at different first and second driving frequencies DF1 and DF2 respectively”; see e.g. in Fig. 14 “the… driving frequency DF2 for the… partial panel region PPR2 may be determined as about 1 Hz” (claimed first drive frequency), and “the… driving frequency DF1 for the… partial panel region PPR1 may be determined to be… about 120 Hz” (claimed second drive frequency); para[0060]; para[0086]-para[0087]), the first scan drive circuit is configured to set a drive frequency of the first plurality of scan lines in a boundary area of the second display region to a third drive frequency (see e.g. regarding Figs. 1 and 14, “the scan driver 130 may… provide the scan signals SS to the boundary portion BP at… driving frequency DF3”; see e.g. in Fig. 14 “driving frequency DF3 for the 1281st through 1284th scan lines SL1281 through SL1284 as about 60 Hz”; para[0051]; para[0060]; para[0070]; para[0086]-para[0087]), and the second scan drive circuit is configured to set a drive frequency of the second plurality of scan lines in the boundary area to a fourth drive frequency (see e.g. regarding Figs. 1 and 14, “the scan driver 130 may… provide the scan signals SS to the boundary portion BP at… driving frequency DF3”; see e.g. in Fig. 14 “driving frequency DF3 for the 1288th and 1289th scan line SL1288 and SL1289 as about 10 Hz”; para[0051]; para[0060]; para[0070]; para[0086]-para[0087]). Regarding claim 2, Park ‘720 discloses all the claim limitations as applied above (claim 1). In addition, Park ‘720 discloses the third drive frequency is different from the fourth drive frequency (see e.g. in Fig. 14 “the… driving frequency DF3 for the 1281st through 1284th scan lines SL1281 through SL1284 as about 60 Hz” and “the… driving frequency DF3 for the 1288th and 1289th scan line SL1288 and SL1289 as about 10 Hz”; para[0051]; para[0060]; para[0070]; para[0086]-para[0087]). Regarding claim 3, Park ‘720 discloses all the claim limitations as applied above (claim 1). In addition, Park ‘720 discloses the third drive frequency is in a range from the first drive frequency to the second drive frequency (as shown in Fig. 14, e.g. drive frequency DF3 of 60 Hz is in a range from the claimed first drive frequency DF2 of 1 Hz to the claimed second drive frequency DF1 of 120 Hz), and wherein the fourth drive frequency is in a range from the first drive frequency to the second drive frequency (as shown in Fig. 14, drive frequency DF3 of 10 Hz is in a range from the claimed first drive frequency DF2 of 1 Hz to the claimed second drive frequency DF1 of 120 Hz). Regarding claim 4, Park ‘720 discloses all the claim limitations as applied above (claim 3). In addition, Park ‘720 discloses the first scan drive circuit is configured to divide the first plurality of scan lines in the boundary area into a plurality of first groups (as shown in Fig. 14, the panel driver 190 including the scan driver 130 drives/divides scan lines in groups in the boundary portion BP), and set the third drive frequency of each of the plurality of first groups differently (as shown in Fig. 14, e.g. “the… driving frequency DF3 for the 1281st through 1284th scan lines SL1281 through SL1284 as about 60 Hz,… the… driving frequency DF3 for the 1285th through 1287th scan lines SL1285 through SL1287 as about 30 Hz,… the… driving frequency DF3 for the 1288th and 1289th scan line SL1288 and SL1289 as about 10 Hz, and… the… driving frequency DF3 for the 1290th scan line SL1290 as about 5 Hz”; para[0086]-para[0087]). Regarding claim 5, Park ‘720 discloses all the claim limitations as applied above (claim 4). In addition, Park ‘720 discloses, based on the second drive frequency being higher than the first drive frequency, the third drive frequency of each of the plurality of first groups increases in a stepwise manner as distance between the first display region and each of the first groups increases (as shown in Fig. 14, “panel driver 190 may drive the… partial panel region PPR1 at the… driving frequency DF1, may drive the… partial panel region PPR2 at the… driving frequency DF2, and may drive the boundary portion BP at the… driving frequency DF3 that gradually decreases per one or more scan lines in a direction from the… partial panel region PPR1 driven at the relatively higher… driving frequency DF1 to the… partial panel region PPR2 driven at the relatively lower… driving frequency DF2”; e.g. given “the… driving frequency DF1 for the… partial panel region PPR1… determined to be… of about 120 Hz, and the… driving frequency DF2 for the… partial panel region PPR2… determined as about 1 Hz”, setting “the… driving frequency DF3 for the 1281st through 1284th scan lines SL1281 through SL1284 as about 60 Hz,… the… driving frequency DF3 for the 1285th through 1287th scan lines SL1285 through SL1287 as about 30 Hz,… the… driving frequency DF3 for the 1288th and 1289th scan line SL1288 and SL1289 as about 10 Hz, and… the… driving frequency DF3 for the 1290th scan line SL1290 as about 5 Hz”; para[0086]-para[0087]). Regarding claim 6, Park ‘720 discloses all the claim limitations as applied above (claim 3). In addition, Park ‘720 discloses the second scan drive circuit is configured to divide the second plurality of scan lines in the boundary area into a plurality of second groups (as shown in Fig. 14, the panel driver 190 including the scan driver 130 drives/divides scan lines in groups in the boundary portion BP), and set a drive frequency of each of the plurality of second groups differently (as shown in Fig. 14, e.g. “the… driving frequency DF3 for the 1281st through 1284th scan lines SL1281 through SL1284 as about 60 Hz,… the… driving frequency DF3 for the 1285th through 1287th scan lines SL1285 through SL1287 as about 30 Hz,… the… driving frequency DF3 for the 1288th and 1289th scan line SL1288 and SL1289 as about 10 Hz, and… the… driving frequency DF3 for the 1290th scan line SL1290 as about 5 Hz”; para[0086]-para[0087]). Regarding claim 7, Park ‘720 discloses all the claim limitations as applied above (claim 6). In addition, Park ‘720 discloses, based on the second drive frequency being higher than the first drive frequency, the fourth drive frequency of each of the plurality of second groups increases in a stepwise manner as distance between the first display region and each of the second groups increases (as shown in Fig. 14, “panel driver 190 may drive the… partial panel region PPR1 at the… driving frequency DF1, may drive the… partial panel region PPR2 at the… driving frequency DF2, and may drive the boundary portion BP at the… driving frequency DF3 that gradually decreases per one or more scan lines in a direction from the… partial panel region PPR1 driven at the relatively higher… driving frequency DF1 to the… partial panel region PPR2 driven at the relatively lower… driving frequency DF2”; e.g. given “the… driving frequency DF1 for the… partial panel region PPR1… determined to be… of about 120 Hz, and the… driving frequency DF2 for the… partial panel region PPR2… determined as about 1 Hz”, setting “the… driving frequency DF3 for the 1281st through 1284th scan lines SL1281 through SL1284 as about 60 Hz,… the… driving frequency DF3 for the 1285th through 1287th scan lines SL1285 through SL1287 as about 30 Hz,… the… driving frequency DF3 for the 1288th and 1289th scan line SL1288 and SL1289 as about 10 Hz, and… the… driving frequency DF3 for the 1290th scan line SL1290 as about 5 Hz”; para[0086]-para[0087]). Regarding claim 8, Park ‘720 discloses all the claim limitations as applied above (claim 1). In addition, Park ‘720 discloses the first plurality of scan lines and the second plurality of scan lines are alternately arranged (as shown in Fig. 14, scan lines SL1 through SL2560 are alternately arranged, based on the broadest reasonable interpretation of the claimed limitations). Regarding claim 9, Park ‘720 discloses all the claim limitations as applied above (claim 1). In addition, Park ‘720 discloses the display panel includes: a display region including the first display region and the second display region (see partial panel region PPR2 and partial panel region PPR1 where pixels are located, as shown in Fig. 1); and a non-display area in which the first scan drive circuit and the second scan drive circuit are arranged (see region where scan driver 130 is arranged being a non-display region, as shown in Fig. 1). Regarding claim 11, Park ‘720 discloses an electronic device (see electronic device 1100 in Fig. 19; para[0098]; para[0104]) comprising: a processor configured to provide an image signal and a control signal (see processor 1110 in Fig. 19 configured to provide input image data IDAT and control signal CTRL to controller 140 of display device 100 in Fig. 1 (1160 in Fig. 19); para[0059]; para[0098]; para[0100]; para[0104]); and a display module configured to determine an operation mode based on the image signal and the control signal, and display an image according to the operation mode (display device 100 in Fig. 1 (1160 in Fig. 19) including panel driver 190, which includes “a still image detector 150, a driving frequency decider 160, a boundary portion setter 170 and a data output unit 180”; “still image detector 150 may receive the input image data IDAT at the input frame frequency IFF, may divide the input image data IDAT into first partial image data PDAT1 for the first partial panel region PPR1 and second partial image data PDAT2 for the second partial panel region PPR2, and may determine whether each of the first and second partial image data PDAT1 and PDAT2 represent a still image”; “the driving frequency decider 160 may set the first driving frequency DF1 for the first partial panel region PPR1 according to whether the first partial image data PDAT1 represent the still image, and may set the second driving frequency DF2 for the second partial panel region PPR2 according to whether the second partial image data PDAT2 represent the still image”, thus determining an operation mode based on the image signal and the control signal, to display an image accordingly; para[0049]; para[0060]; para[0061]; para[0063]; para[0098]; para[0104]), wherein the display module includes: a display panel including a plurality of pixels respectively connected to a plurality of data lines and a plurality of scan lines (as shown in Fig. 1, “display panel 110 may include a plurality of data lines, a plurality of scan lines, and a plurality of pixels PX connected to the plurality of data lines and the plurality of scan lines”; para[0054]); a data drive circuit configured to drive the plurality of data lines (see data driver 120 included in panel driver 190, as shown in Fig. 1; para[0057]); a first scan drive circuit configured to drive a first plurality of scan lines of the plurality of scan lines (see scan driver 130 included in panel driver 190, as shown in Fig. 1, performing as the claimed first scan drive circuit, and which “may be integrated with or formed in a peripheral portion of the display panel 110”, and “may be implemented with one or more integrated circuits”; “the scan driver 130 may provide the scan signals SS to the… partial panel region PPR1 at the… driving frequency DF1, may provide the scan signals SS to the… partial panel region PPR2 at the… driving frequency DF2, and may provide the scan signals SS to the boundary portion BP at the… driving frequency DF3” through scan lines SL as shown in Fig. 14; para[0058]; para[0070]; para[0086]-para[0087]); a second scan drive circuit configured to drive a second plurality of scan lines of the plurality of scan lines (see scan driver 130 included in panel driver 190, as shown in Fig. 1, also performing as the claimed second scan drive circuit, and which “may be integrated with or formed in a peripheral portion of the display panel 110”, and “may be implemented with one or more integrated circuits”; “the scan driver 130 may provide the scan signals SS to the… partial panel region PPR1 at the… driving frequency DF1, may provide the scan signals SS to the… partial panel region PPR2 at the… driving frequency DF2, and may provide the scan signals SS to the boundary portion BP at the… driving frequency DF3” through scan lines SL as shown in Fig. 14; para[0058]; para[0070]; para[0086]-para[0087]), and a drive controller configured to control the data drive circuit, the first scan drive circuit, and the second scan drive circuit based on the image signal and the control signal (see controller 140 in Fig. 1; para[0059]), wherein based on the operating mode being a multi-frequency mode: the display panel is divided into a first display region driven at a first drive frequency and a second display region driven at the second drive frequency (regarding Figs. 1 and 14, see e.g. the claimed first display region comprising partial panel region PPR2, and the claimed second display region comprising partial panel region PPR1 and boundary portion BP, based on the broadest reasonable interpretation of the claimed limitations; “The panel driver 190 of the display device 100 according to example embodiments may perform multi-frequency driving (MFD) that drives the… partial panel region PPR1 and the… partial panel region PPR2 of the display panel 110 at different first and second driving frequencies DF1 and DF2 respectively”; see e.g. in Fig. 14 “the… driving frequency DF2 for the… partial panel region PPR2 may be determined as about 1 Hz” (claimed first drive frequency), and “the… driving frequency DF1 for the… partial panel region PPR1 may be determined to be… about 120 Hz” (claimed second drive frequency); para[0060]; para[0086]-para[0087]), the first scan drive circuit is configured to set a drive frequency of the first plurality of scan lines in a boundary area of the second display region to a third drive frequency (see e.g. regarding Figs. 1 and 14, “the scan driver 130 may… provide the scan signals SS to the boundary portion BP at… driving frequency DF3”; see e.g. in Fig. 14 “driving frequency DF3 for the 1281st through 1284th scan lines SL1281 through SL1284 as about 60 Hz”; para[0051]; para[0060]; para[0070]; para[0086]-para[0087]), and the second scan drive circuit is configured to set a drive frequency of the second plurality of scan lines in the boundary area to a fourth drive frequency (see e.g. regarding Figs. 1 and 14, “the scan driver 130 may… provide the scan signals SS to the boundary portion BP at… driving frequency DF3”; see e.g. in Fig. 14 “driving frequency DF3 for the 1288th and 1289th scan line SL1288 and SL1289 as about 10 Hz”; para[0051]; para[0060]; para[0070]; para[0086]-para[0087]). Regarding claim 12, it is analogous to claim 8, and therefore it is rejected for the same reasons as claim 8 above. Regarding claim 13, it is analogous to claim 2, and therefore it is rejected for the same reasons as claim 2 above. Regarding claim 14, it is analogous to claim 4, and therefore it is rejected for the same reasons as claim 4 above. Regarding claim 15, it is analogous to claim 5, and therefore it is rejected for the same reasons as claim 5 above. Regarding claim 16, it is analogous to claim 6, and therefore it is rejected for the same reasons as claim 6 above. Regarding claim 17, it is analogous to claim 7, and therefore it is rejected for the same reasons as claim 7 above. Regarding claim 18, it is analogous to claim 3, and therefore it is rejected for the same reasons as claim 3 above. Regarding claim 19, it is analogous to claim 9, and therefore it is rejected for the same reasons as claim 9 above. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 10 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2021/0027720), hereinafter Park ‘720, in view of Park et al. (US 2017/0154598), hereinafter Park ‘598. Regarding claim 10, Park ‘720 discloses all the claim limitations as applied above (claim 1). However, Park ‘720 does not appear to expressly disclose the first scan drive circuit and the second scan drive circuit are spaced apart from each other with the first display region and the second display region interposed therebetween. Park ‘598 discloses a first scan drive circuit and a second scan drive circuit spaced apart from each other with a first display region and a second display region interposed therebetween (see in Fig. 1 gate drivers 213a/223a and 213b/223b spaced apart from each other with display areas UDA, LDA, BDA (boundary) interposed therebetween). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Park ‘720’s invention, with the teachings in Park ‘598’s invention, to have the first scan drive circuit and the second scan drive circuit are spaced apart from each other with the first display region and the second display region interposed therebetween, for the advantage of separately driving lines to decrease signal delays in large panels (para[0037]). Regarding claim 20, it is analogous to claim 10, and therefore it is rejected for the same reasons as claim 10 above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to GLORYVID FIGUEROA-GIBSON whose telephone number is (571)272-5506. The examiner can normally be reached on 9am-5pm, Monday -Friday, Eastern Time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nitin Patel can be reached on 571-272-7677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /GLORYVID FIGUEROA-GIBSON/Patent Examiner, Art Unit 2628 /NITIN PATEL/Supervisory Patent Examiner, Art Unit 2628
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Prosecution Timeline

Jan 07, 2026
Application Filed
Sep 29, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
66%
Grant Probability
77%
With Interview (+10.6%)
2y 6m (~1y 9m remaining)
Median Time to Grant
Low
PTA Risk
Based on 375 resolved cases by this examiner. Grant probability derived from career allowance rate.

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