DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6-8, 10-12, 15-16, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al (US 2020/0111403 A1).
Claim 1, Kim (Fig. 1-14) discloses a pixel circuit (Fig. 9; wherein figure shows driving circuit for light emitting element), comprising a first transistor (311; Fig. 9), a second transistor (321; Fig. 9), a third transistor (323; Fig. 9), and a light-emitting element (200; Fig. 9), wherein:
a first electrode of the first transistor (311; Fig. 9) and a first electrode of the second transistor (321; Fig. 9) are configured to receive a power signal (VDD; Fig. 9), a second electrode of the first transistor (311; Fig. 9) is connected to (332; Fig. 9; Paragraph [0160]; wherein discloses “The seventh transistor 332 may be turned on or off according to the control signal Emi, and electrically connect the PAM driving circuit 310 and the light emitting device 200”) the light-emitting element (200; Fig. 9), and a gate electrode (Node C; Fig. 9) of the first transistor (311; Fig. 9) is connected to (Paragraph [0170]) a second electrode of the second transistor (321; Fig. 9), a gate electrode (Node A; Fig. 9) of the second transistor (321; Fig. 9) and a second electrode (Node A; Fig. 9) of the third transistor (323; Fig. 9);
a first electrode of the third transistor (323; Fig. 9) is configured to receive a reset signal (Paragraph [0170]; wherein discloses receiving an initial voltage of -5V), and a gate electrode of the third transistor (323; Fig. 9) is configured to receive a reset control signal (Ref; Fig. 9 and 10);
the first transistor (311; Fig. 9) is configured to provide a driving signal (Paragraph [0113]) to the light-emitting element (200; Fig. 9), the second transistor (321; Fig. 9) is configured to provide a light emission duration control signal (Paragraph [0114]) to the first transistor (311; Fig. 9) to control a light emission duration (Paragraph [0115]) of the light-emitting element (200; Fig. 9), and the third transistor (323; Fig. 9) is configured to provide the reset signal (Paragraph [0170]; wherein discloses receiving an initial voltage of -5V) to the gate electrode (Node A; Fig. 9) of the second transistor (321; Fig. 9) and the gate electrode (Node C; Fig. 9) of the first transistor (311; Fig. 9) in response to the reset control signal (Ref; Fig. 9 and 10) received at the gate electrode of the third transistor (323; Fig. 9).
Claim 2, Kim (Fig. 1-14) discloses further comprising a first capacitor (313; Fig. 9);
wherein a first electrode of the first capacitor (313; Fig. 9) is connected to the gate electrode (Node C; Fig. 9) of the first transistor (311; Fig. 9), and a second electrode of the first capacitor (313; Fig. 9) is configured to receive the power signal (VDD; Fig. 9).
Claim 3, Kim (Fig. 1-14) discloses further comprising a fourth transistor (312; Fig. 9);
wherein:
a first electrode (Node C; Fig. 9) of the fourth transistor (312; Fig. 9) is connected to the gate electrode (Node C; Fig.9) of the first transistor (311; Fig. 9), a second electrode of the fourth transistor (312; Fig. 9) is connected to the second electrode of the first transistor (311; Fig. 9), and a gate electrode of the fourth transistor (312; Fig. 9) is configured to receive a first compensation control signal (RES; Fig. 9 and 10);
the fourth transistor (312; Fig. 9) is configured to provide threshold compensation (Paragraph [0154]) for the first transistor (311; Fig. 9) in response to the first compensation control signal (RES; Fig. 9 and 10) received at the gate electrode of the fourth transistor (312; Fig. 9).
Claim 4, Kim (Fig. 1-14) discloses further comprising a fifth transistor (322; Fig. 9);
wherein:
a first electrode (Node A; Fig. 9) of the fifth transistor (322; Fig. 9) is connected to the gate electrode (Node A; Fig. 9) of the second transistor (321; Fig. 9), a second electrode of the fifth transistor (322; Fig. 9) is connected to the second electrode of the second transistor (321; Fig. 9) and the second electrode (Paragraph [0170]) of the third transistor (323; Fig. 9), and a gate electrode of the fifth transistor (322; Fig. 9) is configured to receive a first compensation and reset control signal (RES; Fig. 9 and 10; wherein figure shows signal RES is applied during A C Node Initialize and VTH compensate);
the fifth transistor (322; Fig. 9) is configured to, in response to the first compensation and reset control signal (RES; Fig. 9 and 10; wherein figure shows signal RES is applied during A C Node Initialize and VTH compensate) received at the gate electrode of the fifth transistor (322; Fig. 9), provide the reset signal (Paragraph [0170]; wherein discloses an initial voltage) provided by the third transistor (323; Fig. 9) and received at the second electrode of the fifth transistor (322; Fig. 9) to the gate electrode of the second transistor (321; Fig. 9) through the first electrode of the fifth transistor (322; Fig. 9); or
the fifth transistor (322; Fig. 9) is configured to, in response to the first compensation and reset control signal (RES; Fig. 9 and 10; wherein figure shows signal RES is applied during A C Node Initialize and VTH compensate) received at the gate electrode of the fifth transistor (322; Fig. 9), provide threshold compensation (Paragraph [0176]) for the second transistor (321; Fig. 9).
Claim 6, Kim (Fig. 1-14) discloses further comprising a seventh transistor (325; Fig. 9);
wherein:
a first electrode of the seventh transistor (325; Fig. 9) is configured to receive a second data signal (Sig<m>; Fig. 9; Paragraph [0156]), a second electrode of the seventh transistor (325; Fig. 9) is connected (Paragraph [0184]) to the gate electrode of the second transistor (321; Fig. 9), and a gate electrode of the seventh transistor (325; Fig. 9) is configured to receive a second data writing control signal (SPWM(n); Fig. 9 and 10);
the seventh transistor (325; Fig. 9) is configured to write the second data signal (Sig<m>; Fig. 9; Paragraph [0156]) into the gate electrode (Paragraph [0184]) of the second transistor (321; Fig. 9) in response to the second data writing control signal (SPWM(n); Fig. 9 and 10) received at the gate electrode of the seventh transistor (325; Fig. 9).
Claim 7, Kim (Fig. 1-14) discloses further comprising a second capacitor (324; Fig. 9);
wherein:
a first electrode (Node B; Fig. 9) of the second capacitor (324; Fig. 9) is connected to the second electrode (Node B; Fig. 9) of the seventh transistor (325; Fig. 9), and a second electrode (Node A; Fig. 9) of the second capacitor (324; Fig. 9) is connected to the gate electrode (Node A; Fig. 9) of the second transistor (321; Fig. 9);
the second capacitor (324; Fig. 9) is configured to couple (Paragraph [0184]) the second data signal (Sig<m>; Fig. 9) written by the seventh transistor (325; Fig. 9) to the gate electrode (Node A; Fig. 9) of the second transistor (321; Fig. 9).
Claim 8, Kim (Fig. 1-14) discloses further comprising a third capacitor (326; Fig. 9);
wherein:
a first electrode (Node B; Fig. 9) of the third capacitor (326; Fig. 9) is connected to the first electrode (Node B; Fig. 9) of the second capacitor (324; Fig. 9), and a second electrode of the third capacitor (326; Fig. 9) is configured to receive the light emission duration control signal (Vsweep; Fig. 9 and 10);
the third capacitor (326; Fig. 9) is configured to couple the light emission duration control signal (Vsweep; Fig. 9 and 10) received at the second electrode of the third capacitor (Vsweep; Fig. 9 and 10) to the gate electrode (Node A; Fig. 9) of the second transistor (321; Fig. 9) through the second capacitor (324; Fig. 9).
Claim 10, Kim (Fig. 1-14) discloses further comprising a ninth transistor (332; Fig. 9);
wherein:
a first electrode of the ninth transistor (332; Fig. 9) is connected to the first electrode of the first transistor (311; Fig. 9), a second electrode of the ninth transistor (332; Fig. 9) is connected to the light-emitting element (200; Fig. 9), and a gate electrode of the ninth transistor (332; Fig. 9) is configured to receive a second driving control signal (Emi; Fig. 9 and 10);
the ninth transistor (332; Fig. 9) is configured to (Paragraph [160]), in response to the second driving control signal (Emi; Fig. 9 and 10) received at the gate electrode of the ninth transistor (332; Fig. 9), provide the driving signal (Paragraph [0113]) provided by the first transistor (311; Fig. 9) and received at the first electrode of the ninth transistor (332; Fig. 9) to the light-emitting element (200; Fig. 9) through the second electrode of the ninth transistor (332; Fig. 9).
Claim 11, Kim (Fig. 1-14) discloses further comprising a tenth transistor (315; Fig. 9);
wherein:
a first electrode of the tenth transistor (315; Fig. 9) is configured to receive a third data signal (Sig<n>; Fig. 9; Paragraph [0155]), a second electrode (Node D; Fig. 9) of the tenth transistor (315; Fig. 9) is connected to (Paragraph [0155]; wherein discloses “the PAM driving circuit 310 may apply a third voltage corresponding to the sum of the first voltage and the applied PAM data voltage to the gate terminal C of the first driving transistor 311”) the gate electrode (Node C; Fig. 9) of the first transistor (311; Fig. 90, and a gate electrode of the tenth transistor (315; Fig. 9) is configured to receive a third data writing control signal (SPAM; Fig. 9 and 10);
the tenth transistor (315; Fig. 9) is configured to provide the third data signal (Sig<n>; Fig. 9; Paragraph [0155]) into the gate electrode (Node C; Fig. 9) of the first transistor (311; Fig. 9) in response to the third data writing control signal (SPAM; Fig. 9) received at the gate electrode of the tenth transistor (315; Fig. 9).
Claim 12, Kim (Fig. 1-14) discloses further comprising an eleventh transistor (322; Fig. 9);
wherein:
a first electrode (Node A; Fig. 9) of the eleventh transistor (322; Fig. 9) is connected to the gate electrode (Node A; Fig. 9) of the second transistor (321; Fig. 9), a second electrode of the eleventh transistor (322; Fig. 9) is connected to the second electrode of the second transistor (321; Fig. 9) and the second electrode (Paragraph [0170]) of the third transistor (323; Fig. 9), and a gate electrode of the eleventh transistor (322; Fig. 9) is configured to receive a second compensation and reset control signal (RES; Fig. 9 and 10; wherein figure shows signal RES is applied during A C Node Initialize and VTH compensate);
the eleventh transistor (322; Fig. 9) is configured to provide the reset signal (Sig<n>; Fig. 9) provided by the third transistor (323; Fig. 9) to the gate electrode (Node A; Fig. 9) of the second transistor (321; Fig. 9) in response to the second compensation and reset control signal (RES; Fig. 9 and 10; wherein figure shows signal RES is applied during A C Node Initialize and VTH compensate) received at the gate electrode of the eleventh transistor (322; Fig. 9); and
the eleventh transistor (322; Fig. 9) is further configured to provide threshold compensation (RES; Fig. 9 and 10; wherein figure shows signal RES is applied during A C Node Initialize and VTH compensate) for the second transistor (321; Fig. 9) in response to the second compensation and reset control signal (RES; Fig. 9 and 10; wherein figure shows signal RES is applied during A C Node Initialize and VTH compensate) received at the gate electrode of the eleventh transistor (322; Fig. 9).
Claim 15, Kim (Fig. 1-14) discloses further comprising a fourth capacitor (314; Fig. 9);
wherein:
a first electrode (Node D; Fig. 9) of the fourth capacitor (314; Fig. 9) is connected to the second electrode (Node D; Fig. 9) of the tenth transistor (315; Fig. 9), and a second electrode (Node C; Fig. 9) of the fourth capacitor (314; Fig. 9) is connected to the gate electrode (Node C; Fig. 9) of the first transistor (311; Fig. 9);
the fourth capacitor (314; Fig. 9) is configured to couple the third data signal (Sig<n>; Fig. 9; Paragraph [0155]) written by the tenth transistor (315; Fig. 9) to the gate electrode (Node C; Fig. 9) of the first transistor (311; Fig. 9).
Claim 16, Kim (Fig. 1-14) discloses a method (Fig. 10) for driving the pixel circuit (Fig. 9) according to claim 1 (see rejection to claim 1 above), comprising:
in a first reset phase (A C Node Initialize; Fig. 10), controlling the third transistor (323; Fig. 9) to turn on (Paragraph [0138]) in response to the reset control signal (Ref; Fig. 9 and 10) being at an active potential (RES during A C Node Initialize; Fig. 10);
providing the reset signal (Sig<n>; Fig. 9 and 10; Paragraph [0170]) to the gate electrode (Node C; Fig. 9) of the first transistor (311; Fig. 9) and the gate electrode (Node A; Fig. 9) of the second transistor (321; Fig. 9) through the third transistor (323; Fig. 9); and
controlling the second transistor (321; Fig. 9) to turn on in response to the reset signal (Sig<n>; Fig. 9; Paragraph [0174]).
Claim 20, Kim (Fig. 1-14) discloses a display apparatus (1300; Fig. 13), comprising:
a data driving circuit (820; Fig. 13), a scan driving circuit (830; Fig. 13), a plurality of data lines (D1-Dm; Fig. 13), a plurality of scan lines (G1-Gn; Fig. 13), and the pixel circuit (Fig. 9) according to claim 1 (See rejection to claim 1 above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 9, and 13-14 is rejected under 35 U.S.C. 103 as being unpatentable over in view of Kim et al (US 2020/0111403 A1) in view of Kim et al (US 2020/0111404 A1).
Claim 5, Kim (US 2020/0111403 A1) discloses the pixel circuit according to claim 1.
Kim (US 2020/0111403 A1) does not expressly disclose further comprising:
a sixth transistor;
wherein:
a first electrode of the sixth transistor is configured to receive a first data signal, a second electrode of the sixth transistor is connected to the first electrode of the first transistor, a gate electrode of the sixth transistor is configured to receive a first data writing control signal;
the sixth transistor is configured to write the first data signal into the first electrode of the first transistor in response to the first data writing control signal received at the gate electrode of the sixth transistor.
Kim (US 2020/0111404 A1) (Fig. 1-14) discloses further comprising:
a sixth transistor (313; Fig. 9);
wherein:
a first electrode of the sixth transistor (313; Fig. 9) is configured to receive (Paragraph [0157]) a first data signal (Sig; Fig. 9), a second electrode of the sixth transistor (313; Fig. 9) is connected to the first electrode of the first transistor (311; Fig. 9), a gate electrode of the sixth transistor (313; Fig. 9) is configured to receive a first data writing control signal (SPAM; Fig. 9 and 10);
the sixth transistor (313; Fig. 9) is configured to write the first data signal (Sig; Fig. 9) into the first electrode of the first transistor (311; Fig. 9) in response to the first data writing control signal (SPAM; Fig. 9) received at the gate electrode of the sixth transistor (313; Fig. 9).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim (US 2020/0111403 A1)’s pixel circuit by applying a PAM driving circuit, as taught by Kim (US 2020/0111404 A1), so to use a pixel circuit with a PAM driving circuit for providing a display panel providing improved color reproducibility to an input image signal through an LED (Paragraph [0006]).
Claim 9, Kim (US 2020/0111403 A1) discloses the pixel circuit according to claim 1.
Kim (US 2020/0111403 A1) does not expressly disclose further comprising an eighth transistor;
wherein:
a first electrode of the eighth transistor is configured to receive the power signal, a second electrode of the eighth transistor is connected to the first electrode of the first transistor, and a gate electrode of the eighth transistor is configured to receive a first driving control signal;
the eighth transistor is configured to, in response to the first driving control signal received at the gate electrode of the eighth transistor, provide the power signal received at the first electrode of the eighth transistor to the first electrode of the first transistor through the second electrode of the eighth transistor.
Kim (US 2020/0111404 A1) (Fig. 1-14) discloses further comprising an eighth transistor (333; Fig. 9);
wherein:
a first electrode of the eighth transistor (333; Fig. 9) is configured to receive the power signal (VDD; Fig. 9), a second electrode of the eighth transistor (333; Fig. 9) is connected to the first electrode of the first transistor (311; Fig. 9), and a gate electrode of the eighth transistor (333; Fig. 9) is configured to receive a first driving control signal (Emi; Fig. 9 and 10);
the eighth transistor (333; Fig. 9) is configured to (Paragraph [0165]), in response to the first driving control signal (Emi; Fig. 9 and 10) received at the gate electrode of the eighth transistor (333; Fig. 9), provide the power signal (VDD; Fig. 9) received at the first electrode of the eighth transistor (333; Fig. 9) to the first electrode of the first transistor (311; Fig. 9) through the second electrode of the eighth transistor (333; Fig. 9).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim (US 2020/0111403 A1)’s pixel circuit by applying a PAM driving circuit, as taught by Kim (US 2020/0111404 A1), so to use a pixel circuit with a PAM driving circuit for providing a display panel providing improved color reproducibility to an input image signal through an LED (Paragraph [0006]).
Claim 13, Kim (US 2020/0111403 A1) discloses the pixel circuit according to claim 12.
Kim (US 2020/0111403 A1) does not expressly disclose further comprising a twelfth transistor;
wherein:
a first electrode of the twelfth transistor is connected to the first electrode of the second transistor, a second electrode of the twelfth transistor is configured to receive a fourth data signal, and a gate electrode of the twelfth transistor is configured to receive a fourth data writing control signal;
the twelfth transistor is configured to write the fourth data signal into the first electrode of the second transistor in response to the fourth data writing control signal received at the gate electrode of the twelfth transistor;
the second transistor is further configured to transmit the fourth data signal received at the first electrode of the second transistor to the second electrode of the second transistor after being turned on;
the eleventh transistor is further configured to provide the fourth data signal to the gate electrode of the second transistor in response to the second compensation and reset control signal received at the gate electrode of the eleventh transistor, and provide threshold compensation for the second transistor.
Kim (US 2020/0111404 A1) (Fig. 1-14) discloses further comprising a twelfth transistor (323; Fig. 9);
wherein:
a first electrode of the twelfth transistor (323; Fig. 9) is connected to the first electrode of the second transistor (321; Fig. 9), a second electrode of the twelfth transistor (323; Fig. 9) is configured to receive a fourth data signal (Sig; Fig. 9; Paragraph [0160]), and a gate electrode of the twelfth transistor (323; Fig. 9) is configured to receive a fourth data writing control signal (SPWM(n); Fig. 9 and 10);
the twelfth transistor (323; Fig. 9) is configured to write the fourth data signal (Sig; Fig. 9; Paragraph [0160]) into the first electrode of the second transistor (321; Fig. 9) in response to the fourth data writing control signal (SPWM(n); Fig. 9 and 10) received at the gate electrode of the twelfth transistor (323; Fig. 9);
the second transistor (321; Fig. 9) is further configured to transmit the fourth data signal (Sig; Fig. 9; Paragraph [0160]) received at the first electrode of the second transistor (321; Fig. 9) to the second electrode of the second transistor (321; Fig. 9) after being turned on (Paragraph [0160]);
the eleventh transistor (322; Fig. 9) is further configured to provide the fourth data signal (Sig; Fig. 9; Paragraph [0160]) to the gate electrode of the second transistor (321; Fig. 9) in response to the second compensation and reset control signal received (SPWM(n); Fig. 9) at the gate electrode of the eleventh transistor (322; Fig. 9), and provide threshold compensation (Paragraph [0160]) for the second transistor (321; Fig. 9).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim (US 2020/0111403 A1)’s pixel circuit by applying a PWM driving circuit, as taught by Kim (US 2020/0111404 A1), so to use a pixel circuit with a PWM driving circuit for providing a display panel providing improved color reproducibility to an input image signal through an LED (Paragraph [0006]).
Claim 14, Kim (US 2020/0111404 A1) (Fig. 1-14) discloses further comprising a fourteenth transistor (331; Fig. 9);
wherein:
a first electrode of the fourteenth transistor (331; Fig. 9) is configured to receive the power signal (VDD; Fig. 9), a second electrode of the fourteenth transistor (331; Fig. 9) is connected to the first electrode of the second transistor (321; Fig. 9) and the first electrode of the twelfth transistor (323; Fig. 9), and a gate electrode of the fourteenth transistor (331; Fig. 9) is configured to receive a third driving control signal (Emi; Fig. 9 and 10);
the fourteenth transistor (331; Fig. 9) is configured to, in response to the third driving control signal (Emi; Fig. 9 and 10) received at the gate electrode of the fourteenth transistor (331; Fig. 9), provide the power signal (VDD; Fig. 9) received at the first electrode of the fourteenth transistor (331; Fig. 9) to the first electrode of the second transistor (321; Fig. 9) through the second electrode of the fourteenth transistor (331; Fig. 9).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim (US 2020/0111403 A1)’s pixel circuit by applying a PWM driving circuit, as taught by Kim (US 2020/0111404 A1), so to use a pixel circuit with a PWM driving circuit for providing a display panel providing improved color reproducibility to an input image signal through an LED (Paragraph [0006]).
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 2020/0111403 A1) in view of Kim et al (US 2020/0111404 A1) and Han et al (CN 113990243 A).
Claim 17, Kim (US 2020/0111403 A1) (Fig. 1-14) discloses wherein the pixel circuit (Fig. 9) further comprises:
a fourth transistor (312; Fig. 9), a fifth transistor (322; Fig. 9), a seventh transistor (325; Fig. 9), a first capacitor (313; Fig. 9), a second capacitor (324; Fig. 9), and a third capacitor (326; Fig. 9);
wherein:
a first electrode of the fourth transistor (312; Fig. 9) is connected to the gate electrode (Node C; Fig. 9) of the first transistor (311; Fig. 9), a second electrode of the fourth transistor (312; Fig. 9) is connected to the second electrode of the first transistor (311; Fig. 9), and a gate electrode of the fourth transistor (312; Fig. 9) is configured to receive a first compensation control signal (RES; Fig. 9 and 10);
a first electrode of the fifth transistor (322; Fig. 9) is connected to the gate electrode (Node A; Fig. 9) of the second transistor (321; Fig. 9), a second electrode of the fifth transistor (322; Fig. 9) is connected to the second electrode of the second transistor (321; Fig. 9) and the second electrode (Paragraph [0170]) of the third transistor (323; Fig. 9), and a gate electrode of the fifth transistor (322; Fig. 9) is configured to receive a first compensation and reset control signal (RES; Fig. 9 and 10; wherein figure shows signal RES is applied during A C Node Initialize and VTH compensate);
a first electrode of the seventh transistor (325; Fig. 9) is configured to receive a second data signal (Sig<m>; Fig. 9; Paragraph [0156]), a second electrode (Node B; Fig. 9) of the seventh transistor (325; Fig. 9) is connected to (Paragraph [0184]) the gate electrode (Node A; Fig. 9) of the second transistor (321; Fig. 9), and a gate electrode of the seventh transistor (325; Fig. 9) is configured to receive a second data writing control signal (SPWM(n); Fig. 9 and 10);
a first electrode (Node C; Fig. 9) of the first capacitor (313; Fig. 9) is connected to the gate electrode (Node C; Fig. 9) of the first transistor (311; Fig. 9), and a second electrode of the first capacitor (313; Fig. 9) is configured to receive the power signal (VDD; Fig. 9);
a first electrode (Node B; Fig. 9) of the second capacitor (324; Fig. 9) is connected to the second electrode (Node B; Fig. 9) of the seventh transistor (325; Fig. 9), and a second electrode (Node A; Fig. 9) of the second capacitor (324; Fig. 9) is connected to the gate electrode (Node A; Fig. 9) of the second transistor (321; Fig. 9); and
a first electrode (Node A; Fig. 9) of the third capacitor (326; Fig. 9) is connected to the first electrode (Node A; Fig. 9) of the second capacitor (324; Fig. 9), and a second electrode of the third capacitor (326; Fig. 9) is configured to receive the light emission duration control signal (Vsweep; Fig. 9);
wherein the method (Fig. 10) further comprises:
a first compensation phase (Vth Compensate; Fig. 10), a first data writing phase (PWM Data Setup; Fig. 10), and a light-emitting phase (Emitting; Fig. 10) sequentially arranged after the first reset phase (A C Node Initialize; Fig. 10);
in the first reset phase (A C Node Initialize; Fig. 10), controlling the fifth transistor (322; Fig. 9) to turn on (Paragraph [0138]) in response to the first compensation and reset control signal (Ref; Fig. 9 and 10) being at the active potential (RES during A C Node Initialize; Fig. 10);
providing the reset signal (Sig<m>; Fig. 9; Paragraph [0138]; wherein discloses “receive input of an input voltage (for example, −5V) from the data line (Sig<m>) via the fourth transistor 323 turned on according to a control signal Ref”) to the gate electrode (Node A; Fig. 9) of the second transistor (322; Fig. 9) further through the fifth transistor (322; Fig. 5; Paragraph [0170]);
charging the second capacitor (324; Fig. 9) in response to the reset signal (Sig<m>; Fig. 9; Paragraph [0138]; wherein discloses “receive input of an input voltage (for example, −5V) from the data line (Sig<m>) via the fourth transistor 323 turned on according to a control signal Ref”) provided to the gate electrode (Node A; Fig. 9) of the second transistor (321; Fig. 9); and
resetting a potential at the gate electrode (Node A; Fig. 9) of the second transistor (321; Fig. 9) to a potential of the reset signal (Sig<m>; Fig. 9; Paragraph [0138]; wherein discloses “receive input of an input voltage (for example, −5V) from the data line (Sig<m>) via the fourth transistor 323 turned on according to a control signal Ref”) in response to the reset signal (Sig<m>; Fig. 9; Paragraph [0138]; wherein discloses “receive input of an input voltage (for example, −5V) from the data line (Sig<m>) via the fourth transistor 323 turned on according to a control signal Ref”) provided to the gate electrode (Node A; Fig. 9) of the second transistor (321; Fig. 9);
in the first compensation phase (Vth Compensate; Fig. 10), controlling the fifth transistor (322; Fig. 9) and the second transistor (321; Fig. 9) to turn on in response to the first compensation and reset control signal (RES; Fig. 9 and 10) being at the active potential (RES during Vth Compensate; Fig. 10);
providing the power signal (VDD; Fig. 9 and 10) to the second electrode of the second transistor (321; Fig. 9) through (Paragraph [0141]) the second transistor (321; Fig. 9); and
performing a compensation for a threshold voltage (Paragraph [0141]) of the second transistor (321; Fig. 9) using the potential at the gate electrode (Node A; Fig. 9) of the second transistor (321; Fig. 9) through the fifth transistor (322; Fig. 9);
in the first data writing phase (PWM Data Setup; Fig. 10), controlling the seventh transistor (325; Fig. 9) to turn on (Paragraph [0184]) in response to the second data writing control signal (SPWM(n); Fig. 9) being at the active potential (SPWM(n) during PWM Data Setup; Fig. 10);
providing the second data signal (Sig<n>; Fig. 9 and 10) being at the active potential (Fig. 10; wherein figure shows a value of PWM Data) to the first electrode (Node B; Fig. 9) of the second capacitor (324; Fig. 9) through the seventh transistor (325; Fig. 9); and
coupling the second data signal (Sig<n>; Fig. 9 and 10) to the gate electrode (Node A; Fig. 9) of the second transistor (321; Fig. 9) through the second capacitor (324; Fig. 9);
in the light-emitting phase (Emitting; Fig. 10), controlling the potential at the gate electrode (Node A; Fig. 9) of the second transistor (321; Fig. 9) gradually transition to the active potential until (Paragraph [0197-0198]) the second transistor (321; Fig. 9) is turned on (Paragraph [0198]), as the light emission duration control signal gradually changes (Vsweep; Fig. 10) from an inactive potential to the active potential (Paragraph [0197]), combined with a coupling effect of the second capacitor (324; Fig. 9) and the third capacitor (326; Fig. 9);
charging the first capacitor (313; Fig. 9) using the power signal (VDD; Fig. 9) passing through the second transistor (321; Fig. 9) in response (Paragraph [0199]) to the second transistor (321; Fig. 9) being turned on (Paragraph [0199]);
controlling the potential (Paragraph [0199]) at the gate electrode (Node C; Fig. 9) of the first transistor (311; Fig. 9) gradually transition to the inactive potential (Paragraph [0199]) until the first transistor (311; Fig. 9 and 10) is turned off and the light emitting element stops emitting light (Paragraph [0199]).
Kim (US 2020/0111403 A1) does not expressly disclose the pixel circuit further comprises:
a sixth transistor, an eighth transistor, and a ninth transistor;
wherein:
a first electrode of the sixth transistor is configured to receive a first data signal, a second electrode of the sixth transistor is connected to the first electrode of the first transistor, a gate electrode of the sixth transistor is configured to receive a first data writing control signal;
a first electrode of the eighth transistor is configured to receive the power signal, a second electrode of the eighth transistor is connected to the first electrode of the first transistor, and a gate electrode of the eighth transistor is configured to receive a first driving control signal;
a first electrode of the ninth transistor is connected to the first electrode of the first transistor, a second electrode of the ninth transistor is connected to the light-emitting element, and a gate electrode of the ninth transistor is configured to receive a second driving control signal;
wherein the method further comprises:
a light-emitting phase sequentially arranged after the first reset phase;
in the light-emitting phase, controlling the eighth transistor to turn on in response to the first driving control signal being at the active potential;
controlling the ninth transistor to turn on in response to the second driving control signal being at the active potential;
driving the light-emitting element to emit light using the power signal passing through the eighth transistor, the first transistor and the ninth transistor.
Kim (US 2020/0111404 A1) (Fig. 1-14) discloses the pixel circuit (Fig. 9) further comprises:
a sixth transistor (313; Fig. 9), an eighth transistor (333; Fig. 9), and a ninth transistor (334; Fig. 9);
wherein:
a first electrode of the sixth transistor (313; Fig. 9) is configured to receive a first data signal (Sig; Fig. 9), a second electrode of the sixth transistor (313; Fig. 9) is connected to the first electrode of the first transistor (311; Fig. 9), a gate electrode of the sixth transistor (313; Fig. 9) is configured to receive a first data writing control signal (SPAM; Fig. 9);
a first electrode of the eighth transistor (333; Fig. 9) is configured to receive the power signal (VDD; Fig. 9), a second electrode of the eighth transistor (333; Fig. 9) is connected to the first electrode of the first transistor (311; Fig. 9), and a gate electrode of the eighth transistor (333; Fig. 9) is configured to receive a first driving control signal (Emi; Fig. 9);
a first electrode of the ninth transistor (334; Fig. 9) is connected to the first electrode of the first transistor (311; Fig. 9), a second electrode of the ninth transistor (334; Fig. 9) is connected to the light-emitting element (200; Fig. 9), and a gate electrode of the ninth transistor (334; Fig. 9) is configured to receive a second driving control signal (Emi; Fig. 9);
wherein the method (Fig. 10) further comprises:
a light-emitting phase (Emitting; Fig. 10) sequentially arranged after the first reset phase (Initialize; Fig. 10);
in the light-emitting phase (Emitting; Fig. 10), controlling the eighth transistor (333; Fig. 9) to turn on (Paragraph [0204]) in response to the first driving control signal (Emi; Fig. 9) being at the active potential (Emi during Emitting; Fig. 10);
controlling the ninth transistor (334; Fig. 9) to turn on (Paragraph [0204]) in response to the second driving control signal (Emi; Fig. 9) being at the active potential (Emi during Emitting; Fig. 10);
driving the light-emitting element (200; Fig. 9) to emit light (Paragraph [0204]) using the power signal (VDD; Fig. 9) passing through the eighth transistor (333; Fig. 9), the first transistor (311; Fig. 9) and the ninth transistor (334; Fig. 9).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim (US 2020/0111403 A1)’s pixel circuit by applying a PAM driving circuit, as taught by Kim (US 2020/0111404 A1), so to use a pixel circuit with a PAM driving circuit for providing a display panel providing improved color reproducibility to an input image signal through an LED (Paragraph [0006]).
Kim in view of Kim does not expressly disclose wherein the method further comprises:
a second reset phase, a second compensation phase, a second data writing phase sequentially arranged after the first reset phase;
in the second reset phase, controlling the third transistor to turn on in response to the reset control signal being at the active potential;
charging the first capacitor using the reset signal passing through the third transistor;
resetting a potential at the gate electrode of the first transistor to the potential of the reset signal; and
controlling the first transistor to turn on;
in the second compensation phase and the second data writing phase, controlling the fourth transistor to turn on in response to the first compensation control signal being at the active potential;
controlling the sixth transistor to turn on in response to the first data writing control signal being at the active potential;
writing the first data signal to the first electrode of the first transistor through the sixth transistor; and
performing a compensation for a threshold voltage of the first transistor using the first data signal through the first transistor and the fourth transistor;
Han (Fig. 1a-8) discloses wherein the method (Fig. 8) further comprises:
a second reset phase (T3; Fig. 8), a second compensation phase (T4; Fig. 8), a second data writing phase (T4; Fig. 8) sequentially arranged after the first reset phase (T1; Fig. 8);
in the second reset phase (T3; Fig. 8), controlling the third transistor (M12; Fig. 7c) to turn on in response to the reset control signal (Rst2; Fig. 7c and 8) being at the active potential (Rst2 during T3; Fig. 8);
charging the first capacitor (C2; Fig. 7c) using the reset signal (LVDD; Fig. 7c) passing through the third transistor (M12; Fig. 7c);
resetting a potential at the gate electrode (Npam; Fig. 7c) of the first transistor (M9; Fig. 7c) to the potential of the reset signal (LVDD; Fig. 7c); and
controlling the first transistor (M9; Fig. 7d) to turn on;
in the second compensation phase (T4; Fig. 8) and the second data writing phase (T4; Fig. 8), controlling the fourth transistor (M10; Fig. 7d) to turn on in response to the first compensation control signal (Gate2; Fig. 7d) being at the active potential (Gate 2 during T4; Fig. 8);
controlling the sixth transistor (M8; Fig. 7d) to turn on in response to the first data writing control signal (Gate2; Fig. 7d) being at the active potential (Gate 2 during T4; Fig. 8);
writing the first data signal (DATApam; Fig. 7d) to the first electrode of the first transistor (M9; Fig. 7d) through the sixth transistor (M8; Fig. 7d); and
performing a compensation for a threshold voltage (Fig. 7d) of the first transistor (M9; Fig. 7d) using the first data signal (DATApam; Fig. 7d) through the first transistor (M9; Fig. 7d) and the fourth transistor (M10; Fig. 7d);
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Kim’s pixel circuit by applying a driving method, as taught by Han, so to use a pixel circuit with a driving method for providing when displaying a frame picture, the driving current of the light emitting module in each pixel can be kept stable, can prevent the picture colour reproducibility (Contents of the Inventions).
Claim 18, Kim (US 2020/0111403 A1) (Fig. 1-14) discloses wherein, in the first data writing phase (PWM Data Setup; Fig. 10), an ending time of the active potential of the second data signal (PWM; Fig. 10) lags behind an ending time of the active potential of the second data writing control signal (SPWM1; Fig. 10) by a first preset time (Fig, 10).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 2020/0111403 A1) in view of Kim et al (US 2019/0371232 A1).
Claim 19, Kim (US 2020/0111403 A1) (Fig. 1-14) discloses wherein the pixel circuit (Fig. 9) further comprises:
a tenth transistor (315; Fig. 9) and a fourth capacitor (314; Fig. 9);
a first electrode of the tenth transistor (315; Fig. 9) is configured to receive a third data signal (Sig<m>; Fig. 9), a second electrode (Node D: Fig. 9) of the tenth transistor (315; Fig. 9) is connected to the gate electrode (Node C; Fig. 9) of the first transistor (311; Fig. 9), and a gate electrode of the tenth transistor (315; Fig. 9) is configured to receive a third data writing control signal (SPAM; Fig. 9); and
a first electrode (Node D; Fi. 9) of the fourth capacitor (314; Fig. 9) is connected to the second electrode (Node D; Fig. 9) of the tenth transistor (315; Fig. 9), and a second electrode (Node C; Fig. 9) of the fourth capacitor (314; Fig. 9) is connected to the gate electrode (Node C; Fig. 9) of the first transistor (311; Fig. 9).
Kim (US 2020/0111403 A1) does not expressly disclose wherein an ending time of the active potential of the third data signal lags behind an ending time of the active potential of the third data writing control signal by a second preset time when writing the third data signal into the tenth transistor.
Kim (US 2019/0371232 A1) (Fig. 1-12) discloses wherein an ending time of the active potential of the third data signal (PAM Data; Fig. 8) lags behind an ending time of the active potential of the third data writing control signal (SPAM1; Fig. 8) by a second preset time (Fig. 8) when writing the third data signal (Data; Fig. 7) into the tenth transistor (311; Fig. 7).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim (US 2020/0111403 A1)’s pixel circuit by applying a driving method, as taught by Kim (US 2019/0371232 A1), so to use a pixel circuit with a driving method for providing is a display panel that improves color reproducibility to an input image signal through an LED which is an inorganic light emitting device (Paragraph [0008]).
Conclusion
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/Adam J Snyder/Primary Examiner, Art Unit 2623 08/03/2026
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