Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 13, 2026, was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
Applicant’s arguments, see Response under Claims in view of 35 U.S.C. 102/103 (pages 8-9), filed September 2, 2026, with respect to the rejections of claims 1 and 26 have been fully considered and are not persuasive.
Applicant argues, “Nowhere in Farian teaches a capacitor coupled between the capacitor of the RC circuit and an output terminal of the comparator.”. Examiner respectfully disagrees. As shown in the rejections below, Farian’s (the prior art of record) charge moving capacitor is indirectly coupled to the capacitor of the RC circuit and is indirectly coupled to the output terminal of the comparator.
Additionally, the applicant argues, “Farian, however, neither teaches nor suggests adjusting the oscillator's output frequency by using a charge moving capacitor to inject charge into, or extract charge from, the RC circuit.”. Examiner respectfully disagrees. As shown in the rejections below, Farian’s electric charges associated with the RC circuit move through the charge moving capacitor to adjust the oscillators frequency.
Claim Rejections - 35 USC § 102
Applicant is reminded that claim mapping is provided as a courtesy to the applicant, but applicant should consider a reference as a whole, as the entire reference gives context to mapped sections.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8, 16, 18-19, and 26-29 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Farian (WO 2024056578 A1; Fig. 1 embodiment); hereinafter Farian*1.
Regarding Claim 1, Farian*1 discloses a circuit, comprising: an oscillation circuit [Fig. 1], configured to generate a clock signal [118], comprising a comparator [114] and a resistor-capacitor (RC) circuit [R/C1], wherein the RC circuit comprises a capacitor [C1]; and a charge moving capacitor [C2], coupled between the capacitor of the RC circuit and an output terminal of the comparator [C2 is indirectly coupled between C1 (thru RCAL) and 114-output (thru 116A/B, 110, 106)]; wherein a frequency of the clock signal is trimmed by injecting or extracting electric charges associated with the RC circuit via the charge moving capacitor [Abstract, Background, Fig. 3].
Regarding Claim 2, Farian*1 discloses the circuit of claim 1, wherein the RC circuit comprising: a resistor [R] connected to the capacitor.
Regarding Claim 3, Farian*1 discloses the circuit of claim 2, wherein the resistor and the capacitor are connected between a first node [106] and a second node [108]; wherein the oscillation circuit comprises a chopping circuit [110] coupled to the first node and the second node; wherein during a first time [first state/high state; Fig. 2], the chopping circuit provides a first voltage [VDD/102] to the first node and provides a second voltage [GND/112] to the second node; wherein during a second time [second state/low state; Fig. 2], the chopping circuit provides the second voltage to the first node and provides the first voltage to the second node.
Regarding Claim 4, Farian*1 discloses the circuit of claim 1, wherein a first end of the charge moving capacitor [lower bar of C2, via RCAL] is coupled to the RC circuit; wherein a second end [upper bar of C2] of the charge moving capacitor changes to a first voltage [VDD/102] from a second voltage [GND/112].
Regarding Claim 5, Farian*1 discloses the circuit of claim 4, wherein the second end of the charge moving capacitor receives a first signal [VC2 input] comprising a rising edge [Fig. 2].
Regarding Claim 6, Farian*1 discloses the circuit of claim 5, wherein the second end of the charge moving capacitor receives the first signal comprising the rising edge within a discharging period [column 7, lines 3-5].
Regarding Claim 7, Farian*1 discloses the circuit of claim 4, wherein the second end of the charge moving capacitor receives a second signal [VC1 input] comprising a falling edge [Fig. 2].
Regarding Claim 8, Farian*1 discloses the circuit of claim 7, wherein the second end of the charge moving capacitor receives the second signal comprising the falling edge within a charging period [column 7, lines 3-5].
Regarding Claim 16, Farian*1 discloses the circuit of claim 1, wherein a waveform [Fig. 2] of a capacitor voltage [VC1] at the capacitor comprises a bump [see figure below].
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Regarding Claim 18, Farian*1 discloses the circuit of claim 16, wherein the waveform of the capacitor voltage comprises the bump over an exponential decreasing [from VDD+VTH to VTH to -VDD+VTH] within a discharging period of the capacitor [column 7, lines 3-8].
Regarding Claim 19, Farian*1 discloses the circuit of claim 16, wherein the waveform of the capacitor voltage comprises the bump over an exponential increasing [from -VDD+VTH to VTH to VDD+VTH] within a charging period of the capacitor [column 7, lines 3-8].
Regarding Claim 26, Farian*1 discloses a frequency trimming method [Abstract], applied in a circuit [Fig. 1], configured to trim a frequency [Abstract] of a clock signal [118] of the circuit, the method comprising: injecting or extracting electric charges associated with a resistor-capacitor (RC) circuit [R/C1] via a charge moving capacitor [C2]; [Abstract, Background, Fig. 3]; wherein the circuit comprises an oscillation circuit [Fig. 1], and the oscillation circuit comprises a comparator [114] and the RC circuit; wherein the RC circuit comprises a capacitor [C1]; wherein the charge moving capacitor is coupled between the capacitor of the RC circuit and an output terminal of the comparator [C2 is indirectly coupled between C1 (thru RCAL) and 114-output (thru 116A/B, 110, 106)]; wherein the oscillation circuit generates the clock signal.
Regarding Claim 27, Farian*1 discloses the frequency trimming method of claim 26, comprising: injecting or extracting the electric charges associated with the RC circuit via the charge moving capacitor connected to the RC circuit.
Regarding Claim 28, Farian*1 discloses the frequency trimming method of claim 27, wherein the step of injecting the electric charges via the charge moving capacitor comprises: increasing a voltage of an end of the charge moving capacitor during a discharging period of the capacitor of the RC circuit [Fig. 2; column 7, lines 3-8].
Regarding Claim 29, Farian*1 discloses the frequency trimming method of claim 27, wherein the step of extracting the electric charges via the charge moving capacitor comprises: decreasing a voltage of an end of the charge moving capacitor during a charging period of the capacitor of the RC circuit [Fig. 2; column 7, lines 3-8].
Claims 1-4, 9-13, 15-17, and 26-29 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Farian (WO 2024056578 A1; Fig. 5 embodiment); hereinafter Farian*5.
Regarding Claim 1, Farian*5 discloses a circuit, comprising: an oscillation circuit [Fig. 5], configured to generate a clock signal [CK/118'], comprising a comparator [502/504] and a resistor-capacitor (RC) circuit [R/C1], wherein the RC circuit comprises a capacitor [C1]; and a charge moving capacitor [C2], coupled between the capacitor of the RC circuit and an output terminal of the comparator [C2 is indirectly coupled between C1 (thru R') and CK1/CK2 (thru 508/116'A/B, 110', 106')]; wherein a frequency of the clock signal is trimmed by injecting or extracting electric charges associated with the RC circuit via the charge moving capacitor [Abstract, Background, Fig. 3].
Regarding Claim 2, Farian*5 discloses the circuit of claim 1, wherein the RC circuit comprising: a resistor [R] connected to the capacitor.
Regarding Claim 3, Farian*5 discloses the circuit of claim 2, wherein the resistor and the capacitor are connected between a first node [106'] and a second node [108']; wherein the oscillation circuit comprises a chopping circuit [110'] coupled to the first node and the second node; wherein during a first time [first state/high state; Fig. 6], the chopping circuit provides a first voltage [VDD/102'] to the first node and provides a second voltage [GND/112'] to the second node; wherein during a second time [second state/low state; Fig. 6], the chopping circuit provides the second voltage to the first node and provides the first voltage to the second node.
Regarding Claim 4, Farian*5 discloses the circuit of claim 1, wherein a first end of the charge moving capacitor [lower bar of C2, via R'] is coupled to the RC circuit; wherein a second end [upper bar of C2] of the charge moving capacitor changes to a first voltage [VDD/102'] from a second voltage [GND/112'].
Regarding Claim 9, Farian*5 discloses the circuit of claim 1, comprising: a delay element [514], coupled between the comparator and the charge moving capacitor [coupled between thru other elements].
Regarding Claim 10, Farian*5 discloses the circuit of claim 9, wherein the delay element produces a delayed clock signal [116B'] to the charge moving capacitor according to the clock signal outputted from the comparator.
Regarding Claim 11, Farian*5 discloses the circuit of claim 10, wherein the delay element produces the delayed clock signal having a delay time [Δt] with respect to the clock signal.
Regarding Claim 12, Farian*5 discloses the circuit of claim 11, wherein the delay time is adjustable [column 11, lines 19-25].
Regarding Claim 13, Farian*5 discloses the circuit of claim 11, wherein the frequency of the clock signal is trimmed by adjusting the delay time or a capacitance of the charge moving capacitor [column 11, lines 19-25].
Regarding Claim 15, Farian*5 discloses the circuit of claim 13, wherein the frequency of the clock signal is trimmed to be lower by adjusting the capacitance higher [column 13, lines 23-25; where traditional trimming techniques adjust capacitors].
Regarding Claim 16, Farian*5 discloses the circuit of claim 1, wherein a waveform [Fig. 6] of a capacitor voltage [VC2] at the capacitor comprises a bump [see figure below].
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Regarding Claim 17, Farian*5 discloses the clock signal generator of claim 16, wherein the bump occurs when a delay time after the oscillation circuit transits states [602-604, 606-608; column 9, line 29 - column 10, line 20].
Regarding Claim 26, Farian*5 discloses a frequency trimming method [Abstract], applied in a circuit [Fig. 5], configured to trim a frequency [Abstract] of a clock signal [CK/118'] of the circuit, the method comprising: injecting or extracting electric charges associated with a resistor-capacitor (RC) circuit [R/C1] via a charge moving capacitor [C2]; [Abstract, Background, Fig. 3]; wherein the circuit comprises an oscillation circuit [Fig. 5], and the oscillation circuit comprises a comparator [502/504] and the RC circuit; wherein the RC circuit comprises a capacitor [C1]; wherein the charge moving capacitor is coupled between the capacitor of the RC circuit and an output terminal of the comparator [C2 is indirectly coupled between C1 (thru R') and CK1/CK2 (thru 508/116'A/B, 110', 106')]; wherein the oscillation circuit generates the clock signal.
Regarding Claim 27, Farian*5 discloses the frequency trimming method of claim 26, comprising: injecting or extracting the electric charges associated with the RC circuit via the charge moving capacitor connected to the RC circuit.
Regarding Claim 28, Regarding Claim 28, Farian*5 discloses the frequency trimming method of claim 27, wherein the step of injecting the electric charges via the charge moving capacitor comprises: increasing a voltage of an end of the charge moving capacitor during a discharging period of the capacitor of the RC circuit [Fig. 6; column 7, lines 3-8].
Regarding Claim 29, Farian*5 discloses the frequency trimming method of claim 27, wherein the step of extracting the electric charges via the charge moving capacitor comprises: decreasing a voltage of an end of the charge moving capacitor during a charging period of the capacitor of the RC circuit [Fig. 6; column 7, lines 3-8].
Claim Rejections - 35 USC § 103
Applicant is reminded that claim mapping is provided as a courtesy to the applicant, but applicant should consider a reference as a whole, as the entire reference gives context to mapped sections.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 20-21 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Farian*1, in view of Tang et al. (CN 117411468 A); hereinafter Farian*1, in view of Tang.
Regarding Claim 20, Farian*1 discloses the circuit of claim 1, wherein the RC circuit comprising: a first capacitor [C1] coupled to a first input terminal [non-inverting (+) input of 114] of the comparator. Farian*1 does not explicitly disclose the RC circuit comprising: a second capacitor coupled to a second input terminal [inverting (-) input of 114] of the comparator.
However, Tang discloses wherein the RC circuit [Fig. 6; R1/C1/R2/C2] comprising: a first capacitor [C1] coupled to a first input terminal [Von] of the comparator; and a second capacitor [C2] coupled to a second input terminal [Vop] of the comparator; and a charge moving capacitor [C3/C4], connected to the RC circuit. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Tang in the invention of Farian*1, with the expected benefit of solving overshoot phenomenon. This method of improving Farian*1 using Tang was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Tang. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Farian*1 and Tang to obtain the invention: incorporating a second pair of resistor and capacitor in series to be in parallel with the first pair of the RC circuit.
Regarding Claim 21, Farian*1, in view of Tang, discloses the circuit of claim 20, comprising: a first charge moving capacitor [Tang; C3] coupled to the first capacitor; and a second charge moving capacitor [Tang; C4] coupled to the second capacitor.
Regarding Claim 25, Farian*1, in view of Tang, discloses the circuit of claim 20, wherein a first waveform [Farian*1; Fig. 2] of a first capacitor voltage [Farian*1; VC1] at the first capacitor comprises a first bump [Farian*1; see figure below claim 16 rejection above] toward a first polarity [Farian*1; negative polarity; -VDD+VTH] over an exponential decreasing [Farian*1; from VDD+VTH to VTH to -VDD+VTH] within a discharging period of the first capacitor [Farian*1; column 7, lines 3-8]; wherein a second waveform [Farian*1; Fig. 2] of a second capacitor voltage [Farian*1; VC2] at the second capacitor comprises a second bump [Farian*1; same location as first bump at VTH] toward a second polarity [Farian*1; positive polarity; VDD+VTH] over an exponential increasing [Farian*1; from -VDD+VTH to VTH to VDD+VTH] within a charging period of the second capacitor [Farian*1; column 7, lines 3-8]; wherein the first polarity and the second polarity are opposite to each other [Farian*1; Fig. 2]; wherein the discharging period of the first capacitor and the charging period of the second capacitor coincide with each other [Farian*1; at VTH].
Allowable Subject Matter
Claims 14 and 22-24 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Claim 14 is objected to because the prior art of the record does not disclose nor render obvious wherein the frequency of the clock signal is trimmed to be lower by adjusting the delay time longer, as cited with the rest of the claimed limitation.
Claim 22 is objected to because the prior art of the record does not disclose nor render obvious wherein a second delay element, coupled between a second output terminal of the comparator and the second charge moving capacitor, as cited with the rest of the claimed limitation.
Claims 23-24 depend upon the objected claim 22 and is therefore also objected to.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Amit Bhatia whose telephone number is (571)272-4410. The examiner can normally be reached Monday-Friday 8:30am-4:30pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached at (571) 270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Amit R Bhatia/Examiner, Art Unit 2836
/REGIS J BETSCH/SPE, Art Unit 2836
