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Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claims 1-12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 7-17 of U.S. Patent No. 12,525,050 in view of Talebzadeh et al. U.S. Patent Publication No. 2020/0219447 (hereinafter Talebzadeh).
Claim 1
Claim 1 of Patent
A display device comprising: a first sensor pixel connected to a first signal input line extending in a first direction and a horizontal driving line extending in a second direction crossing the first direction;
A display device comprising: a first sensor pixel connected to a first signal input line extending in a first direction and a horizontal driving line extending in a second direction crossing the first direction;
a second sensor pixel connected to a second signal input line different from the first signal input line and connected to the horizontal driving line;
a second sensor pixel connected to a second signal input line different from the first signal input line and connected to the horizontal driving line;
a third sensor pixel connected to a third signal input line different from the first and second signal input lines and connected to the horizontal driving line; a fourth sensor pixel connected to a fourth signal input line different from the first to third signal input lines and connected to the horizontal driving line;
and a multiplexer, wherein during a sensing period within a single frame period, a gate-on voltage is applied to the horizontal driving line four times, wherein during a first period within the sensing period, in which a first application of the gate-on voltage is applied a first one of four times,
and a multiplexer, wherein during a sensing period within a single frame period, a gate-on voltage is applied to the horizontal driving line a plurality of times, wherein during a first period within the sensing period, in which a first application of the gate-on voltage is applied a first one of the plurality of times,
the multiplexer electrically connects the first signal input line to an output line and disconnects the second to fourth signal input lines from the output line, wherein during a second period, subsequent to the first period within the sensing period, in which a second application of the gate-on voltage is applied a second one of four times, the multiplexer disconnects the first, third, and fourth signal input lines from the output line and electrically connects the second signal input line to the output line,
the multiplexer electrically connects the first signal input line to an output line and disconnects the second signal input line from the output line, wherein during a second period, subsequent to the first period within the sensing period, in which a second application of the gate-on voltage is applied a second one of the plurality of times, the multiplexer disconnects the first signal input line from the output line and electrically connects the second signal input line to the output line,
wherein during a third period, subsequent to the second period within the sensing period, in which a third application of the gate-on voltage is applied a third one of four times, the multiplexer disconnects the first, second, and fourth signal input lines from the output line and electrically connects the third signal input line to the output line, wherein during a fourth period, subsequent to the third period within the sensing period, in which a fourth application of the gate-on voltage is applied a fourth one of four times, the multiplexer disconnects the first to third signal input lines from the output line and electrically connects the fourth signal input line to the output line,
and wherein a gate-off voltage is applied to the horizontal driving line throughout a period between each of the first to fourth applications of the gate-on voltage.
and wherein a gate-off voltage is applied to the horizontal driving line throughout a period between the first and second applications of the gate-on voltage.
As can be seen above, besides the wording, Patent teaches all the limitations of claim 1 with the exception of a third sensor pixel connected to a third signal input line different from the first and second signal input lines and connected to the horizontal driving line; a fourth sensor pixel connected to a fourth signal input line different from the first to third signal input lines and connected to the horizontal driving line; wherein during a third period, subsequent to the second period within the sensing period, in which a third application of the gate-on voltage is applied a third one of four times, the multiplexer disconnects the first, second, and fourth signal input lines from the output line and electrically connects the third signal input line to the output line, wherein during a fourth period, subsequent to the third period within the sensing period, in which a fourth application of the gate-on voltage is applied a fourth one of four times, the multiplexer disconnects the first to third signal input lines from the output line and electrically connects the fourth signal input line to the output line; a gate-off voltage is applied to the horizontal driving line throughout a period between each of the first to fourth applications of the gate-on voltage.
However, in a related field of endeavor, Talebzadeh teaches an image sensor and further teaches a third sensor pixel connected to a third signal input line different from the first and second signal input lines and connected to the horizontal driving line; a fourth sensor pixel connected to a fourth signal input line different from the first to third signal input lines and connected to the horizontal driving line (Figures 3-4, pixels connected to RD[1] and VMON3-4); wherein during a third period, subsequent to the second period within the sensing period, in which a third application of the gate-on voltage is applied a third one of four times, the multiplexer disconnects the first, second, and fourth signal input lines from the output line and electrically connects the third signal input line to the output line (Figures 3-5, RD[1], Φ3 and Φ1-Φ4), wherein during a fourth period, subsequent to the third period within the sensing period, in which a fourth application of the gate-on voltage is applied a fourth one of four times, the multiplexer disconnects the first to third signal input lines from the output line and electrically connects the fourth signal input line to the output line (Figures 3-5, RD[1], Φ4 and Φ1-Φ4). In addition, the combination of Patent and Talebzadeh teach a gate-off voltage is applied to the horizontal driving line throughout a period between each of the first to fourth applications of the gate-on voltage (Patent teaches gate-off voltage in between gate-on voltage (see claim 1) and Talebzadeh teaches fourth applications of the gate-on voltage RD[1] in figures 3-5).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide third and fourth application of the gate-on voltage with the benefit that transmit for a duration long enough for the digital controller 16 to activate the multiplexer 307 to sequentially activate the switches ϕ1 to ϕm, i.e. for m time periods as suggested in [0047].
In addition,
Claim 2 is rejected over claim 7 of Patent in view of Talebzadeh
Claim 3 is rejected over claim 8 of Patent in view of Talebzadeh
Claim 4 is rejected over claim 9 of Patent in view of Talebzadeh
Claim 5 is rejected over claim 10 of Patent in view of Talebzadeh
Claim 6 is rejected over claim 11 of Patent
Claim 7 is rejected over claim 12 of Patent
Claim 8 is rejected over claim 13 of Patent in view of Talebzadeh
Claim 9 is rejected over claim 14 of Patent
Claim 10 is rejected over claim 15 of Patent in view of Talebzadeh
Claim 11 is rejected over claim 16 of Patent
Claim 12 is rejected over claim 17 of Patent
Claims 1-12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 5 and 9 of U.S. Patent No. 11,837,010 in view of Talebzadeh.
Claim 1
Claim 1of Patent
A display device comprising: a first sensor pixel connected to a first signal input line extending in a first direction and a horizontal driving line extending in a second direction crossing the first direction; a second sensor pixel connected to a second signal input line different from the first signal input line and connected to the horizontal driving line
An input sensing device comprising: a plurality of sensor pixels, where each sensor pixel is connected to a corresponding one of a plurality of driving lines and a corresponding one of a plurality of signal input lines; a horizontal driver configured to sequentially apply a horizontal driving signal to the plurality of sensor pixels through the driving lines;
a third sensor pixel connected to a third signal input line different from the first and second signal input lines and connected to the horizontal driving line; a fourth sensor pixel connected to a fourth signal input line different from the first to third signal input lines and connected to the horizontal driving line;
and a multiplexer, wherein during a sensing period within a single frame period, a gate-on voltage is applied to the horizontal driving line four times, wherein during a first period within the sensing period, in which a first application of the gate-on voltage is applied a first one of four times, the multiplexer electrically connects the first signal input line to an output line and disconnects the second to fourth signal input lines from the output line, wherein during a second period, subsequent to the first period within the sensing period, in which a second application of the gate-on voltage is applied a second one of four times, the multiplexer disconnects the first, third, and fourth signal input lines from the output line and electrically connects the second signal input line to the output line, wherein during a third period, subsequent to the second period within the sensing period, in which a third application of the gate-on voltage is applied a third one of four times, the multiplexer disconnects the first, second, and fourth signal input lines from the output line and electrically connects the third signal input line to the output line, wherein during a fourth period, subsequent to the third period within the sensing period, in which a fourth application of the gate-on voltage is applied a fourth one of four times, the multiplexer disconnects the first to third signal input lines from the output line and electrically connects the fourth signal input line to the output line, and wherein a gate-off voltage is applied to the horizontal driving line throughout a period between each of the first to fourth applications of the gate-on voltage.
a selection circuit connected to n of the signal input lines and to one output line, the selection circuit configured to sequentially output n sensing signals received through the n signal input lines to the one output line, where n is a natural number of 2 or more and the selection circuit includes n selection transistors connected between the n signal input lines and the one output line
and a vertical driver configured to receive the n sensing signals through the one output line, wherein the horizontal driver applies the horizontal driving signal to a given one of the driving lines n times to correspond to the n sensing signals, wherein each of n sensor pixels among the sensor pixels include a pixel transistor connected to a corresponding one of the n signal input lines, and during each of n sequential periods of part of a sensing period, the n times of the horizontal driving signal of a gate-on voltage level is applied to the given one driving line to turn on the pixel transistor of one of the n sensor pixels while a sensing signal control signal is applied to turn on a corresponding one of the n selection transistors
wherein the vertical driver comprises: an integration circuit for integrating a corresponding one of the sensing signals to generate a first output signal; an analog-to-digital converter that converts the first output signal of an analog type into a sensing data signal of a digital type; and a correlated double sampling circuit disposed between an output terminal of the integration circuit and the analog-to-digital converter, wherein the correlated double sampling circuit comprises: a first sampling switch disposed between the output terminal and the analog-to-digital converter; a second sampling switch disposed between the output terminal and the analog-to-digital converter; a first sampling capacitor including one terminal connected between the first sampling switch and the analog-to-digital converter; a second sampling capacitor including one terminal connected between the second sampling switch and the analog-to-digital converter; and a differential amplifier including a first input terminal connected to one terminal of the first sampling capacitor, a second input terminal connected to one terminal of the second sampling capacitor, and an output terminal, and wherein each of the n selection transistors is turned on before the first sampling switch is turned on, and is turned off after the second sampling switch is turned off.
Therefore, besides the wording, Patent teaches all the limitations of claim 1 with the exception of horizontal driving line extending in a second direction crossing the first direction; a third sensor pixel connected to a third signal input line different from the first and second signal input lines and connected to the horizontal driving line; a fourth sensor pixel connected to a fourth signal input line different from the first to third signal input lines and connected to the horizontal driving line. However, Talebzadeh teaches horizontal driving line RD[1] extending in a second direction crossing the first direction as shown in figure 3; a third sensor pixel connected to a third signal input line different from the first and second signal input lines and connected to the horizontal driving line; a fourth sensor pixel connected to a fourth signal input line different from the first to third signal input lines and connected to the horizontal driving line (Figures 3-4, pixels connected to RD[1] and VMON3-4). Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to provide RD as shown in figure 3 with the benefit that the digital controller 16 sends light detector control signals 3051 to 305n to the gate driver 12 to address the light detector circuits 300(1)(1) to 300(n)(m) in the display panel 20 sequentially one row of pixels 22, i.e. light emitting devices 214, at a time using RD lines RD(1) to RD(n), respectively. The light detector control signals on the RD lines RD(1) to RD(n) activate the switches 302 in each row of pixels consecutively, row by row, enabling each photodetector 301 to transmit a light detector current signal corresponding to the luminance of the corresponding light emitting device 214 via a corresponding monitor line VMON(1) to VMON(m).
In addition,
Claim 2 is taught by claim 1 of Patent in view of Talebzadeh
Claim 3 is taught by claim 1 of Patent in view of Talebzadeh
Claim 4 is taught by claim 1 of Patent in view of Talebzadeh
Claim 5 is taught by claim 1 of Patent in view of Talebzadeh
Claim 6 is taught by claim 2 of Patent
Claim 7 is taught by claim 1 of Patent
Claim 8 is taught by claim 1 of Patent in view of Talebzadeh
Claim 9 is taught by Claim 5 of Patent
Claim 10 is taught by Claim 1 of Patent in view of Talebzadeh
Claim 11 is taught by Claim 1 of Patent
Claim 12 is taught by Claim 9 of Patent
Allowable Subject Matter
Claims 1-12 are allowed if double patenting is overcome.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 1 is related to a display device comprising: a first sensor pixel connected to a first signal input line extending in a first direction and a horizontal driving line extending in a second direction crossing the first direction; a second sensor pixel connected to a second signal input line different from the first signal input line and connected to the horizontal driving line; a third sensor pixel connected to a third signal input line different from the first and second signal input lines and connected to the horizontal driving line; a fourth sensor pixel connected to a fourth signal input line different from the first to third signal input lines and connected to the horizontal driving line; and a multiplexer, wherein during a sensing period within a single frame period, a gate-on voltage is applied to the horizontal driving line four times, wherein during a first period within the sensing period, in which a first application of the gate-on voltage is applied a first one of four times, the multiplexer electrically connects the first signal input line to an output line and disconnects the second to fourth signal input lines from the output line, wherein during a second period, subsequent to the first period within the sensing period, in which a second application of the gate-on voltage is applied a second one of four times, the multiplexer disconnects the first, third, and fourth signal input lines from the output line and electrically connects the second signal input line to the output line, wherein during a third period, subsequent to the second period within the sensing period, in which a third application of the gate-on voltage is applied a third one of four times, the multiplexer disconnects the first, second, and fourth signal input lines from the output line and electrically connects the third signal input line to the output line, wherein during a fourth period, subsequent to the third period within the sensing period, in which a fourth application of the gate-on voltage is applied a fourth one of four times, the multiplexer disconnects the first to third signal input lines from the output line and electrically connects the fourth signal input line to the output line, and wherein a gate-off voltage is applied to the horizontal driving line throughout a period between each of the first to fourth applications of the gate-on voltage. Independent claim 10 recites similar limitations.
Talebzadeh teaches in figures 3-5, a first sensor pixel 300(1) (1), second sensor pixel 300(1) (2), third sensor pixel 300(1) (3), four sensor pixel 300 (1) (m), horizontal driving line 3051, signal input lines VMON[1-m], multiplexer 307. In addition, Talebzadeh teaches a gate-on voltage RD[1] is applied to the horizontal driving 3051 line a plurality of times in figures 3-5; and multiplexer is connected to signal input lines in response to Φ1-Φ4. However, Talebzadeh does not appear to specifically disclose all the above underlined limitations in combination to other limitations in the claim.
Hashimoto U.S. Patent Publication No. 2013/0162874 teaches in figure 6, sensor pixel 101, selection circuit SEL, correlated double sampling circuit 103. In addition, figures 6-7 show first sampling switch and second sampling switch in 103 with respect to CTS and CTN. However, Hashimoto does not appear to specifically disclose all the above underlined limitations.
Kato U.S. Patent Publication No. 2010/0073537 teaches in figure 2, pixel circuit, integration circuit 150, correlated double sampling circuit 160 including sampling switches 221-222. However, Kato does not appear to specifically disclose all the above underlined limitations.
Conclusion
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/ROBERTO W FLORES/Primary Examiner, Art Unit 2621
