Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In the response to this office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
INFORMATION DISCLOSURE STATEMENT
The information disclosure statements filed 1/15/2026 and 09/15/2026, have been acknowledged and considered by the examiner. Initialed copies of the PTO-1449 forms are included in this correspondence.
CLAIM REJECTIONS - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention
1. Claims 1-2 are rejected under 35 U.S.C. 102 (a) (2) as being anticipated by Lin et al. US 20210272945.
Consider claim 1. Lin disclose a manufacturing method of pixel package abstract multiple pixel package structure fig. 17-25 shows manufacturing steps , comprising:
providing a plurality of bottom electrodes fig. 3 fig. 9-10 fig. 20-23 4b or 6b and a non-light-emitting semiconductor element fig. 3 fig. 9-10 fig. 20-23 control chip 2;
disposing a lower insulating layer to cover the plurality of bottom electrodes and the non-light-emitting semiconductor element fig. 3 fig. 9-10 fig. 20-23 see insulating layers and base layer 3a 3b
disposing a lower circuit layer on the lower insulating layer, wherein the lower circuit layer is electrically connected to the non-light-emitting semiconductor element fig. 5 upper patterned metal 4a electrically connect to control chip 2 fig. 9-10 also see fig. 20-23 ;
disposing an upper insulating layer on the lower circuit layer fig. 9 5a fig. 24-25 5a, wherein the lower insulating layer and the upper insulating layer comprise a plurality of conductive pillars fig.9-10 31a 31b and 14 conductive via also see figs 22 31a 24-25 51a.
disposing an upper circuit layer on the upper insulating layer fig. 24 25 6a, wherein the upper circuit layer is electrically connected to the lower circuit layer and the plurality of bottom electrodes through the plurality of conductive pillars fig. 10 31a 31b and 14 conductive via also see figs 22 31a 24-25 51a;
disposing a plurality of light-emitting semiconductor elements on and electrically connected to the upper circuit layer fig. 13 light emitting elements 8a-8c connect to second upper patterned meal layer 6a. also see fig. 28 ; and
disposing a light-transmitting protective layer to cover the plurality of light-emitting semiconductor elements fig. 13-14 [0069] protective layer 9 covers light emitting elements.
Consider claim 2. Lin disclose a manufacturing method of pixel package as claimed in claim 1, further comprising: providing a solder mask to cover the lower insulating layer and the bottom surface of the non-light-emitting semiconductor element [0067] The solder mask layer (not shown) can also be formed on the second lower insulating core layer 5b. see 5b in figs 2-3 fig. 9-10 fig. 23-25.
CLAIM REJECTIONS - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 , if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. US 20210272945 in view of Lin et al. US 11251350 hereinafter “Lin2”.
Consider claim 3. Lin discloses the manufacturing method of pixel package as claimed in claim 1, but does not disclose wherein after disposing the lower circuit layer and before disposing the upper insulating layer, the manufacturing method further comprises: disposing a middle insulating layer to cover the lower circuit layer; and disposing a middle circuit layer on the middle insulating layer, wherein the middle circuit layer is electrically connected with the upper circuit layer, the lower circuit layer, and the bottom electrodes through the plurality of conductive pillars.
Lin2 however discloses wherein after disposing the lower circuit layer and before disposing the upper insulating layer, the manufacturing method further comprises: disposing a middle insulating layer to cover the lower circuit layer; and disposing a middle circuit layer on the middle insulating layer, wherein the middle circuit layer is electrically connected with the upper circuit layer, the lower circuit layer, and the bottom electrodes through the plurality of conductive pillars. See fig. 1B-1F before insulation layer 160 is formed and after insulation layer 140 insulation layers 154 are formed. Also, middle circuit layer 156 is formed on 154. Furthermore, middle circuits is connected to upper circuit 156 and lower circuit 152.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the pixel package of Lin to include wherein after disposing the lower circuit layer and before disposing the upper insulating layer, the manufacturing method further comprises: disposing a middle insulating layer to cover the lower circuit layer; and disposing a middle circuit layer on the middle insulating layer, wherein the middle circuit layer is electrically connected with the upper circuit layer, the lower circuit layer, and the bottom electrodes through the plurality of conductive pillars, as taught by Lin2, to improve yield and mitigate a problem of large warpage of PCB Col. 1 lines 41-45.
Consider claim 4. Lin discloses the manufacturing method of pixel package as claimed in claim 1, but does not disclose further comprising providing a temporary carrier for the plurality of bottom electrodes and a non-light-emitting semiconductor element to be disposed on.
Lin2 however discloses further comprising providing a temporary carrier for the plurality of bottom electrodes and a non-light-emitting semiconductor element to be disposed on. Col. 4 lines 26-29 a temporary substrate 110 is first provided. The temporary substrate 110 includes a rigid substrate 112 and a lift-off layer 114 disposed on the rigid substrate. See fig. 1a-1b 110 under chip 130 and electrodes 120/124.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the pixel package of Lin to include further comprising providing a temporary carrier for the plurality of bottom electrodes and a non-light-emitting semiconductor element to be disposed on, as taught by Lin2, to provide mechanical support for fragile pixel dies.
Consider claim 5. Lin as modified by Lin2 discloses the manufacturing method of pixel package as claimed in claim 4, further comprising removing the temporary carrier to expose the lower insulating layer, the plurality of bottom electrodes and the non-light-emitting semiconductor element Lin2 adhesion layer 180 is pressed on the layer 160 before temporary substrate 110 is removed Col. 6 lines 29-30.
CONCLUSION
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IBRAHIM A KHAN whose telephone number is (571)270-7998. The examiner can normally be reached on 10am-6pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nitin Patel can be reached on 571-272-7677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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IBRAHIM A. KHAN
Primary Examiner
Art Unit 2628
/IBRAHIM A KHAN/ 09/29/2026Primary Examiner, Art Unit 2628
