DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claims 1-10 and 14-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 4, 6-7, 9-11, 17, and 19-20 of U.S. Patent No. 12,579,941. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant claims are narrower than the patented claim but contain all of the same limitations.
Current Claim
Patented Claim
1. A pixel driving circuit, comprising: a driving transistor, comprising a first electrode configured to load a first power supply voltage, a second electrode connected to a third node, and a gate connected to a first node; a first transistor, connected to a second node, configured to output a data voltage to the second node in response to a first scan signal; a second transistor, connected to the first node and the third node; a fifth transistor, connected to the second node, configured to output a reference voltage to the second node in response to a first reset signal; a seventh transistor, connected to the third node and a fourth node, configured to electrically communicate the third node with the fourth node in response to a light emitting control signal; and a storage capacitor, connected to the first node and the second node, wherein the storage capacitor is configured to store the data voltage and a threshold voltage of the driving transistor.
1. A pixel driving circuit, comprising: a driving transistor, connected to a first node and a third node; a first transistor, connected to a second node, configured to output a data voltage to the second node in response to a first scan signal; a second transistor, connected to the first node and the third node; a fifth transistor, connected to the second node, configured to output a reference voltage to the second node in response to a first reset signal; a seventh transistor, connected to the third node and a fourth node, configured to electrically communicate the third node with the fourth node in response to a light emitting control signal; and a storage capacitor, connected to the first node and the second node, wherein the storage capacitor is configured to store the data voltage and a threshold voltage of the driving transistor.
2. The pixel driving circuit according to claim 1, further comprising an eighth transistor, wherein a first electrode of the eighth transistor is configured to load an initialization voltage, and a second electrode of the eighth transistor is connected to the fourth node.
2. The pixel driving circuit according to claim 1, further comprising a fourth transistor, wherein a first electrode of the fourth transistor is configured to load an initialization voltage, and a second electrode of the fourth transistor is connected to the first node.
3. The pixel driving circuit according to claim 2, wherein materials of active layers of the first transistor, the driving transistor, the fifth transistor, the seventh transistor, and the eighth transistor are all polysilicon semiconductor materials.
6. The pixel driving circuit according to claim 4, wherein materials of active layers of the first transistor, the driving transistor, the fifth transistor, the seventh transistor, and the eighth transistor are all polysilicon semiconductor materials.
4. The pixel driving circuit according to claim 1, wherein the storage capacitor comprises a first electrode plate and a second electrode plate, the first electrode plate is located in a first gate layer of a display panel, and the second electrode plate is located in a second gate layer of the display panel; wherein the second electrode plates adjacently arranged along a row direction are independently provided.
7. The pixel driving circuit according to claim 1, wherein the storage capacitor comprises a first electrode plate and a second electrode plate, the first electrode plate is located in a first gate layer of a display panel, and the second electrode plate is located in a second gate layer of the display panel; wherein the second electrode plates adjacently arranged along a row direction are independently provided.
5. The pixel driving circuit according to claim 4, wherein the first electrode plate covers a channel region of the driving transistor to be reused as a gate of the driving transistor.
17. The pixel driving circuit according to claim 7, wherein the first electrode plate covers a channel region of the driving transistor to be reused as a gate of the driving transistor.
6. The pixel driving circuit according to claim 1, wherein the display panel is provided with a second metal wiring layer, the second metal wiring layer is provided with a first power supply voltage lead, a data lead, and a transfer metal structure, and a pixel electrode of a light-emitting element is connected to the transfer metal structure through a via hole.
9. The pixel driving circuit according to claim 1, wherein the display panel is provided with a second metal wiring layer, the second metal wiring layer is provided with a first power supply voltage lead, a data lead, and a transfer metal structure, and a pixel electrode of a light-emitting element is connected to the transfer metal structure through a via hole.
7. The pixel driving circuit according to claim 1, wherein the display panel comprises a base substrate, a driving circuit layer, and a pixel layer sequentially stacked; wherein the pixel driving circuit is provided in the driving circuit layer; the pixel layer comprises a red light emitting element, a green light emitting element, and a blue light emitting element; and a pixel electrode of a light-emitting element is electrically connected to the pixel driving circuit.
10. The pixel driving circuit according to claim 1, wherein the display panel comprises a base substrate, a driving circuit layer, and a pixel layer sequentially stacked; wherein the pixel driving circuit is provided in the driving circuit layer; the pixel layer comprises a red light emitting element, a green light emitting element, and a blue light emitting element; and a pixel electrode of a light-emitting element is electrically connected to the pixel driving circuit.
8. The pixel driving circuit according to claim 6, wherein the transfer metal structure comprises a top via hole region and a transfer via hole region, wherein the transfer metal structure is electrically connected to the pixel electrode of the light-emitting element via the via hole in the transfer via hole region; and the transfer metal structure is electrically connected to a second electrode of the seventh transistor via a via hole in the top via hole region.
9. The pixel driving circuit according to claim 1, wherein during a threshold voltage compensation phase, the first node is charged to a voltage of VDD+Vth; wherein the VDD is the first power supply voltage, and the Vth is the threshold voltage of the driving transistor.
11. The pixel driving circuit according to claim 1, wherein during a threshold voltage compensation phase, the first node is charged to VDD+Vth; wherein the VDD is a first power supply voltage, and the Vth is the threshold voltage of the driving transistor.
10. The pixel driving circuit according to claim 1, wherein the pixel driving circuit is applied to a display panel, and the display panel comprises a first gate layer; a gate of the second transistor comprises a first gate located at the first gate layer, the first gate layer is provided with a second scan lead configured to load a second scan signal, and the second scan lead is electrically connected to the first gate of the second transistor, such that the second scan signal is loaded to the first gate of the second transistor.
19. The pixel driving circuit according to claim 1, wherein the pixel driving circuit is applied to a display panel, and the display panel comprises a first gate layer; a gate of the second transistor comprises a first gate located at the first gate layer, the first gate layer is provided with a second scan lead configured to load a second scan signal, and the second scan lead is electrically connected to the first gate of the second transistor, such that the second scan signal is loaded to the first gate of the second transistor.
11. A pixel driving method, applied to the pixel driving circuit according to claim 1, wherein the driving method of the pixel driving circuit comprises: in a reset phase, loading the reference voltage to the second node by loading the first reset signal to a first reset unit; loading an initialization voltage to the first node by loading a second reset signal to a second reset unit; in a data writing phase, loading the data voltage to the second node by loading the first scan signal to a data writing unit; communicating the first node with the third node until a current between the first node and the third node is zero by loading a second scan signal to a threshold compensation unit, such that a threshold voltage of the driving transistor is written into the first node; in a light emitting phase, communicating the third node with the fourth node and loading the reference voltage to the second node by loading the light emitting control signal to a light emitting control unit and the first reset unit.
12. The pixel driving method according to claim 11, wherein in the data writing phase, a data voltage of the driving transistor and the threshold voltage of the driving transistor are written to two ends of the storage capacitor, respectively, wherein the first node is charged to a voltage of VDD+Vth, and the second node is written with the data voltage, such that data writing and threshold voltage compensation of the driving transistor are performed in a same phase.
13. The pixel driving method according to claim 11, wherein in the light emitting phase, the first reset unit is controlled by the light emitting control signal to reset the second node, a voltage of the second node is switched from Vdata to Vref, a voltage of the first node is switched to a voltage of VDD+Vth+Vref−Vdata; wherein the VDD is the first power supply voltage, the Vth is the threshold voltage of the driving transistor; the Vdata is the data voltage, and the Vref is the reference voltage.
14. A display panel comprising: a pixel driving circuit, wherein the pixel driving circuit comprises: a driving transistor, comprising a first electrode configured to load a first power supply voltage, a second electrode connected to a third node, and a gate connected to a first node; a first transistor, connected to a second node, configured to output a data voltage to the second node in response to a first scan signal; a second transistor, connected to the first node and the third node; a fifth transistor, connected to the second node, configured to output a reference voltage to the second node in response to a first reset signal; a seventh transistor, connected to the third node and a fourth node, configured to electrically communicate the third node with the fourth node in response to a light emitting control signal; and a storage capacitor, connected to the first node and the second node, wherein the storage capacitor is configured to store the data voltage and a threshold voltage of the driving transistor.
20. A display panel comprising: a pixel driving circuit, and the pixel driving circuit comprises: a driving transistor, connected to a first node and a third node; a first transistor, connected to a second node, configured to output a data voltage to the second node in response to a first scan signal; a second transistor, connected to the first node and the third node; a fifth transistor, connected to the second node, configured to output a reference voltage to the second node in response to a first reset signal; a seventh transistor, connected to the third node and a fourth node, configured to electrically communicate the third node with the fourth node in response to a light emitting control signal; and a storage capacitor, connected to the first node and the second node, wherein the storage capacitor is configured to store the data voltage and a threshold voltage of the driving transistor.
15. The display panel according to claim 14, further comprising: a base substrate; a driving circuit layer; and a pixel layer; wherein the base substrate, the driving circuit layer and the pixel layer are sequentially stacked, the pixel driving circuit is arranged in the driving circuit layer,
and the pixel layer is provided with a light emitting element corresponding to the pixel driving circuit; wherein a first end of the light emitting element is loaded with a second power supply voltage, and a second end of the light emitting element is electrically connected to a fourth node.
10. The pixel driving circuit according to claim 1, wherein the display panel comprises a base substrate, a driving circuit layer, and a pixel layer sequentially stacked; wherein the pixel driving circuit is provided in the driving circuit layer;
the pixel layer comprises a red light emitting element, a green light emitting element, and a blue light emitting element; and a pixel electrode of a light-emitting element is electrically connected to the pixel driving circuit.
16. The display panel according to claim 14, wherein the pixel driving circuit further comprises: an eighth transistor, wherein a first electrode of the eighth transistor is configured to load an initialization voltage, and a second electrode of the eighth transistor is connected to the fourth node.
4. The pixel driving circuit according to claim 1, further comprising an eighth transistor, wherein a first electrode of the eighth transistor is configured to load an initialization voltage, and a second electrode of the eighth transistor is connected to the fourth node.
17. The display panel according to claim 16, wherein materials of active layers of the first transistor, the driving transistor, the fifth transistor, the seventh transistor, and the eighth transistor are all polysilicon semiconductor materials.
6. The pixel driving circuit according to claim 4, wherein materials of active layers of the first transistor, the driving transistor, the fifth transistor, the seventh transistor, and the eighth transistor are all polysilicon semiconductor materials.
18. The display panel according to claim 14, wherein the storage capacitor comprises a first electrode plate and a second electrode plate, the first electrode plate is located in a first gate layer of a display panel, and the second electrode plate is located in a second gate layer of the display panel; wherein the second electrode plates adjacently arranged along a row direction are independently provided.
7. The pixel driving circuit according to claim 1, wherein the storage capacitor comprises a first electrode plate and a second electrode plate, the first electrode plate is located in a first gate layer of a display panel, and the second electrode plate is located in a second gate layer of the display panel; wherein the second electrode plates adjacently arranged along a row direction are independently provided.
19. The display panel according to claim 18, wherein the first electrode plate covers a channel region of the driving transistor to be reused as a gate of the driving transistor.
17. The pixel driving circuit according to claim 7, wherein the first electrode plate covers a channel region of the driving transistor to be reused as a gate of the driving transistor.
20. The display panel according to claim 14, wherein the display panel is provided with a second metal wiring layer, the second metal wiring layer is provided with a first power supply voltage lead, a data lead, and a transfer metal structure, and a pixel electrode of a light-emitting element is connected to the transfer metal structure through a via hole.
9. The pixel driving circuit according to claim 1, wherein the display panel is provided with a second metal wiring layer, the second metal wiring layer is provided with a first power supply voltage lead, a data lead, and a transfer metal structure, and a pixel electrode of a light-emitting element is connected to the transfer metal structure through a via hole.
Allowable Subject Matter
Claims 11-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: none of the prior art of record, taken alone or in combination, teaches the specifics of the claims, especially “in a reset phase, loading the reference voltage to the second node by loading the first reset signal to a first reset unit; loading an initialization voltage to the first node by loading a second reset signal to a second reset unit; in a data writing phase, loading the data voltage to the second node by loading the first scan signal to a data writing unit; communicating the first node with the third node until a current between the first node and the third node is zero by loading a second scan signal to a threshold compensation unit, such that a threshold voltage of the driving transistor is written into the first node; in a light emitting phase, communicating the third node with the fourth node and loading the reference voltage to the second node by loading the light emitting control signal to a light emitting control unit and the first reset unit” as recited in claim 11. Claims 12-13 are objected to as being dependent on an allowable base claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The closest prior art is made of record in the attached notice of references cited.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PARUL H GUPTA whose telephone number is (571)272-5260. The examiner can normally be reached Monday through Friday, from 10 AM to 7 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at 571-272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PARUL H GUPTA/Primary Examiner, Art Unit 2627
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