DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed: DISPLAY APPARATUS HAVING REPAIR MODULE UTILIZING PREPROCESSED REPAIR IMAGE DATA AND CONTROL METHOD THEREFOR.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office Action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2005/0110738 A1, IDS, hereinafter Kim 1) in view of Oh et al. (US 2006/0124966 A1).
As to claim 1, Kim 1 teaches a display apparatus (Kim 1, e.g., FIG. 1, [0007], “conventional active matrix LCD device”), comprising:
a display panel (Kim 1, FIG. 1, [0011], “liquid crystal panel 150”) and a source driver (Kim 1, FIGS. 1-2, [0080], “source driver IC 200”) located on at least one side of the display panel (Kim 1, see FIG. 1, [0011], “liquid crystal panel 150”),
wherein the display panel (Kim 1, FIG. 1, [0011], “liquid crystal panel 150”) is provided with sub-pixels (Kim 1, FIG. 1, [0010], “pixels”) arranged in an array (Kim 1, see FIG. 1) and a plurality of data signal lines (Kim 1, see FIGS. 1-2, [0071], “source line SL1, SL2, . . . , SLk-1 and SLk”), and the sub-pixels (Kim 1, FIG. 1, [0010], “pixels”) are electrically connected to the data signal lines (Kim 1, see FIGS. 1-2, [0071], “source line SL1, SL2, . . . , SLk-1 and SLk”), and
the display apparatus (Kim 1, e.g., FIG. 1, [0007], “conventional active matrix LCD device”) further comprises
a repair module (Kim 1, FIG. 2, [0077], “repair circuit 260”) and a plurality of data signal transmission lines (Kim 1, FIGS. 1-2, [0077], “output signals Yl, Y2, . . . , Yk-1”), and extension directions of the data signal transmission lines (Kim 1, FIGS. 1-2, [0077], “output signals Yl, Y2, . . . , Yk-1”) are the same as extension directions of the data signal lines (Kim 1, see FIGS. 1-2, [0071], “source line SL1, SL2, . . . , SLk-1 and SLk”),
the data signal transmission lines (Kim 1, FIGS. 1-2, [0077], “output signals Yl, Y2, . . . , Yk-1”) are electrically connected to the source driver (Kim 1, see FIGS. 1-2, [0080], “source driver IC 200”) and the data signal lines (Kim 1, see FIGS. 1-2, [0071], “source line SL1, SL2, . . . , SLk-1 and SLk”), respectively, the source driver (Kim 1, see FIGS. 1-2, [0080], “source driver IC 200”) is electrically connected to an unbroken data signal transmission line (Kim 1, FIGS. 1-2, [0077], “output signals Y2, . . . , Yk-1”, i.e., excluding “Y1”), and is configured to provide a data signal (Kim 1, FIGS. 1-2, [0071], “the `DATA` is inputted to latch unit 220”) to the unbroken data signal transmission line (Kim 1, FIGS. 1-2, [0077], “output signals Y2, . . . , Yk-1”, i.e., excluding “Y1”), and
the repair module (Kim 1, FIG. 2, [0077], “repair circuit 260”) is electrically connected to a data signal line (Kim 1, e.g., see FIGS. 1-2, [0071], “source line SL1P”) connected to a broken data signal transmission line (Kim 1, FIGS. 1-2, [0077], “Y1” via “N1A”), and is configured to provide a data signal to the data signal line connected to the broken data signal transmission line (Kim 1, FIGS. 1-2, [0078], “the repair circuit 260 provides the signal RCO1 corresponding to the output signal Y1 of a driver IC 200 to one end SL1P of a disconnected source line, to which the output signal Y1 of the source driver IC 200 is not supplied, via a dummy input line LDI1 and a dummy output line LDO1 when at least one of the source lines arranged in liquid crystal panel is disconnected”).
Kim 1 does not teach “some of the data signal transmission lines are broken”.
However, Oh teaches the concept that some of the data signal transmission lines are broken (Oh, FIG. 2, [0044], e.g., “opened area(s) OP1 OP2”).
At the time of effective filing date, it would have been obvious to one of ordinary skill in the art to modify the “repair circuit 260” taught by Kim 1 to further detect the “opened area(s) OP1 OP2” on the “data signal transmitting lines DFL”, as taught by Oh, in order to “provide an array substrate capable of improving a manufacturing yield and preventing signal distortion” (Oh, [0010]).
As to claim 18, Kim 1 teaches a control method for a display apparatus, configured to control the display apparatus according to claim l, comprising: providing, by a source drive circuit (Kim 1, FIG. 1, [0059], “source driver 1000”), a data signal to an unbroken data signal transmission line (Kim 1, see FIGS. 1-2, [0077], “output signals Y2, . . . , Yk-1, Yk”), and providing, by a repair module (Kim 1, FIG. 2, [0077], “repair circuit 260”), a data signal to a data signal line connected to a broken data signal transmission line (Kim 1, see FIGS. 1-2, [0077], “output signal Yl”).
Claims 2-3 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2005/0110738 A1, IDS, Kim 1) in view of Oh et al. (US 2006/0124966 A1) and Huang (US 2020/0013319 A1).
As to claim 2, Kim 1 teaches the display apparatus according to claim 1, wherein when the display apparatus (Kim 1, e.g., FIG. 1, [0007], “conventional active matrix LCD device”) comprises a peripheral area (Oh, e.g., see FIGS. 1-2, [0031], “peripheral area PA”), the source driver (Kim 1, see FIGS. 1-2, [0080], “source driver IC 200”) is disposed on the peripheral area (Oh, e.g., see FIGS. 1-2, [0031], “peripheral area PA”), and the repair module (Kim 1, FIG. 2, [0077], “repair circuit 260”) is disposed on at least one of the display panel and the peripheral area (Kim 1, see FIGS. 1-2, [0080], “source driver IC 200” comprises “repair circuit 260”), and the data signal transmission lines (Kim 1, FIGS. 1-2, [0077], “output signals Yl, Y2, . . . , Yk-1”) are disposed on the display panel (Kim 1, see FIGS. 1-2, one ends of “output signals Yl, Y2, . . . , Yk-1” extend to “panel 150”) and the peripheral area (Kim 1, see FIGS. 1-2, the other ends of “output signals Yl, Y2, . . . , Yk-1” extend to “source driver IC 200”).
Kim 1 does not explicitly teach that the peripheral area is a “chip on film”.
However, Huang teaches the concept that the peripheral area is a chip on film (Huang, [0002], “source chip-on-film (S-COF)”).
At the time of effective filing date, it would have been obvious to one of ordinary skill in the art to modify the “peripheral area PA” taught by Kim 1 to further comprise the “chip on film”, as taught by Huang, as a routine engineering choice (Huang, [0002], “In an active array switch (thin film transistor, TFT) display, a system board is connected to a control board (C-board) by using a line. For example, the C-board is connected to a printed circuit board (PCB) by using a flexible flat cable (FFC), and the PCB is connected to a display area by using a source chip-on-film (S-COF) and a gate chip-on-film (G-COF)”).
As to claim 3, Kim 1 teaches the display apparatus according to claim 2, wherein
the source driver (Kim 1, FIG. 2, [0060], “ source driver IC 1000”) comprises a data processing circuit (Kim 1, FIG. 1, [0008], “controller 100”) and a plurality of signal output circuits (Kim 1, FIG. 1, “source driver ICs 200, 400, 600 and 800”), and a signal output circuit of the plurality of signal output circuits (Kim 1, FIG. 1, “source driver ICs 200, 400, 600 and 800”) comprises a shift register (Kim 1, FIGS. 1-2, [0061], “shift register 210”), a data latch circuit (Kim, 1, FIG. 2, [0066], “latch unit 220”), a level conversion circuit (Kim 1, FIGS. 1-2, [0068], “level shifter 225”), a digital-to-analog conversion circuit (Kim 1, FIGS. 1-2, [0069], “digital-to-analog converter 230”), and an output buffer circuit (Kim 1, FIGS. 1-2, [0073], “buffer unit 240” in association with “switch unit 250”),
the data processing circuit (Kim, FIG. 1, [0008], “controller 100”) is configured to preprocess received image data (Kim 1, FIG. 1, [0008], “receives video data and control signals, and … and gray scale data DATA to the source driver 1000”),
the shift register (Kim 1, FIGS. 1-2, [0061], “shift register 210”) is electrically connected to the data processing circuit (Kim, see FIGS. 1-2, [0008], “controller 100”) and is configured to sample and output preprocessed image data to generate a first data signal (Kim 1, FIG. 2, [0063], “outputs pulses to the latch unit 220 every given number of clocks in accordance with horizontal clock signals H_CL”),
the data latch circuit (Kim, 1, FIG. 2, [0066], “latch unit 220”) is electrically connected to the shift register (Kim 1, FIGS. 1-2, [0061], “shift register 210”) and is configured to latch the first data signal and output a second data signal (Kim 1, FIGS. 1-2, [0067], “latches the `DATA` in response to the pulses output from the shift register 210, and outputs the `DATA` in response to a load signal `TP`”),
the level conversion circuit (Kim 1, FIGS. 1-2, [0068], “level shifter 225”) is electrically connected to the data latch circuit (Kim, 1, FIG. 2, [0066], “latch unit 220”) and is configured to convert the second data signal to a third data signal, and a level of the third data signal is greater than a level of the second data signal (Kim 1, FIGS. 1-2, [0068], “raises the voltage level of the output signal of the latch unit 220”),
the digital-to-analog conversion circuit (Kim 1, FIGS. 1-2, [0069], “digital-to-analog converter 230”) is configured to convert the third data signal into a data signal, the third data signal is a digital signal and the data signal is an analog signal (Kim 1, FIGS. 1-2, [0070], “generates k voltage signals to output the k voltage signals to the buffer unit 240”),
the output buffer circuit (Kim 1, FIGS. 1-2, [0073], “buffer unit 240” in association with “switch unit 250”) is electrically connected to the digital-to-analog conversion circuit (Kim 1, FIGS. 1-2, [0069], “digital-to-analog converter 230”) and a data signal transmission line of the data signal transmission lines (Kim 1, FIGS. 1-2, [0077], “output signals Yl, Y2, . . . , Yk-1”), and is configured to send the data signal to the unbroken data signal transmission line (Kim 1, FIGS. 1-2, [0074], “includes SWITCH1, SWITCH2, . . . , SWITCHk respectively corresponding to the source line SL1, SL2, . . . , SLk-1 and SLk”),
the shift register (Kim 1, FIGS. 1-2, [0061], “shift register 210”) comprises at least one shift register unit, and when the shift register comprises a plurality of shift register units, the plurality of shift register units located in a same shift register are cascaded with each other (Kim 1, FIGS. 1-2, [0065], “the carry-out signal is supplied to a following shift register unit 210 (not shown)”), and
the plurality of data signal transmission lines (Kim 1, FIGS. 1-2, [0077], “output signals Yl, Y2, . . . , Yk-1”) and the plurality of data signal lines (Kim 1, see FIGS. 1-2, [0071], “source line SL1, SL2, . . . , SLk-1 and SLk”) are in a one-to-one correspondence relationship (Kim 1, see FIGS. 1-2), and a number of shift register units (Kim, see FIGS. 1-2, k) in the signal output circuit (Kim 1, FIG. 1, “source driver ICs 200, 400, 600 and 800”, e.g., 4k) is the same as a number of data signal transmission lines (Kim 1, FIGS. 1-2, [0077], “output signals Yl, Y2, . . . , Yk-1, Yk” × 4 = 4k) connected to the signal output circuit (Kim 1, FIG. 1, “source driver ICs 200, 400, 600 and 800”, e.g., 4k), and
there is a one-to-one correspondence relationship between the shift register units in the signal output circuit and the data signal transmission lines (Kim 1, FIGS. 1-2, [0077], “output signals Yl, Y2, . . . , Yk-1, Yk”) connected to the signal output circuit (Kim 1, FIG. 1, “source driver ICs 200, 400, 600 and 800”).
As to claim 17, Huang teaches the display apparatus according to claim 2, further comprising a printed circuit board, wherein the printed circuit board is electrically connected to the chip on film (Huang, [0002], “In an active array switch (thin film transistor, TFT) display, a system board is connected to a control board (C-board) by using a line. For example, the C-board is connected to a printed circuit board (PCB) by using a flexible flat cable (FFC), and the PCB is connected to a display area by using a source chip-on-film (S-COF) and a gate chip-on-film (G-COF)”).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2005/0110738 A1, IDS, Kim 1) in view of Oh et al. (US 2006/0124966 A1), Huang (US 2020/0013319 A1) and Wang et al. (US 2015/0212379 A1, IDS).
As to claim 4, Kim 1 in view of Oh and Huang does not teach the display apparatus according to claim 3, wherein the display apparatus further comprises a memory, and wherein the memory is configured to store a set of defect identifications, the set of defect identifications comprises an identification of a shift register unit electrically connected to the broken data signal transmission line, and the identification comprises a serial number of the shift register unit or an address of the shift register unit.
However, Wang teaches the concept that the display apparatus further comprises a memory, and wherein the memory is configured to store a set of defect identifications, the set of defect identifications comprises an identification of a shift register unit electrically connected to the broken data signal transmission line, and the identification comprises a serial number of the shift register unit (Wang, FIG. 3, [0060], “the serial numbers of poor signal leads of data lines in data lines connected with output channels in the source driver IC1 are determined at first. As a signal lead of data line connected with an output channel 2 of the source driver IC1 is poor and a signal lead of data line connected with an output channel 5 of the source driver IC1 is poor, the serial numbers of the poor signal leads of data lines in the data lines connected with the source driver IC1 are 2 and 5. If the serial numbers are sorted according to the order from small to large, the new serial number of the data line with the serial number 2 is 1, and the new serial number of the data line with the serial number 5 is 2”; it is reasonably inferred that there must be a memory for the “serial numbers” to be “stored”) or an address of the shift register unit.
At the time of effective filing date, it would have been obvious to one of ordinary skill in the art to modify the “repair circuit 260” taught by Kim 1 to further “store the serial numbers” of the “shift register” corresponding to the “poor signal lead of data line”, as taught by Wang, in order to “provide a display substrate and a method for repairing a lead of driver ICs, which are used for solving the problem of increasing the costs of products due to the waste of products as the traditional display panel cannot repair poor signal leads in the external lead area” (Wang, [0006]).
Allowable Subject Matter
Claims 5-16 and 19-20 would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 5, Kim 1 teaches the display apparatus according to claim 4, wherein the repair module (Kim 1, FIG. 2, [0077], “repair circuit 260”) comprises at least one repair output circuit (Kim 1, FIG. 2, [0088], a circuit corresponding to “repair output signal RCO1”), at least one repair signal transmission line (Kim 1, FIG. 2, e.g., 1st portion of “first dummy output line LDO1” receiving “RCO1”), and at least one repair signal connection line (Kim 1, FIG. 2, [0082], 2nd portion of “first dummy output line LDO1” outputting “RCO1”), and an extension direction of the repair signal transmission line (Kim 1, FIG. 2, e.g., 1st portion of “first dummy output line LDO1” receiving “RCO1”) intersects with an extension direction of the repair signal connection line (Kim 1, FIG. 2, [0082], 2nd portion of “first dummy output line LDO1” outputting “RCO1”), there is a one-to-one correspondence relationship between the repair signal transmission line (Kim 1, see FIG. 2, e.g., “output signal Y1”) and the repair signal connection line (Kim 1, see FIG. 2, [0082], “ first dummy output line LDO1”), and the extension direction of the repair signal transmission line (Kim 1, FIG. 2, e.g., 1st portion of “first dummy output line LDO1” receiving “RCO1”) is the same as the extension directions of the data signal transmission lines (Kim 1, FIGS. 1-2, [0077], “output signals Yl, Y2, . . . , Yk-1, Yk”).
However, the closest known prior art, i.e., Kim et al. (US 2005/0110738 A1, IDS), Oh et al. (US 2006/0124966 A1), Huang (US 2020/0013319 A1), Wang et al. (US 2015/0212379 A1, IDS) and Kim et al. (US 2016/0349565 A1), alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “the data processing circuit is configured to acquire the set of defect identifications stored in advance; determine whether an identification of a shift register unit by which image data is to be sent is located in the set of defect identifications stored in advance; when the identification of the shift register unit by which the image data is to be sent is not located in the set of defect identifications stored in advance, send the preprocessed image data to the shift register unit; and when the identification of the shift register unit by which the image data is to be sent is located in the set of defect identifications stored in advance, send preprocessed repair image data to the repair output circuit, the repair image data being image data to be provided to a shift register unit connected to the broken data signal transmission line, the repair output circuit is respectively electrically connected to the data processing circuit and at least one repair signal transmission line, and is configured to, according to the preprocessed repair image data, generate a data signal to be sent to the data signal line connected to the broken data signal transmission line, the repair signal connection line is respectively electrically connected to a corresponding repair signal transmission line and the data signal line connected to the broken data signal transmission line, and different repair signal connection lines are connected to different data signal lines, and a number of repair signal transmission lines is greater than or equal to a number of broken data signal transmission lines”.
As to claims 6-8, they directly or indirectly depend from claim 5, and are allowable at least for the same reason above.
As to claim 9, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “the repair module comprises a plurality of repair control circuits, a selection circuit, a repair signal transmission line, a first repair signal connection line, and a second repair signal connection line, and an extension direction of the first repair signal connection line and an extension direction of the second repair signal connection line intersect respectively with an extension direction of the repair signal transmission line, and the extension direction of the repair signal transmission line is the same as the extension directions of the data signal transmission lines, the data processing circuit is configured to generate a control signal, the repair control circuits are electrically connected to the data processing circuit and the selection circuit, respectively, and are configured to generate repair control signals according to the control signal, the selection circuit is electrically connected to the signal output circuits, the repair control circuits, the data signal transmission lines, and the first repair signal connection line, respectively, and is configured to transmit data signals output by the signal output circuits to the data signal transmission lines or the first repair signal connection line under control of the repair control signals, the repair signal transmission line is electrically connected to the first repair signal connection line and the second repair signal connection line, respectively, and the second repair signal connection line is electrically connected to the data signal line connected to the broken data signal transmission line”.
As to claims 10-12, they directly or indirectly depend from claim 9, and are allowable at least for the same reason above.
As to claim 13, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “the repair module comprises a plurality of repair signal connection lines, and extension directions of the repair signal connection lines intersect with the extension directions of the data signal lines, a repair signal connection line of the plurality of repair signal connection lines is electrically connected to the data signal line connected to the broken data signal transmission line and a data signal line connected to a data signal transmission line adjacent to the broken data signal transmission line, and repair signal connection lines connected to different data signal transmission lines are different, and a number of the repair signal connection lines is greater than or equal to a number of broken data signal transmission lines”.
As to claims 14-15, they depend from claim 13, and are allowable at least for the same reason above.
As to claim 16, it indirectly depend from claim 5, and is allowable at least for the same reason above.
As to claim 19, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “acquiring, by the data processing circuit, a set of defect identifications stored in advance, wherein the set of defect identifications comprises an identification of a shift register unit electrically connected to the broken data signal transmission line, and the identification comprises a serial number of the shift register unit or an address of the shift register unit, determining, by the data processing circuit, whether an identification of a shift register unit by which image data is to be sent is located in the set of defect identifications stored in advance; when the identification of the shift register unit by which the image data is to be sent is not located in the set of defective identifications stored in advance, sending, by the data processing circuit, preprocessed image data to the shift register unit; and when the identification of the shift register unit by which the image data is to be sent is located in the set of defect identifications stored in advance, sending, by the data processing circuit, preprocessed repair image data to a repair output circuit of the plurality of repair output circuits, wherein the repair image data is image data to be provided to a shift register unit connected to the broken data signal transmission line, and generating, by the repair output circuit, according to the preprocessed repair image data, a data signal to be provided to the data signal line connected to the broken data signal transmission line, and providing the data signal to the data signal line connected to the broken data signal transmission line”.
As to claim 20, it indirectly depend from claim 5, and is allowable at least for the same reason above.
Conclusion
The prior arts made of record and not relied upon are considered pertinent to applicant’s disclosure: Kim et al. (US 2016/0349565 A1) teaches the concept of “signal transmission lines, connection line connecting the GIP driver and the signal transmission lines” (Abs.);
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD J HONG whose telephone number is (571) 270-7765. The examiner can normally be reached on 9:00 AM to 6:00 PM EST.
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Jul. 17, 2026
/RICHARD J HONG/Primary Examiner, Art Unit 2623
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