DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/07/2026 has been placed in record and considered by the examiner.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Son Seung Sok (KR 20080100580A hereinafter Son) in view of Shi (US 20240194105 hereinafter Shi).
Referring to claim 1, Son discloses an array substrate (Son- highlighted section; Referring to FIG. 1, the display panel according to the present exemplary embodiment includes a first substrate 100, a second substrate facing the first substrate (not shown), and a liquid crystal layer interposed between the first and second substrates. (Not shown).), comprising a driving region and a first frame region located on a side of the driving region and extending in a first direction (Son- highlighted section; The first substrate 100 further includes a gate driving circuit 110. The gate driving circuit 110 is formed in the peripheral area AR2 and is formed on at least one side of both sides of the display area AR1 in the second direction. In FIG. 2, for example, the gate driving circuit 110 is formed on the left side of the display area AR1.), wherein the array substrate comprises:
a substrate (Son- highlighted section; Referring to FIG. 1, the display panel according to the present exemplary embodiment includes a first substrate 100, a second substrate facing the first substrate (not shown), and a liquid crystal layer interposed between the first and second substrates. (Not shown).); and
a driving circuit layer on a side of the substrate (Son- highlighted section; The first substrate 100 further includes a gate driving circuit 110. The gate driving circuit 110 is formed in the peripheral area AR2 and is formed on at least one side of both sides of the display area AR1 in the second direction. In FIG. 2, for example, the gate driving circuit 110 is formed on the left side of the display area AR1.), comprising:
a plurality of gate driving circuits in the first frame region, wherein the plurality of gate driving circuits comprise a dummy gate driving circuit and a starting row gate driving circuit (Son- highlighted section; FIG. 2 is a block circuit diagram illustrating a gate driving circuit of the first substrate of FIG. 1. 2, the gate driving circuit 110 according to the present exemplary embodiment includes a plurality of gate drivers 112 and a first dummy driver 114, and optionally further includes a second dummy driver 116. can do.);
a first signal line and a second signal line (Fig. 3; CL1, CL2), wherein the first signal line and the second signal line extend in the first direction (Fig. 3; CL1, CL2 extend in first direction), and the first signal line is located on a side of the second signal line away from the driving region (Son- highlighted section; The clock line may be electrically connected to the gate drivers 112 to apply the clock signal to the gate drivers 112. Specifically, for example, the first clock line CL1 may be electrically connected to odd-numbered gate drivers among the gate drivers 112, and the first clock signal CK1 may be electrically connected to each of the odd-numbered gate drivers. Is applied. The second clock line CL2 is electrically connected to even-numbered gate drivers among the gate drivers 112 to apply the second clock signal CK2 to each of the even-numbered gate drivers. In this case, the second clock signal CK2 preferably has an inverted waveform with respect to the first clock signal CK1.); and
a third signal line (Fig. 3; CL1-d) extending in a second direction (Fig. 3; CL1-d as third line in second direction intersects CL1, CL2 lines in the first direction), wherein the second direction intersects the first direction (Fig. 3; CL1-d as third line in second direction intersects CL1, CL2 lines in first direction), an end of the first signal line (Fig. 3; CL1) is electrically connected to the third signal line (Fig. 3; CL1-d) (Fig. 3;CL1 is connected to CL1-d), the third signal line (Fig. 3; CL1-d and CL2-d are as third lines) is electrically connected to the dummy gate driving circuit (Fig. 3; CL1-d is connected to Dummy ASG 1 114) and is electrically connected to the starting row gate driving circuit (Fig. 3; dummy driver 114 is electrically connected to the gate drivers).
However, Son does not explicitly disclose the other end of the first signal line is configured to be electrically connected to a driving chip, the driving chip provides a driving signal to the starting row gate driving circuit.
In an analogous art, Shi discloses the other end of the first signal line is configured to be electrically connected to a driving chip, the driving chip provides a driving signal to the starting row gate driving circuit (Shi- [0091]; The present application further provides a display device including a driving chip and any one of the above gate driving circuits or any one of the above display panels. The driving chip and the gate driving circuit are electrically connected. The driving chip is used to provide a plurality of control signals including a clock signal to the gate driving circuit.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the technique of Shi to the system of Son in order to improve the pre-charging effect of the gate driving unit.
Referring to claim 14, Son discloses a display substrate, comprising: the array substrate according to claim 1; and a light-emitting structure layer located on a side of the array substrate away from the substrate,
wherein the display substrate comprises a display region corresponding to the driving region of the array substrate, and the light-emitting structure layer comprises a plurality of sub-pixels located in the display region (Son- highlighted section; A plurality of pixel parts (not shown) are formed in the display area AR1. For example, the pixel units may be arranged in a matrix form. Each of the pixel units may include a thin film transistor and a pixel electrode electrically connected to the thin film transistor. In this case, each of the thin film transistors is electrically connected to a data line (not shown) formed in a first direction and a gate line (not shown) formed in a second direction crossing the first direction. Preferably, the first direction is perpendicular to the second direction.
The first substrate 100 further includes a gate driving circuit 110. The gate driving circuit 110 is formed in the peripheral area AR2 and is formed on at least one side of both sides of the display area AR1 in the second direction. In FIG. 2, for example, the gate driving circuit 110 is formed on the left side of the display area AR1.).
Referring to claim 15, Son discloses wherein the display substrate further comprises a color filter layer located on a side of the light-emitting structure layer away from the substrate, and the light-emitting structure layer comprises liquid crystal molecules (Son- highlighted section; The first substrate 100 includes a plurality of pixel units and signal lines electrically connected to the pixel units. The second substrate is disposed to face the first substrate 100. The second substrate may include color filters and a common electrode formed on an entire surface of the substrate to correspond to the pixel parts. The liquid crystal layer is interposed between the first substrate 100 and the second substrate, the arrangement is changed by an electric field formed between the first substrate 100 and the second substrate.).
Referring to claim 16, Son discloses a display device, comprising the display substrate according to claim 14 (Son- highlighted section; Referring to FIG. 1, the display panel according to the present exemplary embodiment includes a first substrate 100, a second substrate facing the first substrate (not shown), and a liquid crystal layer interposed between the first and second substrates. (Not shown).).
Claim Objections
Claims 2-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Referring to claim 2, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitation “wherein the driving circuit layer further comprises:
a fourth signal line adjacent to the first signal line, the fourth signal line is disposed in a same layer and extends in a same direction as the first signal line, and the fourth signal line is connected to the third signal line; and
a lapping portion overlapped with the first signal line and the fourth signal line, respectively”.
Referring to claims 3-6 are objected upon dependent on the claim 2.
Referring to claim 7, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitation “wherein,
the third signal line comprises a fourth sub-signal line and a fifth sub-signal line located on a side of the fourth sub-signal line away from the first signal line; and
a second gap is provided between the fourth sub-signal line and the fifth sub-signal line, an end portion of the fourth sub-signal line away from the second gap is electrically connected to the first signal line, and an end portion of the fourth sub-signal line adjacent to the second gap is electrically connected to the starting row gate driving circuit”.
Referring to claim 8, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitation “wherein, the driving circuit layer further comprises a first wire, an end of the first wire is connected to the third signal line, and the other end of the first wire is electrically connected to the starting row gate driving circuit; and the array substrate further comprises an insulating layer located between the first wire and the third signal line, the first wire is electrically connected to the third signal line through an opening on the insulating layer, and an orthographic projection of the first wire on the substrate overlaps with an orthographic projection of the third signal line on the substrate”.
Referring to claim 9, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitation “wherein, the driving circuit layer further comprises a first wire, and the first wire comprises a first sub-wire and a second sub-wire;
an end of the first sub-wire is connected to the third signal line, and the other end of the first sub-wire is electrically connected to the starting row gate driving circuit;
the second sub-wire is located on a side of the first sub-wire away from the starting row gate driving circuit; and
a third gap is provided between the first sub-wire and the second sub-wire”.
Referring to claim 10, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitation “wherein,
the driving circuit layer further comprises a first wire and at least one fifth signal line;
an end of the first wire is connected to the third signal line, the other end of the
first wire is electrically connected to the starting row gate driving circuit, and the first wire extends at least partially in the first direction;
the fifth signal line extends in the second direction and is electrically connected to the dummy gate driving circuit; and
the fifth signal line comprises a sixth sub-signal line, a seventh sub-signal line and an eighth sub-signal line disposed in the second direction, a fourth gap is provided between the seventh sub-signal line and the sixth sub-signal line and between the seventh sub-signal line and the eighth sub-signal line, respectively, and orthographic projections of two fourth gaps on the substrate are located on two opposite sides of an orthographic projection of the first wire on the substrate”.
Referring to claim 11, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitation “wherein, the gate driving circuit comprises a start transistor, a pull-down transistor and a connection node, and an output end of the start transistor and an input end of the pull-down transistor are respectively connected to the connection node;
the third signal line is electrically connected to a gate of the start transistor of the starting row gate driving circuit, and a signal transmitted by the second signal line and a signal transmitted by the first signal line transmit are the same;
the driving circuit layer further comprises a plurality of second wires, an end of each of the plurality of second wires is connected to the second signal line, and the other end of each of the plurality of second wires is connected to a gate of the pull-down transistor of the gate driving circuit; and
the second wire corresponding to the starting row gate driving circuit comprises a third sub-wire and a fourth sub-wire, a fifth gap is provided between the third sub-wire and the fourth sub-wire, an end portion of the third sub-wire away from the fifth gap is connected to the gate driving circuit, and an end portion of the fourth sub-wire away from the fifth gap is connected to the gate of the pull-down transistor”.
Referring to claims 12-13 are objected upon dependent on the claim 11.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT D AU whose telephone number is (571)272-5948. The examiner can normally be reached M-F. General 8am-5pm.
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/SCOTT D AU/Examiner, Art Unit 2624
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