DETAILED ACTIONNotice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al (2021/0217341) (herein “Huang”) in view of LIU et al (2019/0333597) (herein “LIU”). In regards to claim 1, Huang teaches a shift register, comprising: an input circuit configured to, under the control of a first clock signal from a first clock terminal, provide a first power supply voltage of a first power supply terminal to a first node (See; Figs. 4 and 5 for input module 10 and pull-down control module 20 connected to CLK and providing VGL to N2) and provide an input signal from an input terminal to a second node (See; Figs. 4 and for input connected to N1); and an output circuit configured to output a signal through an output terminal under the control of a potential of the first node, the potential of the second node (See; Figs. 4 and 5 for output module 30 outputting OUT under control of the potential of N1 and N2). Huang fails to explicitly teach a control circuit configured to: provide a potential of the second node to a third node under the control of a first enable signal from a first enable terminal, and provide the potential of the second node to a fourth node under the control of a second enable signal from a second enable terminal; and an output circuit configured to output a signal through an output terminal under the control of a potential of the first node, the potential of the second node, a potential of the third node, and a potential of the fourth node. However, LIU teaches a shift register, comprising a control circuit configured to: provide a potential of the second node to a third node under the control of a first enable signal from a first enable terminal, and provide the potential of the second node to a fourth node under the control of a second enable signal from a second enable terminal (See; Figs 1-4 for providing a potential of node N1 through a first level control sub-circuit to node OC1 under control of an enable signal and provided to a second node OC2 under control of an enable signal); and an output circuit configured to output a signal through an output terminal under the control of a potential of the third node, and a potential of the fourth node (See; Figs. 1-4 for output sub-circuit 130 outputting output1, output 2 under control of OC1 and OC2). Therefore it would have been obvious to one of ordinary skill in the art at the time of filing to combine HUANG and Liu’s driving circuits into a single driving circuit so as to reduce a bezel width of the display and decrease power consumption of the display device. In regards to claim 23, Huang teaches a driving circuit, comprising M cascaded shift registers of claim 1, where M is a positive integer greater than 1; wherein an input terminal of an mth-stage shift register is electrically connected to an output terminal of an (m-1)th-stage shift register, and 1 < m < M (See; Fig. 7).
Allowable Subject Matter
Claims 2-15, 17, 20, 24 and 25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/JONATHAN A BOYD/Primary Examiner, Art Unit 2627
