DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Status of Claims
The amendment filed on 10/22/2025 has been entered. In the amendment, Applicant amended claims 2, 9, 12-13, 16-17, 19-20, 22-23, 28 and 31, cancelled claims 3, 14-15, 18, 21, 24-27 and 29-30. Currently claims 1-2, 4-13, 16-17, 19-20, 22-23, 28 and 31 are pending.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 12 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the elements “the first level”, “the second level”, “the third level” and “the fourth level”. There are insufficient antecedent bases for these elements in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, 9 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yao et al. (US 2022/0068212).
Regarding claim 1, Yao teaches a shift register (Fig. 1A: scan driving shift register unit 104; Fig. 1C: circuit structure diagram of light-emitting control shift register unit), characterized by comprising a first clock signal line (Figs. 1C-1D and [0061]: “a first clock signal line“ is interpreted as a clock signal line connected to first clock signal terminal CK of first transistor T1), a second clock signal line (Figs. 1C-1D and [0061]: “a second clock signal line“ is interpreted as a clock signal line connected to first clock signal terminal CK of third transistor T3), a third clock signal line (Figs. 1C-1D and [0061]: “a third clock signal line“ is interpreted as a clock signal line connected to second clock signal terminal CB of fourth transistor T4), a fourth clock signal line (Figs. 1C-1D and [0061]: “a fourth clock signal line“ is interpreted as a clock signal line connected to second clock signal terminal CB of fourth transistor T3), an input sub-circuit (Fig. 1C: T1-T3), a first control sub-circuit (Fig. 1C: T4-T5), a second control sub-circuit (Fig. 1C: T6-T8 and C1), and an output sub-circuit (Fig. 1C: T9-T10 and C3); wherein
the input sub-circuit is configured to control potentials of a first node (Fig. 1C: node N1) and a second node (Fig. 1C: node N2) in response to a first clock signal (Fig. 1C: clock signal provided to gate/CK terminal of T1) provided via the first clock signal line and a second clock signal (Fig. 1C: clock signal provided to gate/CK terminal of T3) provided via the second clock signal line;
the first control sub-circuit is configured to control the potential of the first node in response to a signal of the second node (Fig. 1C: signal at node N2) and a third clock signal (Fig. 1C: clock signal provided CB/gate terminal of T4) provided via the third clock signal line;
the second control sub-circuit is configured to control a potential of a third node (Fig. 1C: node N4) in response to a signal of the first node (Fig. 1C: when potential of N1 is low), the signal of the second node, and a fourth clock signal (Fig. 1C: clock signal provided by gate/CB terminal of T7) provided via the fourth clock signal line; and
the output sub-circuit is configured to output a first output signal (Fig. 1C: potential of VGL) in response to the signal of the first node, or output a second output signal (Fig. 1C: potential of VGH) in response to the signal of the third node.
Regarding claim 4, Yao further teaches the shift register according to claim 1, wherein the first clock signal has the same timing as the second clock signal (Fig. 1D); the third clock signal has an opposite timing to the first clock signal (Fig. 1D); and the fourth clock signal has the same timing as the third clock signal (Fig. 1D).
Regarding claim 9, Yao further teaches the shift register according to claim 1, wherein the shift register further comprises a first power signal line (Fig. 1C: power line providing voltage VGL to T3), a second power signal line (Fig. 1C: power line providing voltage VGL to T10), a third power signal line (Fig. 1C: power line providing voltage VGH to T5 and T9), and a fourth power signal line (Fig. 1C: power line providing voltage VGH to T8); wherein
the input sub-circuit is electrically connected to the first power signal line (Fig. 1C: VGL provided to T3), the first control sub-circuit is electrically connected to the third power signal line or the fourth power signal line (Fig. 1C: VGH provided to T5), the second control sub-circuit is electrically connected to the fourth power signal line (Fig. 1C: VGH provided to T8), and the output sub-circuit is electrically connected to the second power signal line and the third power signal line (Fig. 1C: VGH and VGL provided to T10).
Regarding claim 13, Yao further teaches the shift register according to claim 1, wherein the input sub-circuit comprises a first transistor (Fig. 1C: T1), a second transistor (Fig. 1C: T2) and a third transistor (Fig. 1C: T3);
the first transistor has a first electrode (Fig. 1C: left terminal of T1) electrically connected to a signal input (Fig. 1C: input terminal EI), a second electrode (Fig. 1C: right terminal of T1) electrically connected to the first node, and a control electrode (Fig. 1C: gate terminal of T1) electrically connected to the first clock signal line;
the second transistor has a first electrode (Fig. 1C: bottom terminal of T2) electrically connected to the second clock signal line (Fig. 1C: CK signal line), a second electrode (Fig. 1C: top terminal of T2) electrically connected to the second node, and a control electrode (Fig. 1C: gate of T2) electrically connected to the first node; and
the third transistor has a first electrode (Fig. 1C: left terminal of T3) electrically connected to a first power signal line (Fig. 1C: VCL power signal line connected to T3), a second electrode (Fig. 1C: right terminal of T3) electrically connected to the second node, and a control electrode (Fig. 1C: gate of T3) electrically connected to the second clock signal line, or
the input sub-circuit comprises a first transistor (Fig. 1C: T1), a second transistor (Fig. 1C: T2) and a third transistor (Fig. 1C: T3);
the first transistor has a first electrode (Fig. 1C: left terminal of T1) electrically connected to a signal input (Fig. 1C: input terminal EI), a second electrode (Fig. 1C: right terminal of T1) electrically connected to the first node, and a control electrode (Fig. 1C: gate terminal of T1) electrically connected to the first clock signal line;
the second transistor has a first electrode (Fig. 1C: bottom terminal of T2) electrically connected to the first clock signal line (Fig. 1C: CK signal line), a second electrode (Fig. 1C: top terminal of T2) electrically connected to the second node, and a control electrode (Fig. 1C: gate of T2) electrically connected to the first node; and
the third transistor has a first electrode (Fig. 1C: left terminal of T3) electrically connected to a first power signal line (Fig. 1C: VCL power signal line connected to T3), a second electrode (Fig. 1C: right terminal of T3) electrically connected to the second node, and a control electrode (Fig. 1C: gate of T3) electrically connected to the second clock signal line, or
the input sub-circuit comprises a first transistor (Fig. 1C: T1), a second transistor (Fig. 1C: T2) and a third transistor (Fig. 1C: T3);
the first transistor has a first electrode (Fig. 1C: left terminal of T1) electrically connected to a signal input (Fig. 1C: input terminal EI), a second electrode (Fig. 1C: right terminal of T1) electrically connected to the first node, and a control electrode (Fig. 1C: gate terminal of T1) electrically connected to the first clock signal line;
the second transistor has a first electrode (Fig. 1C: bottom terminal of T2) electrically connected to the first clock signal line (Fig. 1C: CK signal line), a second electrode (Fig. 1C: top terminal of T2) electrically connected to the second node, and a control electrode (Fig. 1C: gate of T2) electrically connected to the first node; and
the third transistor has a first electrode (Fig. 1C: left terminal of T3) electrically connected to a first power signal line (Fig. 1C: VCL power signal line connected to T3), a second electrode (Fig. 1C: right terminal of T3) electrically connected to the second node, and a control electrode (Fig. 1C: gate of T3) electrically connected to the second clock signal line.
Claims 28 and 31 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lu et al. (WO 2022183489 A1, to which US 20230162685 is equivalent; the latter being used for this examination).
Regarding claim 28, Lu teaches a gate driver circuit (Fig. 8: block diagram of gate driving circuit 20; Fig. 9: gate driving circuit 20), comprising N cascaded shift registers (Fig. 8: plurality of cascaded shift register unit, e.g., A1, A2, A3, etc.); wherein except for a first stage shift register (Fig. 8: shift register unit A1), a signal input of an (i+1)th stage shift register is electrically connected to a signal output of an ith stage shift register (Fig. 8: input terminal INN of a shift register unit of a (N+1)-th stage is connected to first node N1 of the shift register unit of the N-th stage), where n is a positive integer greater than 1, and i is a positive integer less than or equal to N,
wherein a first clock signal line (Fig. 8: CLK1 signal line) in the ith stage shift register is multiplexed as a fourth clock signal line (Fig. 8: CLK4 signal line) in the (i+1)th stage shift register, a second clock signal line (Fig. 8: CLK2 signal line) in the ith stage shift register is multiplexed as a first clock signal line (Fig. 8: CLK1 signal line) in the (i+1)th stage shift register, a third clock signal line (Fig. 8: CLK3 signal line) in the ith stage shift register is multiplexed as a second clock signal line (Fig. 8: CLK2 signal line) in the (i+1)th stage shift register, and a fourth clock signal line (Fig. 8: CLK4 signal line) in the ith stage shift register is multiplexed as a third clock signal line (Fig. 8: CLK3 signal line) in the (i+1)th stage shift register
Regarding claim 31, Lu further teaches a display apparatus (Fig. 9: display device 30), comprising a pixel driver circuit (Fig. 9: pixel driver circuit for driving pixels P) and a gate driver circuit according to claim 28, wherein the gate driver circuit is electrically connected to the pixel driver circuit to provide a gate control signal ( Fig. 9 gate control signals provided via gate lines GL) for the pixel driver circuit.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16-17, 19-20 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Yao et al. (US 2022/0068212) in view of Wei et al. (CN 113421604 A).
Regarding claim 16, Yao further teaches the shift register according to claim 1, wherein the shift register further comprises an isolation sub-circuit (Fig. 1C: T11 and T12);
isolate the first node from the output sub-circuit electrically connected to the first node ([0088]: “because the second power line VGL always provides a low level, the eleventh transistor T11 and the twelfth transistor T12 are always turned on, thereby avoiding the second clock signal provided by the second clock signal terminal CB connected to the sixth transistor T6 and the output signal of the output terminal EOUT connected to the tenth transistor from affecting the levels of the second node N2 and the first node N1, respectively, thereby ensuring the stability of the circuit”); and isolate the second node from the second control sub-circuit electrically connected to the second node ([0088]: “because the second power line VGL always provides a low level, the eleventh transistor T11 and the twelfth transistor T12 are always turned on, thereby avoiding the second clock signal provided by the second clock signal terminal CB connected to the sixth transistor T6 and the output signal of the output terminal EOUT connected to the tenth transistor from affecting the levels of the second node N2 and the first node N1, respectively, thereby ensuring the stability of the circuit”); and
(Fig. 1C: node, not labelled, between right terminal of T11 and gate of T6).
Yao does not further teach:
the isolation sub-circuit is configured to isolate the first node from the first control sub-circuit electrically connected to the first node; and
the first control sub-circuit is electrically connected to a fifth node; the output sub- circuit is electrically connected to the fifth node.
In the same field of endeavor, Wii teaches in fig. 3
an isolation sub-circuit (Fig. 3: first isolation circuitry 15) is configured to isolate the first node from the first control sub-circuit electrically connected to the first node (Fig. 3: isolation circuitry 15 includes always turned-on first isolation transistor T12, which isolates node N4, which is equivalent to first node in this instant claim, from first control sub-circuit 12); and
the first control sub-circuit is electrically connected to a fifth node (Fig. 3: node N1); the output sub- circuit is electrically connected to the fifth node (Fig. 3).
Before the effective filing date of the invention, it would have been obvious for one ordinary skill in the art to combine Wii’s technique with Yao’s technique by substituting Wei’s first control sub-circuit 12 and isolation transistor T12 for Yao’s first control sub-circuit (i.e., T4 and T in Fig. 1C) and isolation transistor T12 to further improve the performance reliability of the shift register.
Regarding claim 17, Yao in view of Wi further teaches the shift register according to claim 16, wherein the isolation sub-circuit comprises an eleventh transistor (Yao: T11) and a twelfth transistor (Wei: T12);
the eleventh transistor has a first electrode (Yao: Fig. 1C, left terminal of T11) electrically connected to the second node, a second electrode (Yao: Fig. 1C, right terminal of T11) electrically connected to the fourth node, and a control electrode (Yao: Fig. 1C, gate of terminal of T11) electrically connected to a first power signal line (Yao: Fig. 1C, VGL power signal line); and
the twelfth transistor has a first electrode (Wei: Fig. 3, left electrode of T12) electrically connected to the first node, a second electrode (Wei: Fig. 3, right electrode of T12) electrically connected to the fifth node, and a control electrode (Wei: Fig. 3, gate of T12) electrically connected to a second power signal line (Fig. 6: VGL power signal line) or
the isolation sub-circuit comprises an eleventh transistor (Yao: T11) and a twelfth transistor (Wei: T12);
the eleventh transistor has a first electrode (Fig. 1C of Yao and Fig. 3 of Wei: left terminal of T11) electrically connected to the second node, a second electrode (Fig. 1C of Yao and Fig. 3 of Wei: right terminal of T11) electrically connected to the fourth node, and a control electrode (Fig. 1C of Yao and Fig. 3 of Wei: gate of terminal of T11) electrically connected to a first power signal line (Fig. 1C of Yao and Fig. 3 of Wei: VGL power signal line); and
the twelfth transistor has a first electrode (Wei: Fig. 3, left electrode of T12) electrically connected to the first node, a second electrode (Wei: Fig. 3, right electrode of T12) electrically connected to the fifth node, and a control electrode (Wei: Fig. 3, gate of T12) electrically connected to a first power signal line (Wei: Fig. 3: VGL power signal line).
Regarding claim 19, Wei further teaches the shift register according to claim 16, wherein the first control sub-circuit comprises a fourth transistor (Fig. 3: T4), a fifth transistor (Fig. 3: T5), and a third capacitor (Fig. 3: C1);
the fourth transistor has a first electrode (Fig. 3: lower electrode of T4) electrically connected to the third clock signal line (Fig. 3: CB clock signal line), a second electrode (Fig. 3: upper electrode of T4) electrically connected to a second electrode (Fig. 3: lower electrode of T5) of the fifth transistor, and a control electrode (Fig. 3: gate electrode of T5) electrically connected to the fifth node; and
the fifth transistor has a first electrode (Fig. 3: upper electrode of T5) electrically connected to a third power signal line (Fig. 3: VGH power signal line) or a fourth power signal line, the second electrode electrically connected to a first plate (Fig. 3: upper electrode of C1) of the third capacitor, and a control electrode (Fig. 3: gate of T5) electrically connected to the second node; and
the third capacitor has a second plate electrically connected to the fifth node (Fig. 3: lower electrode of C1 connected to node N1).
Regarding claim 20, Yao further teaches the shift register according to claim 16, wherein the second control sub-circuit comprises a sixth transistor (Fig. 1C: T6), a seventh transistor (Fig. 1C: T7), an eighth transistor (Fig. 1C: T8), and a first capacitor (Fig. 1C: C1);
the sixth transistor has a first electrode (Fig. 1C: upper electrode of T6) electrically connected to the fourth clock signal line, a second electrode (Fig. 1C: lower electrode of T6) electrically connected to a first electrode (Fig. 1C: left electrode of T6) of the seventh transistor, and a control electrode (Fig. 1C: gate electrode of T6) electrically connected to the fourth node and a first plate (Fig. 1C: left electrode of C1) of the first capacitor;
the seventh transistor has the first electrode electrically connected to a second plate (Fig. 1C: right plate of C1) of the first capacitor, a second electrode (Fig. 1C: right electrode of T7) electrically connected to the third node, and a control electrode (Fig. 1C: gate of T7) electrically connected to the fourth clock signal line; and
the eighth transistor has a first electrode (Fig. 1C: lower electrode of T8) electrically connected to a fourth power signal line (Fig. 1C: VGH power signa line), a second electrode (Fig. 1C: upper electrode of T8) electrically connected to the third node, and a control electrode (Fig. 1C: gate electrode of T8) electrically connected to the first node,
Regarding claim 22, Yao further teaches the shift register according to claim 16, wherein
the output sub-circuit comprises a ninth transistor (Fig. 1C: T9), a tenth transistor (Fig. 1C: T10), and a second capacitor (Fig. 1C: C3);
the ninth transistor has a first electrode (Fig. 1C: upper electrode T9 Fig. 1C: lower electrode T9) electrically connected to a third power signal line (Fig. 1C: VGH power signal line) and a first plate (Fig. 1C: upper plate of C3) of the second capacitor, a second electrode (Fig. 1C: lower electrode T9) electrically connected to a signal output (Fig. 1C: output terminal EOUT), and a control electrode (Fig. 1C: gate of T9) electrically connected to the third node;
the tenth transistor has a first electrode (Fig. 1C: lower electrode of T10) electrically connected to a second power signal line (Fig. 1C: VGL power signal line), a second electrode (Fig. 1C: upper electrode of T10) electrically connected to the signal output, and a control electrode (Fig. 1C: gate of T10) electrically connected to the fifth node; and
the second capacitor has a second plate (Fig. 1C: lower electrode of C3) electrically connected to the third node.
Allowable Subject Matter
Claims 2, 5-8, 10-11 and 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 2: the claimed timing difference between the “first clock signal” and the “second clock signal”, “the claim timing difference between the “second clock signal” and the “third clock signal”/“fourth clock signal” and the claimed timing difference between the “third clock signal” and the “fourth clock signal” are not taught by Yao (Note in Fig. 1D of Yao’s disclosure, the “first clock signal” and the “second clock signal” have the same timing and the “third clock signal” and the “fourth clock signal” have the same timing) and it is rendered not obvious to further modify the technique of Yao to derive the instant invention.
Claim 5: neither the feature “the first level of the first clock signal has a different potential from the first level of the second clock signal” nor the feature “the third level of the third clock signal has a different potential from the third level of the fourth clock signal” is taught by Yao (Note that in Fig. 1D of Yao’s disclosure, the “first clock signal” and the “second clock signal” have the same potential level and the “third clock signal” and the “fourth clock signal” have the same potential level) and it is rendered not obvious to further modify the technique of Yao to derive the instant invention.
Claim 10: the claimed potential level difference between the “first power signal” and the “second power signal” and the claimed potential level difference between the “third power signal” and the “fourth power signal” are not taught by Yao (Note in Fig. 1D of Yao’s disclosure, the “first power signal” and the “second power signal” have the same potential level and the “third power signal” and the “fourth power signal” have the same potential level) and it is rendered not obvious to further modify the technique of Yao to derive the instant invention.
Claim 23: inclusion of the claimed fourteenth transistor in the input sub-circuit for the recited structural relationship with other elements in the instant claim and inclusion of the claimed fifteenth transistor and sixteenth transistor in the first control sub-circuit for the recited structural relationships with other elements in the instant claim are not taught by Yao and it is rendered not obvious to further modify the technique of Yao to derive the instant invention.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
WO 2022/089067 A1 (US 2023/0093654 as English equivlaent) by Li et al. teaches claim 1 in Fig. 6A, but does not teach claim 2 (Note in Fig. 6B, clock signal CK2 and clock signal CK3/CK4 are of opposite polarities).
US 2021/0366354 by Li et al. teaches claim 1 in Figs. 2 and 4.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XUEMEI ZHENG whose telephone number is (571)272-1434. The examiner can normally be reached Monday-Friday: 9:30 pm-6:00 pm.
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/XUEMEI ZHENG/Primary Examiner, Art Unit 2629
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