DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The amendment filed on 10/30/2025 has been entered. In the amendment, Applicant amended claims 7, 14 and 16 and added new claims 17-20. Currently claims 1-20 are pending.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 7 and 13-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Feng et al. (US 2023/0033702).
Regarding claim 1, Feng teaches a shift register (Abstract: “The gate driving circuit (3) comprises multiple stages of cascaded shift registers (31)”; Fig. 6: upper one of two adjacent shift registers), comprising:
an input circuit (Fig. 6: first input circuit 3101), wherein the input circuit is electrically connected to an input terminal (Fig. 6: input signal terminal 1put) and a pull-up node (Fig. 6: pull-up node Q<N), and the input circuit is configured to write a signal (Fig. 6: signal provided by input signal terminal 1put) from the input terminal to the pull-up node;
a first output circuit (Fig. 6: first output circuit formed by M5, M18, M30 and C1), wherein the first output circuit is electrically connected to the pull-up node, a first clock signal terminal (Fig. 6: clock signal terminal CLKE_1) and a first output terminal (Fig. 6: first output signal terminal Oput1<N>), and the first output circuit is configured to write a signal (Fig. 6 signal provided by terminal CLKE_1) of the first clock signal terminal to the first output terminal under control of a signal (Fig. 4: signal at first pull-up node Q<N >) at the pull-up node;
a second output circuit (Fig. 6: second output circuit formed by M6, M19, M31 and C2), wherein the second output circuit is electrically connected to the pull-up node, a second clock signal terminal (Fig. 6: clock signal terminal CLKF_1) and a second output terminal (Fig. 6: second output signal terminal Oput2<N>), and the second output circuit is configured to write a signal (Fig. 6 signal provided by terminal CLKF_1) of the second clock signal terminal to the second output terminal under the control of the signal at the pull-up node.
Regarding claim 7, Feng further teaches the shift register according to claim 1, wherein the shift register further comprises:
a cascade circuit (Fig. 6: cascade circuit formed by M4, M17 and M29), wherein the cascade circuit is electrically connected to a cascade signal terminal (Fig. 6: terminal CLKD_1), the pull-up node and a cascade output terminal (Fig. 6: output terminal CR<N>), and the cascade circuit is configured to write a signal (Fig. 6: signal provided by terminal CLKD_1) from the cascade signal terminal to the cascade output terminal under the control of the signal at the pull-up node.
Regarding claim 13, Feng further teaches the shift register according to claim 1, wherein the shift register further comprises a reset circuit (Fig. 6: fifth reset circuit 3109), the reset circuit is electrically connected to a first pull-down node (Fig. 6: first pull-down node QB_A), a second pull-down node (Fig. 6: second pull-down node QB_B), the first output terminal, the second output terminal and a second voltage terminal (Fig. 6: third voltage signal terminal VGL2), and the reset circuit is configured to write a signal (Fig. 6: signal provided by third voltage signal terminal VGL2) from the second voltage terminal to the first output terminal or the second output terminal under control of a signal (Fig. 6: signal provided by first pull-down node QB_A or second pull-down node QB_B) at the first pull-down node or the second pull-down node.
Regarding claim 14, Feng further teaches a scanning driver circuit (Abstract: “The sub-pixels (2) comprise pixel driving circuits (21). The gate driving circuit (3) comprises multiple stages of cascaded shift registers (31)”; Fig. 1: gate driver circuit 3; Fig. 7: diagram of gate drive circuit), wherein the scanning driver circuit comprises a plurality of shift registers (Abstract: “The gate driving circuit (3) comprises multiple stages of cascaded shift registers (31)””; Fig. 7) according to claim 1, and the plurality of shift registers are cascaded (Fig. 7).
Regarding claim 15, Feng further teaches the scanning driver circuit according to claim 14, wherein the plurality of shift registers comprise a first shift register (Fig. 6: upper shift register) and a second shift register (Fig. 6: lower shift register), the first shift register and the second shift register are cascaded (Fig. 6), a first pull-down node (Fig. 6: first pull-down node QB_A in upper shift register) of the first shift register is electrically connected to a first pull-down node (Fig. 6: first pull-down node QB_A in lower shift register) of the second shift register, and a second pull-down node (Fig. 6: second pull-down node QB_B in upper shift register) of the first shift register is electrically connected to a second pull-down node (Fig. 6: second pull-down node QB_B in lower shift register) of the second shift register; and
the first shift register further comprises a first noise-reduction circuit (Fig. 6: control circuit 3104; [0127]: “The control circuit 3104 is configured to, under control of the voltage of the pull-up node Q, transmit a sixth voltage signal transmitted by the sixth voltage signal terminal VDD_A or a second voltage signal transmitted by the second voltage signal terminal VGL1 to the pull-down node QB_A, so as to control a voltage of the pull-down node QB_A”). the first noise-reduction circuit is electrically connected to the first pull-down node, and the second shift register further comprises a second noise-reduction circuit (Fig. 6: control circuit 3104), the second noise-reduction circuit is electrically connected to the second pull-down node.
Regarding claim 16, Feng further teaches a display panel ([0002]; [0013]: “the display panel includes a plurality of rows of sub-pixels and a pixel circuit for driving the sub-pixels”), wherein the display panel comprises the shift register according to claim 1.
Regarding claim 17, Feng further teaches the display panel 16 wherein the display panel further a plurality of sub-pixel rows ([0013]: “the display panel includes a plurality of rows of sub-pixels and a pixel circuit for driving the sub-pixels”), the plurality of sub-pixel rows include a first sub-pixel row and a second sub-pixel row that are adjacent ([0044]: “Each shift register can be used to drive a pixel circuit of one row of sub-pixels, or pixel circuits of two adjacent rows of sub-pixels”), the first output terminal is electrically connected to the first sub-pixel row (Fig. 4: G1<N> or G2<N> for N-th sub-pixel row; [0013]; [0044]), and the second output terminal is electrically connected to the second sub-pixel row (Fig. 4: G1<N+1> or G2<N+1> for (N+1)-th sub-pixel row; [0013]; [0044]).
Regarding claim 18, Feng further teaches a display panel ([0002]; [0013]; [0044]), wherein the display panel comprises the scanning driver circuit according to claim 14.
Regarding claim 19, Feng further teaches the display panel according to claim 18, wherein the display panel further comprises a plurality of gate lines (Fig. 1: gate lines GL), a plurality of data lines (Fig. 1: data lines DL), and a plurality of sub-pixels (Fig. 1: sub-pixels P);
the display panel comprises an active area (Fig. 1: display region A) and a non-active area (Fig. 1: bezel region B) electrically connected to the active area; and
the plurality of sub-pixels, the plurality of gate lines, and the plurality of data lines are located within the active area (Fig. 1: sub-pixels P, gate lines GL and data lines DL located within display region A), and the scanning driver circuit is located within the non-active area (Fig. 1: gate driver circuit 3 located within bezel region B).
Regarding claim 20, Feng further teaches the display panel according to claim 19, wherein first output terminals and second output terminals of the plurality of shift registers are electrically connected to the plurality of gate lines respectively (Abstract: “The gate driving circuit (3) comprises multiple stages of cascaded shift registers (31)”; Figs. 1, 7).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-6 are rejected under 35 U.S.C. 103 as being unpatentable over Feng et al. (US 2023/0033702) in view of Fang et al. (US 2019/0006018).
Regarding claim 2, Feng does not further teach the according to claim 1, wherein the shift register further comprises:
a first isolation circuit. wherein the first isolation circuit is electrically connected between the pull-up node and the first output circuit, the first isolation circuit is electrically connected to a first isolation control terminal, and the first isolation circuit is configured to disconnect an electrical connection between the pull-up node and the first output circuit under control of a signal from the first isolation control terminal.
However, in the same field of endeavor, Fang teaches in Fig. 3 wherein the shift register further comprises:
a first isolation circuit (Fig. 3: transistors MT13). wherein the first isolation circuit is electrically connected between the pull-up node (Fig. 3: first node N1) and the first output circuit (Fig. 3: transistor MT11, transistor MT12 and output capacitors OC1), the first isolation circuit is electrically connected to a first isolation control terminal (Fig. 3: gate of MT13), and the first isolation circuit is configured to disconnect an electrical connection between the pull-up node and the first output circuit ([0044]: “When the potential of the first node N1 rises to be equal to the active potential supplied by the second reference potential terminal VGH, the third transfer transistors MT13 and MT23 are turned off”) under control of a signal (Fig. 3: signal of VGH) from the first isolation control terminal.
Before the effective filing date of the invention, it would have been obvious for one ordinary skill in the art to modify the technique of Feng with Fang’s technique to add a transistor between the pull-up node and the first output circuit and add a transistor between the pull-up node and the second output circuit to improve performance reliability of Feng’s shift register (Fang: [0044], “This can avoid a potential increase in the leakage current flowing from the first node N1 to the second scan level terminal CNB through the second transistor M2. Further, since the first node N1 is not in conduction with the internal nodes ND1 and ND2, the decrease in the potential of the first node N1 due to the leakage current does not affect the potentials of the internal nodes ND1 and ND2, thereby ensuring that the gate drive signals output from the output terminals OUT1 and OUT2 do not deteriorate. This is especially advantageous in high temperature scenarios where the leakage current significantly increases”).
Regarding claim 3, Fang further teaches the according to claim 2, wherein the shift register further comprises:
a second isolation circuit (Fig. 3: transistor MT23), wherein the second isolation circuit is electrically connected between the pull-up node (Fig. 3: first node N1) and the second output circuit (Fig. 3: MT21, MT22 and output capacitors OC2), the second isolation circuit is electrically connected to a second isolation control terminal (Fig. 3: gate of MT23), and the second isolation circuit is configured to disconnect an electrical connection between the pull-up node and the second output circuit ([0044]: “When the potential of the first node N1 rises to be equal to the active potential supplied by the second reference potential terminal VGH, the third transfer transistors MT13 and MT23 are turned off”) under control of a signal (Fig. 3: signal of VGH) from the second isolation control terminal.
Regarding claim 4, Fang further teaches the according to claim 3, wherein the first isolation control terminal is electrically connected to the second isolation control terminal (Fig. 3: gate of MT13 and gate of MT23 connected to VGH terminal).
Regarding claim 5, Fang further teaches the according to claim 3, wherein the first isolation circuit is configured to disconnect the electrical connection between the pull-up node and the first output circuit when the first output terminal is at a high-level signal ([0044]: “since the first node N1 is not in conduction with the internal nodes ND1 and ND2, the decrease in the potential of the first node N1 due to the leakage current does not affect the potentials of the internal nodes ND1 and ND2, thereby ensuring that the gate drive signals output from the output terminals OUT1 and OUT2 do not deteriorate”); and/or, the second isolation circuit is configured to disconnect the electrical connection between the pull-up node and the second output circuit when the second output terminal is at the high-level signal ([0044]: “since the first node N1 is not in conduction with the internal nodes ND1 and ND2, the decrease in the potential of the first node N1 due to the leakage current does not affect the potentials of the internal nodes ND1 and ND2, thereby ensuring that the gate drive signals output from the output terminals OUT1 and OUT2 do not deteriorate”).
Regarding claim 6, Fang further teaches the according to claim 3, wherein the first isolation circuit comprises a first isolation transistor (Fig. 3: MT13). a first electrode (Fig. 3: left electrode of MT13) of the first isolation transistor is electrically connected to the pull-up node. a second electrode (Fig. 3: right electrode of MT13) of the first isolation transistor is electrically connected to the first output circuit. and a gate (Fig. 3: gate of MT13) of the first isolation transistor is electrically connected to the first isolation control terminal: and/or.
the second isolation circuit comprises a second isolation transistor (Fig. 3: MT23). a first electrode (Fig. 3: left electrode of MT23) of the second isolation transistor is electrically connected to the pull-up node, a second electrode (Fig. 3: right electrode of MT23) of the second isolation transistor is electrically connected to the second output circuit, and a gate (Fig. 3: gate of MT23) of the second isolation transistor is electrically connected to the second isolation control terminal.
Claims 8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Feng et al. (US 2023/0033702) in view of Sun et al. (US 2022/0327987).
Regarding claim 8, Feng does not further teach the shift register according to claim 7, wherein the shift register further comprises:
a third isolation circuit, wherein the third isolation circuit is electrically connected between the pull-up node and the cascade circuit, the third isolation circuit is electrically connected to a third isolation control terminal, and the third isolation circuit is configured to disconnect an electrical 4connection between the pull-up node and the cascade circuit under control of a signal from the third isolation control terminal.
However, in the same field of endeavor, Sun teaches in Fig. 11 wherein the shift register further comprises:
a third isolation circuit (Fig. 11: anticreep circuit 9 including tenth transistor T10), wherein the third isolation circuit is electrically connected between the pull-up node (Fig. 11: node Q) and the cascade circuit (Fig. 11: cascading output circuit 6 including tenth transistor T10), the third isolation circuit is electrically connected to a third isolation control terminal (Fig. 11: gate terminal of tenth transistor T10), and the third isolation circuit is configured to disconnect an electrical 4connection between the pull-up node and the cascade circuit ([0176]) under control of a signal (Fig. 11: signal of VGH2) from the third isolation control terminal.
Before the effective filing date of the invention, it would have been obvious for one ordinary skill in the art to modify the technique of Feng with Sun’s technique to add a transistor between the pull-up node and the cascade circuit to improve performance reliability of Feng’s shift register (Sun: [0176]: “so that the voltage at the first node PU may be effectively prevented from being discharged”).
Regarding claim 10, Sun further teaches the shift register according to claim8, wherein the third isolation circuit comprises a third isolation transistor (Fig. 11: tenth transistor T10), a first electrode (Fig. 11: left terminal of T10) of the third isolation transistor is electrically connected to the pull-up node, a second electrode (Fig. 11: right terminal of T10) of the third isolation transistor is electrically connected to the cascade circuit. and a gate (Fig. 11: gate of T10) of the third isolation transistor is electrically connected to the third isolation control terminal.
Claims 11-12 are a rejected under 35 U.S.C. 103 as being unpatentable over Feng et al. (US 2023/0033702) in view of Liu et al. (CN 113920937 A, to which US 2024/0112623 is equivalent; the latter being used for this examination).
Regarding claim 11, Feng does not further teach the shift register according to claim 1, wherein at least a portion of transistors in the shift register are double gate structures.
The technique of using a double-gate structure in a shift register is not new, however.
Liu, for instance, teaches in Fig. 8 and [0201] an output transistor T9 is a transiter with double gates.
Before the effective filing date of the invention, it would have been obvious to combine Liu’s technique with Fent’s technique forming output transistors in Feng’s first output circuit and second output circuit with double gate structures to prevent and reduce occurrence of a leakage current.
Regarding claim 12, Feng further teaches the shift register according to claim 11, wherein the input circuit comprises a first input transistor (Fig. 6: M1) and a second input transistor (Fig. 6: M2), a first electrode (Fig. 6: upper terminal of M1) of the first input transistor is electrically connected to the input terminal, a second electrode (Fig. 6: lower terminal of M1) of the first input transistor is electrically connected to a first electrode (Fig. 6: upper terminal of M2) of the second input transistor, a second electrode (Fig. 6: lower terminal of M2) of the second input transistor is electrically connected to the pull-up node, and gates of the first input transistor and the second input transistor is electrically connected to the input terminal (Fig. 6: gates of M1 and M2 connected to terminal 1put);
the shift register further comprises a leakage-prevention circuit (Fig. 6: leakage prevention circuit 3102), the leakage-prevention circuit is electrically connected to a first voltage terminal (Fig. 6: first voltage signal terminal VDD), a leakage-prevention control terminal (Fig. 6: gate terminal of M3) and the second electrode of the first input transistor (Fig. 6: right terminal of M3 connected to lower terminal of M1), and the leakage-prevention circuit is configured to write a signal (Fig. 6: ) from the first voltage terminal to the second electrode of the first input transistor under control of a signal (Fig. 6: signal at gate of M3) from the leakage-prevention control terminal.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Feng et al. (US 2023/0033702) in view of Sun et al. (US 2022/0327987), and further in view of Fang et al. (US 2019/0006018).
Regarding claim 9, Feng in view of Sun does not further teach the shift register according to claim 8, wherein the third isolation control terminal is electrically connected to a first isolation control terminal and a second isolation control terminal.
The instant invention is different from Sun’s technique in that in the instant invention the plurality of output circuit (the cascade circuit, the first output circuit and the second output circuit) each has a respect isolation circuit while Sun’s technique has the cascade circuit, the first output circuit and the second output circuit share the same isolation circuit. However, it is not new in the related art configuring each of a plurality of output circuits to have a respective isolation circuit.
Fang, for instance, teaches in Fig. 3 each of output circuits has a respective isolation circuit (i.e., M13 for first output circuit 130 and M23 for second output circuit 140).
Before effective filing date of the invention, it would have been obvious for one ordinary skill in the art to further modify the technique of Feng in view of Sun with Fang’s technique by configuring each of Feng’s cascade circuit, the first output circuit and the second output circuit to have a respective isolation circuit, wherein the gate of each isolation circuit is connected to the VGH terminal.
The modification is an obvious matter of design choice.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2023/0148117 by Feng also teaches independent claim 1 and some other claims in Figs. 1 and 17.
US 2023/0162686 by Feng also teaches independent claim 1 and some other claims in Fig. 3C.
US 2023/0335207 by Feng also teaches independent claim 1 and some other claims in Figs. 5 and 14.
US 2024/0203357 by Feng also teaches independent claim 1 and some other claims in Figs. 1 and 8.
US 2024/0257712 by Feng also teaches independent claim 1 and some other claims in Figs. 2 and 36.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XUEMEI ZHENG whose telephone number is (571)272-1434. The examiner can normally be reached Monday-Friday: 9:30 pm-6:00 pm.
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/XUEMEI ZHENG/Primary Examiner, Art Unit 2629
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