DETAILED ACTION
Claims 1-20 filed October 30th, 2025, are pending in the current action.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 6, 7, 12, 13, 16 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al. (US2021/0358414)
Consider claim 1, where Yang teaches a pixel circuit, comprising a light-emitting element, (See Yang Fig. 7 where there is a micro OLED) a driving circuit, a driving node control circuit and a first write-in circuit; (See Yang Fig. 7 and ¶32 where there is a driving sub-circuit 12, a data write-in sub-circuit 11 and a step-down sub-circuit 15.) wherein a control end of the driving circuit is electrically coupled to a driving node, and the driving circuit is configured to generate a driving current for driving the light-emitting element under the control of a potential at the driving node; (See Yang Fig. 7 and ¶37 where A control end of the driving sub-circuit 12 is connected to the control node NC, and a second end of the driving sub-circuit 12 is connected to a first electrode of the light-emitting element EL. The driving sub-circuit 12 is configured to, at the light-emitting stage, enable the first end of the driving sub-circuit 12 to be electrically connected to the first electrode of the light-emitting element EL under the control of the control node NC, so as to drive the light-emitting element EL to emit light.) the first write-in circuit is electrically coupled to a write-in control line, a first data line and a control node, and configured to write a first data voltage provided by the first data line into the control node under the control of a write-in control signal provided by the write-in control line; (See Yang Fig. 7 and ¶33 where the data write-in sub-circuit 11 is connected to a gate line Gate, a data line Data and a data write-in node ND, and configured to, at a charging compensation stage, write a data voltage across the data line Data into the data write-in node ND under the control of the gate line Gate.) and the driving node control circuit is electrically coupled to the control node, a first voltage end and the driving node, and configured to control the driving node to be electrically coupled to or electrically decoupled from the first voltage end under the control of a potential at the control node. (See Yang Fig. 7 and ¶35 where the step-down sub-circuit 15 is connected to the data write-in node ND, a control node NC and the power source voltage input end, and configured to, at the charging compensation stage, step down the data voltage so as to acquire a first step-down voltage.)
Consider claim 6, where Yang discloses the pixel circuit according to claim 1, wherein the first write-in circuit comprises a first transistor, (See Yang Fig. 7 and ¶73 where the data write-in sub-circuit 11 may include: a first data write-in transistor N1) and the driving node control circuit comprises a second transistor; (See Yang Fig. 7 and ¶77 where The step-down sub-circuit 15 may include a step-down transistor TD) a gate electrode of the first transistor is electrically coupled to the write-in control line, a first electrode of the first transistor is electrically coupled to the first data line, and a second electrode of the first transistor is electrically coupled to the control node; (See Yang Fig. 7 and ¶73 where the data write-in sub-circuit 11 may include: a first data write-in transistor N1, a gate electrode of which is connected to the first gate line Gate1, a drain electrode of which is connected to the data line Data, and a source electrode of which is connected to the data write-in node ND) and a gate electrode of the second transistor is electrically coupled to the control node, a first electrode of the second transistor is electrically coupled to the first voltage end, and a second electrode of the second transistor is electrically coupled to the driving node. (See Yang Fig. 7 and ¶77 where the step-down sub-circuit 15 may include a step-down transistor TD, a gate electrode of which is connected to the data write-in node ND, a source electrode of which is configured to receive the power source voltage Vdd, and a drain electrode of which is connected to the control node NC.)
Consider claim 7, where Yang discloses the pixel circuit according to claim 1 wherein the driving circuit comprises a driving transistor; and a gate electrode of the driving transistor is electrically coupled to the driving node, a first electrode of the driving transistor is electrically coupled to the first node, a second electrode of the driving transistor is electrically coupled to the second node, and a substrate of the driving transistor is electrically coupled to the power source voltage end. (See Yang Fig. 7 and ¶74 where the driving sub-circuit 12 may include a driving transistor DTFT, a gate electrode of which is connected to the control node NC, a drain electrode of which is connected to an anode of the micro-OLED Moled. A cathode of the micro-OLED Moled is configured to receive a low voltage VSS.)
Consider claim 12, where Yang discloses a driving method, applied to the pixel circuit according to claim 1 comprising: writing, by the first write-in circuit, the first data voltage into the control node under the control of the write-in control signal, and controlling, by the driving node control circuit, the driving node to be electrically coupled to or electrically decoupled from the first voltage end under the control of the potential at the control node. (See Yang Fig. 78 and ¶83 where at the charging compensation stage S2, Gate1 and EM may output a high level, and Gate2 and Discharge may output a low level, so as to turn on P1 and N1, and turn off N2 and P2. At this time, Data may output the data voltage Vdata, and Vdata may be written into ND, so TD may operate at the saturation region.)
Consider claim 13, where Yang discloses the driving method according to claim 12, wherein a first end of the driving circuit is electrically coupled to a first node, and a second end of the driving circuit is electrically coupled to a second node; and the driving method comprises: in a case that the driving node control circuit controls the driving node to be electrically coupled to the first voltage end, controlling, by the driving circuit, the first node to be electrically decoupled from the second node under the control of the potential at the driving node. (See Yang Fig. 7 and ¶74 where the driving sub-circuit 12 may include a driving transistor DTFT, a gate electrode of which is connected to the control node NC, a drain electrode of which is connected to an anode of the micro-OLED Moled. A cathode of the micro-OLED Moled is configured to receive a low voltage VSS.)
Consider claim 16, where Yang discloses a display device, comprising a pixel circuit according to claim 1. (See Yang ¶97 and the rejection of claim 1 above)
Consider claim 19, where Yang discloses the pixel circuit according to claim 4, wherein the first write-in circuit comprises a first transistor, (See Yang Fig. 7 and ¶73 where the data write-in sub-circuit 11 may include: a first data write-in transistor N1) and the driving node control circuit comprises a second transistor; (See Yang Fig. 7 and ¶77 where The step-down sub-circuit 15 may include a step-down transistor TD) a gate electrode of the first transistor is electrically coupled to the write-in control line, a first electrode of the first transistor is electrically coupled to the first data line, and a second electrode of the first transistor is electrically coupled to the control node; (See Yang Fig. 7 and ¶73 where the data write-in sub-circuit 11 may include: a first data write-in transistor N1, a gate electrode of which is connected to the first gate line Gate1, a drain electrode of which is connected to the data line Data, and a source electrode of which is connected to the data write-in node ND) and a gate electrode of the second transistor is electrically coupled to the control node, a first electrode of the second transistor is electrically coupled to the first voltage end, and a second electrode of the second transistor is electrically coupled to the driving node. (See Yang Fig. 7 and ¶77 where the step-down sub-circuit 15 may include a step-down transistor TD, a gate electrode of which is connected to the data write-in node ND, a source electrode of which is configured to receive the power source voltage Vdd, and a drain electrode of which is connected to the control node NC.)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability should not be negated by the manner in which the invention was made.
Claim(s) 4 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang as applied to claim 1 above, in further view of Lo (US2018/0197469)
Consider claim 4, where Yang discloses the pixel circuit according to claim 1, where Yang does not explicitly teach further comprising a first initialization circuit (M1); wherein the first initialization circuit is electrically coupled to an initial control end, an initial voltage end and the driving node, and configured to write an initial voltage provided by the initial voltage end into the driving node under the control of an initial control signal provided by the initial control end. However, in an analogous field of endeavor Lo teaches further comprising a first initialization circuit (M1); wherein the first initialization circuit is electrically coupled to an initial control end, an initial voltage end and the driving node, and configured to write an initial voltage provided by the initial voltage end into the driving node under the control of an initial control signal provided by the initial control end. (See Lo Figs. 2, 3, and ¶15-20 where the control terminal of the first switch T1 is controlled by a control signal G1… During the initialization period P1, the first switch T1 and the second switch T2 are turned on, and the third switch T3 is turned off. Hence, the charges of the capacitor C1 may be removed/reset during the initialization period P1. Besides, the voltage Vg at the control terminal of the transistor T4 is pulled down to the initialization voltage Vini, and the voltage at the first terminal of the light-emitting element E1 is pulled down to VEE) Therefore, it would have been obvious for one of ordinary skill in the art to modify the pixel circuit of Yang by initializing the pixel circuit prior to the data write-in period as taught by Lo. One of ordinary skill in the art would have been motivated to perform the modification for the advantage of/ benefit of resetting the driving voltage of the driving transistor by turning off the driving transistor. (See Lo ¶20)
Consider claim 10, where Yang in view of Lo teaches the pixel circuit according to claim 4, wherein the first initialization circuit comprises a seventh transistor; (See Yang Fig. 2 and ¶19 where there is the first switch T1 ) and a gate electrode of the seventh transistor is electrically coupled to the initial control end, (See Yang ¶19 where the control terminal of the first switch T1 is controlled by a control signal G1) a first electrode of the seventh transistor is electrically coupled to the initial voltage end, (See Yang ¶17 where A first terminal of the first switch T1 is coupled to a first voltage line INI1 of the display panel 120.) and a second electrode of the seventh transistor is electrically coupled to the driving node. (See Yang Fig. 2 where the other end of T2 is coupled to the gate of the driving transistor T4)
Allowable Subject Matter
Claims 2, 3, 5, 8, 9, 11, 14, 15, 17, 18, and 20 are allowed.
The following is an examiner’s statement of reasons for allowance: Claim 2 recites: “The pixel circuit according to claim 1, further comprising an energy storage circuit, a second write-in circuit and a compensation control circuit; wherein the energy storage circuit is electrically coupled to the driving node, and configured to store electric energy; a first end of the driving circuit is electrically coupled to a first node, and a second end of the driving circuit is electrically coupled to a second node; the second write-in circuit is electrically coupled to a scanning line, a second data line and the first node, and configured to control the second data line to write a second data voltage into the first node under the control of a scanning signal provided by the scanning line; and the compensation control circuit is electrically coupled to the scanning line, the driving node and the second node, and configured to control the driving node to be electrically coupled to or electrically decoupled from the second node under the control of the scanning signal.” The Examiner was able to find the individual elements of the circuit in Zhang et al (US2022/0190100), however the modification of Yang with Zhang would fundamentally alter the operations of each reference beyond their original intents. Thus, the combination would be non-obvious.
Claims 3, 5, 8, 9, 11, 17, 18, and 20 are allowed based upon their dependence from claim 2.
Claim 14 recites the method being performed by the circuit in claim 2 and is allowed for similar reasons. Claim 15 is allowed based upon its dependence from claim 14.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM LU whose telephone number is (571)270-1809. The examiner can normally be reached 10am-6:30pm.
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WILLIAM LU
Primary Examiner
Art Unit 2624
/WILLIAM LU/Primary Examiner, Art Unit 2624
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