DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 16, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by [Watakabe; Hajime et al., US 20230169922 A1].
Regarding claim 1:
Watakabe discloses:
1. (Original) A pixel driving circuit [Watakabe: Fig.10: pixel 103B; ¶ 0094: “FIG. 10 is an equivalent circuit diagram of the pixel 103B”], provided in a display panel [Watakabe: Fig. 1: display device 100; Fig.11; ¶ 0095: “FIG. 11 is a diagram illustrating a cross-sectional structure of the pixel 103B of the display device 100”] to drive a light-emitting element (OLED) [Watakabe: Fig.10: light-emitting element OLED; ¶ 0044: “The driving transistor DRT functions as a current control element that controls a current flowing through the light-emitting element OLED according to a gate-source voltage”; ¶ 0094: “The equivalent circuit diagram shown in FIG. 10 is different from the equivalent circuit diagram shown in FIG. 2 in the structure of the driving transistor DRT”; Examiner: Preamble treated as non-limiting intended use; mapping supplied for completeness. Furthermore, ¶ 0094 states the Fig.10 circuit differs from the Fig.2 circuit only in the structure of the driving transistor DRT.], the pixel driving circuit [Watakabe: Fig.10: pixel 103B; ¶ 0094: “FIG. 10 is an equivalent circuit diagram of the pixel 103B”] comprising a driving transistor (T3) [Watakabe: Fig.11: transistor 210A; ¶ 0095: “ the transistor 210A corresponds to the driving transistor DRT shown in FIG. 10”] for generating a driving current [Watakabe: ¶ 0046: “The driving transistor DRT outputs a driving current with a current amount corresponding to the video signal Vsig to the light-emitting element OLED”],
wherein a channel region [Watakabe: Fig.11: channel area 208a; ¶ 0096: “the oxide semiconductor layer 208_1 includes the channel area 208a”] of the driving transistor (T3) [Watakabe: Fig.11: transistor 210A; ¶ 0095: “ the transistor 210A corresponds to the driving transistor DRT shown in FIG. 10”] is made of a metal oxide semiconductor material [Watakabe: ¶ 0047: “the oxide semiconductor layer is used as the semiconductor layer of the transistor constituting the display device 100 will be described”; ¶ 0072: “examples include a compound (IGZO) containing indium, gallium, and zinc”; Examiner: IGZO is a metal oxide semiconductor material.], and the driving transistor (T3) [Watakabe: Fig.11: transistor 210A; ¶ 0095: “ the transistor 210A corresponds to the driving transistor DRT shown in FIG. 10”] has only one of a top gate and a bottom gate [Watakabe: Fig.11: conductive layer 204_1; ¶ 0096: “The transistor 210A functioning as the driving transistor DRT has a bottom gate structure”; ¶ 0098: “ a transistor with a bottom gate structure is arranged as the driving transistor DRT on the same substrate”; Examiner: Conductive layer 204_1 lies between the channel area 208a and the substrate 101 is therefore a bottom gate. No gate electrode is recited above the oxide semiconductor layer 208_1 so no top gate is present and the driving transistor has exactly one gate.].
Regarding claim 3:
Watakabe discloses:
3. (Original) The pixel driving circuit [Watakabe: Figs.10 and 11: pixel 103B; ¶ 0094: “FIG. 10 is an equivalent circuit diagram of the pixel 103B”] according to claim 1, further comprising at least one switching transistor [Watakabe: Fig.11: transistor 250; ¶ 0095: “the transistor 250 corresponds to the writing transistor SST shown in FIG. 10”; ¶ 0044: “The writing transistor SST functions as a switching element that selects conduction or non-conduction between...”] ,
wherein a channel region [Watakabe: Fig.11: channel area 208i; ¶ 0091: “The oxide semiconductor layer 208 includes a channel area 208i”] of a switching transistor [Watakabe: Fig.11: transistor 250; ¶ 0095: “the transistor 250 corresponds to the writing transistor SST shown in FIG. 10”; ¶ 0044: “The writing transistor SST functions as a switching element that selects conduction or non-conduction between...”] is made of a metal oxide semiconductor material [Watakabe: Fig.11: oxide semiconductor layer 208_3; ¶ 0091: “The transistor 250 has at least an oxide semiconductor layer 208_3 arranged on the insulating film 206”; ¶ 0047: “the oxide semiconductor layer is used as the semiconductor layer of the transistor constituting the display device 100 will be described”; ¶ 0073: “Specifically, the oxide semiconductor layers 208_1 and 208_2 may be made of InO.sub.x, ZnO.sub.x, SnO.sub.x, In—Ga—O, In—Zn—O, In—Al—O, In—Sn—O, In—Hf—O, In—Zr—O, In—W—O, In—Y—O, In-Ga—Zn-O, In—Al—Zn—O, In—Sn—Zn—O, In—Hf—Zn—O, In—Ga—Sn—O, In—Al—Sn—O, In—Hf—Sn—O, In—Ga—Al—Zn—O, In—Ga—Hf—Zn—O, In-Sn-Ga—Zn-O or the like”].
Regarding claim 16:
Watakabe discloses:
16. (Currently Amended) A display panel [Watakabe: Fig.1: display device 100 having a display area 102 and a peripheral area 109 arranged on a substrate 101; ¶ 0039: “The display area 102 includes a plurality of pixels 103 arranged in a matrix. Each of the plurality of pixels 103 includes a plurality of transistors and light-emitting elements”], comprising the pixel driving circuit [Watakabe: Fig.10: pixel 103B; ¶ 0094: “FIG. 10 is an equivalent circuit diagram of the pixel 103B”] according to claim 1 [Examiner: See the rejection of claim 1 above.].
Regarding claim 20:
Watakabe discloses:
20. (New) The display panel according to claim 16, further comprising a light-emitting element [Watakabe: Fig.10: light-emitting element OLED] electrically connected to the pixel driving circuit [Watakabe: Fig.10: pixel 103B; ¶ 0094: “FIG. 10 is an equivalent circuit diagram of the pixel 103B”; ¶ 0044: “The driving transistor DRT is connected in series with the light-emitting element OLED between the high potential power source SLa and the low potential power source electrode SLb”; ¶ 0061: “The transistor 210 is connected to the light-emitting element 230”].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over [Watakabe; Hajime et al., US 20230169922 A1].
Regarding claim 4:
Watakabe discloses:
4. (Original) The pixel driving circuit [Watakabe: Fig.10: pixel 103B; ¶ 0094: “FIG. 10 is an equivalent circuit diagram of the pixel 103B”] according to claim 3,
wherein the switching transistor [Watakabe: Fig.11: transistor 250; ¶ 0094: “The transistor 250 functioning as the writing transistor SST has a top gate structure”] has a top gate [Watakabe: Fig.11: conductive layer 214].
However, the Fig.11 embodiment of Watakabe does not expressly disclose:
and a bottom gate.
The Fig.3 embodiment of Watakabe discloses:
wherein the switching transistor [Watakabe: Fig.3: transistor 220; ¶ 0053: “the transistor 220 corresponds to the writing transistor SST”] has a top gate [Watakabe: Fig.3: conductive layer 214_2; ¶ 0055: “The transistor 220 functioning as the writing transistor SST is a dual gate structure. The transistor 220 includes at least a conductive layer 204_2, the insulating film 206 arranged on the conductive layer 204_2, an oxide semiconductor layer 208_2 arranged on the insulating film 206, the insulating film 212 arranged on the oxide semiconductor layer 208_2, and a conductive layer 214_2 arranged on the insulating film 212”] and a bottom gate [Watakabe: Fig.3: conductive layer 204_2; ¶ 0055: “The transistor 220 functioning as the writing transistor SST is a dual gate structure. The transistor 220 includes at least a conductive layer 204_2, the insulating film 206 arranged on the conductive layer 204_2, an oxide semiconductor layer 208_2 arranged on the insulating film 206, the insulating film 212 arranged on the oxide semiconductor layer 208_2, and a conductive layer 214_2 arranged on the insulating film 212. In this case, the first control terminal for controlling switching of the transistor 220 is the conductive layer 204_2 and the conductive layer 214_2. Therefore, the transistor 220 is the dual gate drive”].
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to substitute the dual-gate writing transistor 220 of Fig.3 for the top-gate writing transistor 250 of Fig.11, retaining the bottom-gate driving transistor 210. Watakabe contemplates this pairing at ¶ 0113, ¶ 0132 and ¶ 0145, and states at ¶ 0159 that the embodiments “can be combined with each other without causing any technical inconsistency.” The motivation is Watakabe’s own: a dual gate structure raises ON current but degrades driving transistor reliability (¶ 0048), so Watakabe teaches applying it to the writing transistor and not the driving transistor (¶ 0051). The predictable result is faster-switching writing transistor while the driving transistor retains the larger subthreshold swing that permits fine gradation control at low grayscale (¶ 0057).
Claim(s) 5-6 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over [Watakabe; Hajime et al., US 20230169922 A1] in view of [Zhou; Xingyu et al., US 20190172954 A1] and further in view of [Kang; Pengtao, US 20160049453 A1].
Regarding claim 5:
Watakabe discloses:
5. (Original) The pixel driving circuit [Watakabe: Fig.10: pixel 103B; ¶ 0094: “FIG. 10 is an equivalent circuit diagram of the pixel 103B”] according to claim 4,
wherein the display panel [Watakabe: Fig.1: display device 100 having a display area 102 on substrate 101] has
a base substrate (SUB) [Watakabe: Fig.11: substrate 101] ,
an inorganic buffer layer (BUF) [Watakabe: Fig.11: base film 202; ¶ 0070: “Silicon oxide or silicon nitride may be used as the base film 202 in a single layer, or a stacked layer may be used by combining silicon oxide and silicon nitride”; Examiner: Silicon oxide and silicon nitride are inorganic.] ,
a first gate layer (GT1) [Watakabe: Fig.11: conductive layer 204_1; Fig.3: conductive layers 204_1 and 204_2] ,
a first gate insulating layer (GI1) [Watakabe: Fig.11: insulating film 206; ¶ 0054: “The insulating film 206 functions as a gate insulating film of the transistor 210”] ,
a semiconductor layer (SCL2) [Watakabe: Fig.11: oxide semiconductor layers 208_1 and 208_2],
a second gate insulating layer (GI2) [Watakabe: Fig.11: insulating film 212; ¶ 0055: “The insulating film 206 and the insulating film 212 function as the gate insulating films”],
a second gate layer (GT2) [Watakabe: Fig.11: conductive layer 214; Fig.3: conductive layers 214_1 and 214_2] ,
a source-drain metal layer (SD) [Watakabe: Fig.11: source electrode and drain electrode 218_1and 218_2; ¶ 0083: “The source electrodes or drain electrodes 218_1 to 218_4 are formed by forming a conductive film on the insulating film 216...”] that are stacked in sequence [Watakabe: ¶ 0069 to ¶ 0083; Examiner: The recited order of formation is substrate 101, base film 202, conductive layers 204, insulating film 212, conductive layer 214, insulating film 216, source and drain electrodes 218.];
the driving transistor (T3) [Watakabe: Fig.11: transistor 210A; ¶ 0095: “ the transistor 210A corresponds to the driving transistor DRT shown in FIG. 10”] includes the bottom gate located in the first gate layer (GT1) [Watakabe: Fig.11: conductive layer 204_1; Fig.3: conductive layers 204_1 and 204_2; ¶ 0096: “The transistor 210A includes at least the conductive layer 204_1, the insulating film 206 arranged on the conductive layer 204_1, and the oxide semiconductor layer 208_1 arranged on the insulating film 206”] and
an active layer located in the semiconductor layer (SCL) [Watakabe: Fig.11: oxide semiconductor layer 208_1],
and the active layer of the driving transistor (T3) [Watakabe: Fig.11: oxide semiconductor layer 208_1] includes a channel region [Watakabe: Fig.11: channel area 208a; ¶ 0096: “the oxide semiconductor layer 208_1 includes the channel area 208a”],
and a first conductive region [Watakabe: Fig.11: high concentration impurity area 208b] and a second conductive region [Watakabe: Fig.11: high concentration impurity area 208c] located on both sides of the channel region [Watakabe: Fig.11: channel area 208a; ¶ 0096: “the oxide semiconductor layer 208_1 includes the channel area 208a, the high concentration impurity areas 208b and 208c, and low concentration impurity areas 208d and 208e”];
each switching transistor [Watakabe: Fig.3: transistor 220] includes a bottom gate located in the first gate layer (GT1) [Watakabe: Fig.3: conductive layers 204_2; Examiner: Conductive layers 204_1 and 204_2 are formed in the same step per ¶ 0070 and are therefore the same layer.],
an active layer located in the semiconductor layer [Watakabe: Fig.3: oxide semiconductor layer 208_2]
and a top gate located in the second gate layer (GT2) [Watakabe: Fig.3: conductive layer 214_2; ¶ 0055: “a conductive layer 214_2 arranged on the insulating film 212”] ;
and the active layer of the switching transistor [Watakabe: Fig.3: oxide semiconductor layer 208_2] includes a channel region [Watakabe: Fig.3: channel area 208f],
and a first conductive region [Watakabe: Fig.3: high concentration impurity area 208g] and a second conductive region [Watakabe: Fig.3: high concentration impurity area 208h] located on both sides of the channel region [Watakabe: ¶ 0055: “The high concentration impurity areas 208g and 208h are arranged with the channel area 208f interposed therebetween”].
However, Watakabe does not expressly disclose:
a light-shielding metal layer stacked between the base substrate and the inorganic buffer layer;
a planarization layer stacked between the second gate layer and the source-drain metal layer.
Zhou discloses:
a light-shielding metal layer [Zhou: Fig.14: light-shielding layer 20; ¶ 0061: “the light-shielding layer 20 is formed by patterning a metal layer deposited on the base substrate 10”] stacked between the base substrate [Zhou: Fig.14: base substrate 10] and the inorganic buffer layer [Zhou: Fig.14: buffer layer 30; ¶ 0094: “ the buffer layer 30 is a silicon oxide (SiOx) thin film, a silicon nitride (SiNx) thin film, or a composite thin film formed by alternately laminating a silicon oxide thin film and a silicon nitride thin film”; ¶ 0088: “a base substrate 10, a light-shielding layer 20 disposed on the base substrate 10, a buffer layer 30 disposed on the base substrate 10 covering the light-shielding layer 20, an active layer 40 disposed on the buffer layer 30 corresponding to a region above the light-shielding layer 20”].
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to interpose Zhou’s patterned metal light-shielding layer between Watakabe’s substrate and base film. Watakabe’s channels are oxide semiconductor (¶ 0047) and Watakabe recognizes that their back surface must be shielded (¶ 0055), but its conductive layer 204_1 is the driving transistor’s sole gate and switches in operation, and the writing transistor has no layer beneath its channel. Zhou supplies a dedicated shielding layer to “protect the active layer from light irradiation and prevent the TFT from generating a negative threshold voltage drift phenomenon” (¶ 0046) , and one or ordinary skill would have been motivated to add it to shield every channel without containing the gate potentials, predictably suppressing the drift Zhou identifies.
Kang discloses:
a planarization layer [Kang: Fig.2: planarization layer 15, arranged between the gate 14 and the source and drain 17; Fig.3: planarization layer 15 formed after the gates 14 and before the contact vias 16 and the source and drain 17; 0048: “the top-gate type thin film transistor includes the active region 11, the gate insulating layer, the gate 14, a planarization layer 15, a source and a drain 17 which are sequentially provided on a base substrate 10, wherein, the source and the drain 17 are respectively connected to the active region 11 through contact vias 16 which penetrate through the gate insulating layer and the planarization layer 15”] stacked between the gate layer and the source-drain metal layer [Kang: ¶ 0075: “The planarization layer 15 may be made of any one of silicon oxide (SiOx), silicon nitride (SiNx), hafnium oxide (HfOx), silicon oxynitride (SiON), aluminum oxide (AlOx), and an organic material”].
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form the planarization layer of Kang over Watakabe’s second gate layer before the source and drain electrodes. Watakabe forms electrodes 218 directly on insulating film 216, which conforms over the patterned conductive layers 214, whereas Kang places a planarization layer 15 at that same position with contract routed through vias 16 (¶ 0048). One of ordinary skill would have been motivated to planarize before patterning the electrodes, Watakabe itself recognizing that a film formed over a steep end portion suffers a coverage defect (¶ 0063), and Watakabe’s existing via scheme accommodates the added layer without change (¶ 0083). Kang is analogous art, an OLED array substrate.
Regarding claim 6:
Watakabe in view of Zhou and further in view of Kang discloses:
6. (Currently Amended) The pixel driving circuit [Watakabe: Fig.10: pixel 103B; ¶ 0094: “FIG. 10 is an equivalent circuit diagram of the pixel 103B”] according to claim 5,
wherein the at least one switching transistor [Watakabe: Fig.11: transistor 250; ¶ 0095: “the transistor 250 corresponds to the writing transistor SST shown in FIG. 10”; ¶ 0044: “The writing transistor SST functions as a switching element that selects conduction or non-conduction between...”] includes a first light-emitting control transistor (T5) [Watakabe: Fig.16: output transistor BCT of the pixel 103E; ¶ 0116: “The output transistor BCT controls the signal BG to control the light emission duration of the light-emitting element OLED”];
the first light-emitting control transistor (T5) [Watakabe: Fig.16: output transistor BCT of the pixel 103E] includes a bottom gate located in the first gate layer (GT1) [Watakabe: Fig.3: conductive layer 204_2 of transistor 220; ¶ 0113: “the output transistor BCT, and the reset transistor RST may have the structure of the transistor 220 or the transistor 250 described in the second embodiment”],
an active layer located in the semiconductor layer (SCL) [Watakabe: Fig.3: oxide semiconductor layer 208_2 of transistor 220],
and a top gate located in the second gate layer (GT2) [Watakabe: Fig.3: conductive layer 214_2 of transistor 220] ;
the top gate and bottom gate of the first light-emitting control transistor (T5) [Watakabe: Fig.16: output transistor BCT of the pixel 103E] are both used to load a first light-emitting control signal (EM) [Watakabe: Fig.16: light emission control scanning signal line Sga; ¶ 0116: “he gate electrode is connected to the light emission control scanning line Sga. As a result, the output transistor BCT is turned on (conduction state) and off (non-conduction state) by a control signal BG (1 to m/2) from the light emission control scanning line Sga”; ¶ 0052: “the dual gate drive is such that on/off is controlled by inputting the same control signal to the gate electrodes arranged above and below the oxide semiconductor layer”; Examiner: Where BCT takes the dual gate structure of transistor 220, the control signal BG is applied to both conductive layer 204_2 and conductive layer 214_2.];
a first conductive region of the first light-emitting control transistor (T5) [Watakabe: Fig.16: output transistor BCT of the pixel 103E] is used to load a first driving power supply voltage (VDD) [Watakabe: Fig.16: high potential power source SLa; ¶ 0116: “In the output transistor BCT, the drain electrode is connected to the high potential power source Sla”; ¶ 0110: “The high potential power source Pvdd is applied to the high potential power source SLa”];
and a second conductive region of the first light-emitting control transistor (T5) [Watakabe: Fig.16: output transistor BCT of the pixel 103E] is electrically connected to the first conductive region of the driving transistor (T3) [Watakabe: Fig.16: driving transistor DRT; ¶ 0116: “the source electrode is connected to the drain electrode of the driving transistor DRT”; ¶ 0117: “In the driving transistor DRT, the drain electrode is connected to the source electrode of the output transistor BCT”]
through a conductive structure [Watakabe: Fig.3: source and drain electrodes 218_1 to 218_4; ¶ 0083: “a contact hole reaching the oxide semiconductor layers 208_1 and 208_2 and the conductive layer 214_1 is formed in the insulating film 212 and the insulating film 216”].
Regarding claim 15:
Watakabe in view of Zhou and further in view of Kang discloses:
15. (Currently Amended) The pixel driving circuit [Watakabe: Fig.10: pixel 103B; ¶ 0094: “FIG. 10 is an equivalent circuit diagram of the pixel 103B”] according to claim 6,
wherein the conductive structure is located in one or more of the light-shielding metal layer (LS), the first gate layer (GT1) [Watakabe: Fig.11: conductive layer 204_1; Fig.3: conductive layers 204_1 and 204_2] , the second gate layer (GT2) [Watakabe: Fig.11: conductive layer 214; Fig.3: conductive layers 214_1 and 214_2] , the semiconductor layer (SCL), and the source-drain metal layer (SD) [Watakabe: Fig.3: source and drain electrodes 218_1 to 218_4; ¶ 0083: “a contact hole reaching the oxide semiconductor layers 208_1 and 208_2 and the conductive layer 214_1 is formed in the insulating film 212 and the insulating film 216. Next, the source electrodes are the drain electrodes 218_1 to 218_4 are formed on the insulating film 216”; Examiner: The claim requires the conductive structure to be located in on or more of five recited layers. The source and drain electrodes 218 constitute the source-drain metal layer and satisfy that recitation.].
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over [Watakabe; Hajime et al., US 20230169922 A1] in view of [Kang; Pengtao, US 20160049453 A1].
Regarding claim 19:
Watakabe discloses:
19. (New) The pixel driving circuit [Watakabe: Fig.10: pixel 103B; ¶ 0094: “FIG. 10 is an equivalent circuit diagram of the pixel 103B”] according to claim 3,
wherein the driving transistor (T3) [Watakabe: Fig.11: transistor 210A; ¶ 0095: “ the transistor 210A corresponds to the driving transistor DRT shown in FIG. 10”] and the at least one switching transistor [Watakabe: Fig.11: transistor 250; ¶ 0095: “the transistor 250 corresponds to the writing transistor SST shown in FIG. 10”; ¶ 0044: “The writing transistor SST functions as a switching element that selects conduction or non-conduction between...”].
However, Watakabe does not expressly disclose:
that the driving transistor and the at least one switching transistor are all etch stop layer (ESL) transistors.
Kang discloses:
etch stop layer (ESL) transistors [Kang: ¶ 0048: “the bottom-gate type thin film transistor includes the gate 14, the gate insulating layer, the active region 11, an etch stop layer, the source and the drain 17 which are sequentially provided on the base substrate 10, wherein, the source and the drain 17 are respectively connected to the active region 11 through contact vias 16 which penetrate through the etch stop layer”; ¶ 0082: “An etch stop layer (ESL) is formed on the active regions 11 by processes such as sputtering, exposure, development, etching, stripping off, and the like. The sources and the drains 17 of the switching thin film transistor 2 and the driving thin film transistor 1 are formed on the etch stop layer by processes such as sputtering, exposure, development, etching, stripping off, and the like, and the sources and the drains 17 are respectively connected to the respective active regions through the contact vias 16 penetrating through the etch stop layer”; Examiner: Kang applies etch stop layer to both the driving thin film transistor 1 and the switching thin film transistor 2.]
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form the transistors of Watakabe with an etch stop layer as taught by Kang. Watakabe forms its source and drain electrodes 218 directly on the oxide semiconductor layers through contact holes (¶ 0083), exposing the channel to the source-drain etch, whereas Kang interposes an etch stop layer between the active region and the source and drain and applies it both the driving and switching transistors (¶ 0048, 0082). One of ordinary skill would have been motivated to adopt that arrangement to protect the oxide channel during source-drain patterning, and Watakabe confirms at ¶ 0113 that all of its driving and switching transistors are formed in the same process, so the layer applies to both as claimed. Kang is analogous art, an OLED array substrate.
Allowable Subject Matter
Claims 2, 7-14, and 17-18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2:
The prior art does not teach or suggest either singularly or in combination the at least claimed “wherein the display panel has a base substrate, a light-shielding metal layer, an inorganic buffer layer, a first gate layer, a first gate insulating layer and a semiconductor layer that are stacked in sequence; and an active layer of the driving transistor is located in the semiconductor layer, and the driving transistor has the bottom gate located in the first gate layer, wherein the pixel driving circuit further comprises a storage capacitor, wherein a first electrode plate of the storage capacitor is located in the light-shielding metal layer of the display panel, and a second electrode plate of the storage capacitor serves as the bottom gate of the driving transistor”, in combination with the other recited claim features.
Regarding claim 7:
The prior art does not teach or suggest either singularly or in combination the at least claimed “wherein the at least one switching transistor includes a data writing transistor for loading a data voltage and a gate reset transistor for resetting the bottom gate of the driving transistor; the data writing transistor includes a bottom gate located in the first gate layer, an active layer located in the semiconductor layer, and a top gate located in the second gate layer; the top gate and bottom gate of the data writing transistor are both used to load a first scan signal, and a first conductive region of the data writing transistor is used to load the data voltage; the gate reset transistor includes a bottom gate located in the first gate layer, an active layer located in the semiconductor layer, and a top gate located in the second gate layer; the bottom gate and top gate of the gate reset transistor are both used to load a second scan signal, and a first conductive region of the gate reset transistor is used to load a first initialization voltage; and a second conductive region of the data writing transistor, a second conductive region of the gate reset transistor, and the bottom gate of the driving transistor are electrically connected to each other through a conductive structure, wherein the pixel driving circuit further comprises a storage capacitor, wherein a first electrode plate of the storage capacitor serves as the bottom gate of the driving transistor, and a second electrode plate of the storage capacitor is located in the light-shielding metal layer”, in combination with the other recited claim features.
Regarding claim 8:
The prior art does not teach or suggest either singularly or in combination the at least claimed “further comprising a storage capacitor, wherein a first electrode plate of the storage capacitor serves as the bottom gate of the driving transistor, and a second electrode plate of the storage capacitor is located in the light-shielding metal layer; the at least one switching transistor includes an electrode reset transistor for resetting a pixel electrode of the light-emitting element; the electrode reset transistor includes a bottom gate located in the first gate layer, an active layer located in the semiconductor layer, and a top gate located in the second gate layer; the top gate and bottom gate of the electrode reset transistor are both used to load a third scan signal, and a first conductive region of the electrode reset transistor is used to load a second initialization voltage; and a second conductive region of the electrode reset transistor, the second electrode plate of the storage capacitor, the second conductive region of the driving transistor and the pixel electrode are electrically connected through a conductive structure”, in combination with the other recited claim features.
Regarding claim 9:
The prior art does not teach or suggest either singularly or in combination the at least claimed “comprising a storage capacitor, wherein a first electrode plate of the storage capacitor serves as the bottom gate of the driving transistor, and a second electrode plate of the storage capacitor is located in the light-shielding metal layer; the at least one switching transistor includes a threshold compensation transistor and a gate reset transistor for resetting the bottom gate of the driving transistor; the threshold compensation transistor includes a bottom gate located in the first gate layer, an active layer located in the semiconductor layer, and a top gate located in the second gate layer; the top gate and bottom gate of the threshold compensation transistor are both used to load a first scan signal, and a second conductive region of the threshold compensation transistor is electrically connected to the first conductive region of the driving transistor; the gate reset transistor includes a bottom gate located in the first gate layer, an active layer located in the semiconductor layer, and a top gate located in the second gate layer; the bottom gate and top gate of the gate reset transistor are both used to load a first reset control signal, and a first conductive region of the gate reset transistor is used to load a first initialization voltage; and the bottom gate of the driving transistor, a first conductive region of the threshold compensation transistor, and a second conductive region of the gate reset transistor are electrically connected to each other through a conductive structure”, in combination with the other recited claim features.
Regarding claim 10:
The prior art does not teach or suggest either singularly or in combination the at least claimed “wherein the at least one switching transistor includes a threshold compensation transistor and a first light-emitting control transistor; the threshold compensation transistor includes a bottom gate located in the first gate layer, an active layer located in the semiconductor layer, and a top gate located in the second gate layer; the top gate and bottom gate of the threshold compensation transistor are both used to load a first scan signal, and a first conductive region of the threshold compensation transistor is electrically connected to the bottom gate of the driving transistor; the first light-emitting control transistor includes a bottom gate located in the first gate layer, an active layer located in the semiconductor layer, and a top gate located in the second gate layer; the bottom gate and top gate of the first light-emitting control transistor are both used to load a first light-emitting control signal, and a first conductive region of the first light-emitting control transistor is used to load a first driving power supply voltage; and the first conductive region of the driving transistor, a second conductive region of the first light-emitting control transistor, and a second conductive region of the threshold compensation transistor are electrically connected to each other through a conductive structure”, in combination with the other recited claim features.
Regarding claim 11:
The prior art does not teach or suggest either singularly or in combination the at least claimed “wherein the at least one switching transistor include includes a data writing transistor and a second light-emitting control transistor; the data writing transistor includes a bottom gate located in the first gate layer, an active layer located in the semiconductor layer, and a top gate located in the second gate layer; the bottom gate and top gate of the data writing transistor are both used to load a second scan signal, and a first conductive region of the data writing transistor is used to load a data voltage; the second light-emitting control transistor includes a bottom gate located in the first gate layer, an active layer located in the semiconductor layer, and a top gate located in the second gate layer; the bottom gate and top gate of the second light-emitting control transistor are both used to load a first light-emitting control signal, and a second conductive region of the second light-emitting control transistor is electrically connected to a pixel electrode of the light-emitting element; and the second conductive region of the driving transistor, a second conductive region of the data writing transistor, and a first conductive region of the second light-emitting control transistor are electrically connected through a conductive structure”, in combination with the other recited claim features.
Regarding claim 12:
The prior art does not teach or suggest either singularly or in combination the at least claimed “further comprising a storage capacitor, wherein a first electrode plate of the storage capacitor serves as the bottom gate of the driving transistor, and a second electrode plate of the storage capacitor is located in the light-shielding metal layer; the at least one switching transistor includes a second light-emitting control transistor and an electrode reset transistor for resetting a pixel electrode of the light-emitting element; the second light-emitting control transistor includes a bottom gate located in the first gate layer, an active layer located in the semiconductor layer, and a top gate located in the second gate layer; the bottom gate and top gate of the second light-emitting control transistor are both used to load a first light-emitting control signal, and a first conductive region of the second light-emitting control transistor is electrically connected to the second conductive region of the driving transistor; the electrode reset transistor includes a bottom gate located in the first gate layer, an active layer located in the semiconductor layer, and a top gate located in the second gate layer; the top gate and bottom gate of the electrode reset transistor are both used to load a second reset control signal, and a first conductive region of the electrode reset transistor is used to load a second initialization voltage; and a second conductive region of the electrode reset transistor, the second electrode plate of the storage capacitor, a second conductive region of the second light-emitting control transistor and the pixel electrode are electrically connected through a conductive structure”, in combination with the other recited claim features.
Regarding claim 13:
The prior art does not teach or suggest either singularly or in combination the at least claimed “further comprising a storage capacitor, wherein the storage capacitor includes a first electrode plate located in the first gate layer and a second electrode plate located in the light-shielding metal layer; the at least one switching transistor includes a second light-emitting control transistor, a gate reset transistor and a data writing transistor; the second light-emitting control transistor includes a bottom gate located in the first gate layer, an active layer located in the semiconductor layer, and a top gate located in the second gate layer; the bottom gate and top gate of the second light-emitting control transistor are both used to load a second light-emitting control signal; the gate reset transistor includes a bottom gate located in the first gate layer, an active layer located in the semiconductor layer, and a top gate located in the second gate layer; the bottom gate and top gate of the gate reset transistor are both used to load a second reset control signal, and a first conductive region of the gate reset transistor is used to load a first initialization voltage; a second conductive region of the second light-emitting control transistor, a second conductive region of the gate reset transistor, and the bottom gate of the driving transistor are electrically connected through a conductive structure; the data writing transistor includes a bottom gate located in the first gate layer, an active layer located in the semiconductor layer, and a top gate located in the second gate layer; the bottom gate and top gate of the data writing transistor are both used to load a first scan signal, and a first conductive region of the data writing transistor is used to load a data voltage; and a second conductive region of the data writing transistor, a first conductive region of the second light-emitting control transistor, and the first electrode plate of the storage capacitor are electrically connected to each other through a conductive structure”, in combination with the other recited claim features.
Regarding claim 14:
The prior art does not teach or suggest either singularly or in combination the at least claimed “further comprising an auxiliary capacitor and a storage capacitor; the auxiliary capacitor includes a first electrode plate located in the first gate layer and a second electrode plate located in the light-shielding metal layer, and the storage capacitor includes a first electrode plate located in the first gate layer and a second electrode plate located in the light-shielding metal layer; the at least one switching transistor includes a voltage- stabilizing transistor, a data writing transistor, and an electrode reset transistor; the voltage-stabilizing transistor includes a bottom gate located in the first gate layer, an active layer located in the semiconductor layer, and a top gate located in the second gate layer; the bottom gate and top gate of the voltage-stabilizing transistor are both used to load a second reset control signal, and a first conductive region of the voltage-stabilizing transistor is used to load a first initialization voltage; the data writing transistor is used for loading a data voltage onto the first electrode plate of the storage capacitor in response to a first scan signal; the electrode reset transistor includes a bottom gate located in the first gate layer, an active layer located in the semiconductor layer, and a top gate located in the second gate layer; the bottom gate and top gate of the electrode reset transistor are both used to load a first reset control signal, and a first conductive region of the electrode reset transistor is used to load a second initialization voltage; and the second electrode plate of the auxiliary capacitor, the second electrode plate of the storage capacitor, and a second conductive region of the voltage-stabilizing transistor are electrically connected to each other through a conductive structure”, in combination with the other recited claim features.
Regarding claim 17:
The prior art does not teach or suggest either singularly or in combination the at least claimed “wherein the display panel has a base substrate, a light-shielding metal layer, an inorganic buffer layer, a first gate layer, a first gate insulating layer, a semiconductor layer, a second gate insulating layer, a second gate layer, a planarization layer and a source-drain metal layer that are stacked in sequence; and an active layer of the driving transistor is located in the semiconductor layer, and the driving transistor has the top gate located in the second gate layer, wherein the pixel driving circuit further comprises a storage capacitor, wherein a first electrode plate of the storage capacitor is located in the first gate layer, and a second electrode plate of the storage capacitor is located in the light-shielding metal layer and is electrically connected to the top gate of the driving transistor”, in combination with the other recited claim features.
Regarding claim 18:
Claim 18 depend on claim 17 and is found allowable for at least the same reason as discussed above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
[Han; Younghun et al., US 20240081098 A1] discloses:
“The present disclosure provides a thin film transistor, an electroluminescent display device and a driving transistor. A thin film transistor according to an exemplary embodiment of the present disclosure includes a semiconductor layer, a first insulating layer disposed on the semiconductor layer, two or more first gate electrodes disposed on the first insulating layer and separated from each other, a second insulating layer disposed on the first gate electrodes, a source electrode and a drain electrode disposed on the second insulating layer and respectively electrically connected to a source region and a drain region of the semiconductor layer and a second gate electrode disposed above the first gate electrodes, a channel region may be configured between the source region and the drain region. As a result, it becomes possible to increase subthreshold swing (SS) value, and thus, it becomes possible to improve low gradation spots without increasing a bezel width,” as recited in the abstract.
Inquiry
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/KOOSHA SHARIFI-TAFRESHI/Primary Examiner, Art Unit 2628
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