DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
If the exception under 35 U.S.C. 102(b)(2)(C) is properly invoked, a disqualified U.S. patent document is not prior art under 35 U.S.C. 102(a)(2) as of its effectively filed date (for both anticipation and obviousness rejections), but it may still be used as prior art under 35 U.S.C. 102(a)(1) as of its publication or issue date. In addition, the examiner may make a subsequent, new double patenting rejection based upon the disqualified reference. See MPEP 717.02 and 2154.02.
4. Claims 1-4, and 8-9 are rejected under AIA 35 U.S.C. 102(a)(1)(2) as being anticipated by Yumoto (US Publication 2019/0124292).
Regarding claim 1, Yumoto discloses a video signal processing device (Yumoto, fig. 1, para. 0027, image processing device 10A) comprising:
a receiving interface that receives a video signal that represents a moving image (Yumoto, para. 0038, image input unit 12 receives from camera 30 input image signal Vin via a receiving interface; image input unit 12 generates and outputs first image information Vdat1 (for example, YUV420) based on the received input image signal Vin);
a video processing circuit that generates a first signal by performing video processing in a pattern among a plurality of video processing patterns in which the video processing circuit is capable of performing video processing on the video signal received by the receiving interface (Yumoto, para. 0039, High-image quality processor 13 converts the image quality in a frame unit with respect to first image information Vdat1 stored in frame memory 16. Specifically, high-image quality processor 13 performs high-image quality processing including, for example, image distortion correction, view angle conversion, and noise reduction on first image information Vdat1 based on enable signal EN from controller 11, and outputs second image information Vdat2 “first signal” having high-image quality);
a capture circuit that generates a second signal by capturing the video signal received by the receiving interface (Yumoto, para. 0040, Interpolation frame setting unit 14 sets an interpolation frame output in the transition period based on enable signal EN and change signal CHG from controller 11 in the case that the high-image quality display is changed to the low-image quality display or in the case that the low-image quality display is changed to the high-image quality display. Specifically, in the case that enable signal EN is determined to be changed from “1” to “0”, namely, in the case that the low-speed traveling is changed to the high-speed traveling, interpolation frame setting unit 14 sets the interpolation frame output in the transition period in order to transition smoothly to the low-image quality display based on input enable signal EN and change signal CHG. In the case that enable signal EN is changed from “0” to “1”, namely, in the case that the high-speed traveling is changed to the low-speed traveling, interpolation frame setting unit 14 sets the interpolation frame output in the transition period in order to transition smoothly to the high-image quality display. Image information Vdat3 about the interpolation frame is stored in frame memory 16. Image information Vdat3 “second signal” may be selected from image information Vdat1 stored in frame memory 16, or image information Vdat3 may newly be generated based on first image information Vdat1);
a compositing circuit that outputs a composite signal by compositing the first signal and the second signal (Yumoto, para. 0043, image output unit 15 reads second image information Vdat2 having high-image quality as output image information Vdat4 for the low-speed traveling, and reads first image information Vdat1 having low-image quality for the high-speed traveling. Image output unit 15 reads third image information Vdat3 in the transition period in which the vehicle speed changes to change the high-image quality display to the low-image quality display and the transition period in which the low-image quality display is changed to the high-image quality display. Output image signal Vout is input to display device 20. The image captured by on-board camera 30 is displayed on display device 20 with a slight frame delay); and
a processor (Yumoto, fig’s 1-3, controller 11) that:
(a) in a first period, controls the compositing circuit to output the first signal as the composite signal (Yumoto, para. 0043, image output unit 15 reads second image information Vdat2 having high-image quality as output image information Vdat4 for the low-speed traveling, and reads first image information Vdat1 having low-image quality for the high-speed traveling. Image output unit 15 reads third image information Vdat3 in the transition period in which the vehicle speed changes to change the high-image quality display to the low-image quality display and the transition period in which the low-image quality display is changed to the high-image quality display. Output image signal Vout is input to display device 20. The image captured by on-board camera 30 is displayed on display device 20 with a slight frame delay; in a first period, controller 11 controls the image output unit 15 so as to output the second image information Vdat2 as “a composite signal”);
(b) in a second period, controls the video processing circuit to perform changing of the pattern of the video processing performed by the video processing circuit, the second period being a period not included in the first period (Yumoto, para. 0043, in a second period that is a period not included in the first period, controller 11 controls the high-quality processing unit 13 so as to change the pattern of the video processing performed by the high-quality processing unit 13); and (c) in a change period, controls: the capture circuit to generate the second signal; and the compositing circuit to output the second signal as the composite signal, the change period being a period in which the changing is performed (Yumoto, para. 0043, image output unit 15 reads second image information Vdat2 having high-image quality as output image information Vdat4 for the low-speed traveling, and reads first image information Vdat1 having low-image quality for the high-speed traveling. Image output unit 15 reads third image information Vdat3 in the transition period in which the vehicle speed changes to change the high-image quality display to the low-image quality display and the transition period in which the low-image quality display is changed to the high-image quality display. Output image signal Vout is input to display device 20. The image captured by on-board camera 30 is displayed on display device 20 with a slight frame delay; in a change period, controls the interpolation frame setting unit 14 so as to generate the third image information Vdat3 and controls the image output unit 15 so as to output the third image information Vdat3 as “a composite signal”).
Regarding claim 2, Yumoto discloses the video signal processing device according to claim 1 further comprising:
a memory, wherein the processor controls the capture circuit to store, in the memory, the second signal generated by the capture circuit (Yumoto, para. 0040, Image information Vdat3 about the interpolation frame is stored in frame memory 16), and
when a first time length corresponding to first latency that occurs in the video signal due to the video processing in a first pattern is different from a second time length corresponding to second latency that occurs in the video signal due to the video processing in a second pattern, the processor controls the compositing circuit to output, in the change period, the second signal whose elapsed time since being stored in the memory is a time length between the first time length and the second time length, the first pattern being a pattern before the changing among the plurality of video processing patterns, the second pattern being a pattern after the changing among the plurality of video processing patterns (Yumoto, para’s 0068-0082, fig’s 9-10, the interpolation frame is set in the transition period such that the frame delay amount of the output image decreases gradually from the four frames toward the one frame “first time length corresponding to first delay latency”, so that the high-image quality display of the four frame delays is smoothly changed to the low-image quality display of the one frame delay without damaging the continuity of the frames. Although the long transition period is required as compared with a technique of simply thinning the frame, motion discontinuity of a moving image can be reduced, and the degradation of the quality can be prevented; the interpolation frame is set in the transition period such that the frame delay amount of the output image increases gradually from the one frame toward the four frames “second time length corresponding to second delay latency”, so that the low-image quality display of the one frame delay is smoothly changed to the high-image quality display of the four frame delays without damaging the continuity of the frames. Although the long transition period is required as compared with a technique of simply repeating the frame, motion discontinuity of a moving image can be reduced, and the degradation of the quality can be prevented; the control unit 11 controls the image output unit 15 such that the elapsed time after the third image information Vdat3 output by an image output unit 15 within the change period is stored in the frame memory 16 changes from a first time to a second time).
Regarding claim 3, Yumoto discloses the video signal processing device according to claim 2, wherein the processor controls the compositing circuit to cause the elapsed time of the second signal since being stored in the memory to change from the first time length toward the second time length, the second signal being outputted by the compositing circuit in the change period (Yumoto, para’s 0068-0082, fig’s 9-10, the control unit 11 controls the image output unit 15 such that the elapsed time after the third image information Vdat3 output by an image output unit 15 within the change period is stored in the frame memory 16 changes from a first time to a second time).
Regarding claim 4, Yumoto discloses the video signal processing device according to any one of claim 1, wherein the receiving interface receives a command to change the video processing performed on the video signal by the video processing circuit to lower-latency video processing, and when the receiving interface receives the command, in (b), the processor controls the video processing circuit to change the video processing performed on the video signal to the lower-latency video processing (Yumoto, para’s 0083-0088, fig’s 11-12, a receiving interface of the image processing device receives an instruction to change video processing performed on a video signal by the high-quality processing unit 13 to lower-delay video processing, and (b) when the reception interface receives an instruction, the control unit 11 performs control such that video processing performed on the video signal by the high-quality processing unit 13 is changed to lower-delay video processing).
Claims 8-9 are rejected for the same reasons set forth in claim 1. Yumoto further discloses computer readable medium (see Yumoto, para. 0087, fig. 1, ROM memory medium 112).
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1,148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating
obviousness or nonobviousness.
6. Claim 5 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Yumoto, as applied to claim 1 above, in view of Pulli et al. (US Publication 2017/0099439).
Regarding claim 5, Yumoto discloses the video signal processing device according to any one of claim 1 comprising the change period, the change period being a period in which the changing is performed as described in claim 1 above.
Yumoto does not explicitly disclose but Pulli discloses wherein at a time immediately before or after the change period, the processor controls the compositing circuit to generate and output the composite signal by blending a pixel value included in the first signal with a pixel value included in the second signal (Pulli, para. 0262, the method of method embodiment 13, wherein generating a composite image includes combining the first portion of said scene area of interest included in the first image captured by said first camera module during the second image capture time period and having a first resolution with the missing second portion of said scene area of interest included in the identified image including the second missing scene portion, the identified image including the missing second image portion being an image captured during an image capture time period preceding or following the second image capture time period).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Pulli’s features into Yumoto’s invention for enhancing user’s viewing experience with smooth visual transition by preventing abrupt display of image content.
7. Claim 6 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Yumoto, as applied to claim 1 above, in view of Saito (US Publication 2020/0169647).
Regarding claim 6, Yumoto discloses the video signal processing device according to any one of claim 1.
Yumoto does not explicitly disclose but Saito discloses wherein the compositing circuit includes an on-screen display (OSD) compositing circuit that composites the first signal and the second signal as an OSD signal (Saito, para. 0069, the OSD superimposing circuit 66 combines the image information included in the first signal S1 or the second signal S2 with another OSD information and outputs the combined image information).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Saito’s features into Yumoto’s invention for enhancing user’s viewing experience by providing unified rendering and preventing synchronization issues between multiple video signals.
8. Claim 7 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Yumoto, as applied to claim 1 above, in view of Uemura et al. (US Publication 2011/0249089).
Regarding claim 7, Yumoto discloses the video signal processing device according to any one of claim 1, wherein the processor controls the compositing circuit to cause the elapsed time of the second signal since being stored in the memory to change from the first time length toward the second time length, the second signal being outputted by the compositing circuit in the change period (Yumoto, para’s 0068-0082, fig’s 9-10, the control unit 11 controls the image output unit 15 such that the elapsed time after the third image information Vdat3 output by an image output unit 15 within the change period is stored in the frame memory 16 changes from a first time to a second time).
Yumoto does not explicitly disclose but Uemura discloses wherein the compositing circuit further includes a muting circuit that switches whether to mute the first signal generated by the video processing circuit, and the processor controls the muting circuit to mute the first signal in the change period (Uemura, para’s 0011-0013, under the control of the CPU 14, when the video changing unit 13 changes a video signal to another type of video signal, in order to prevent the displayed videos from looking untidy during the change, a process called an image mute is temporarily performed. In the image mute process, for example, if a first video signal is assumed to be changed to a second video signal, a last frame of the first video signal is displayed, and thereafter an entirely black image is displayed during a period of one frame or several frames. After the entirely black image is displayed, a video based on the second video signal is displayed).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Uemura’s features into Yumoto’s invention for enhancing user’s viewing experience by preventing visual artifacts and ensuring a seamless viewing experience.
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. These include:
Staker et al., US Publication 2004/0218100
Hendry et al., US Publication 2015/0036734
Tanaka et al., US Publication 2014/0376873
Conclusion
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to LOI H TRAN whose telephone number is (571)270-5645. The examiner can normally be reached 8:00AM-5:00PM PST FIRST FRIDAY OF BIWEEK OFF.
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/LOI H TRAN/Primary Examiner, Art Unit 2484
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