Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-5, 8, 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bae (US 20120212401) in view of Kim (US 20200342806).
Regarding claim 1 Bae teaches a display device (fig.1), comprising:
a clock signal output circuit (fig.2A, 210, SC1):
a plurality of clock signal lines (CLK1, CLK2);
a driver circuit including a shift register and electrically connected to the plurality of clock signal lines (fig. 2A, CK1, Ck2);
a plurality of pixel circuits (fig. 1, [0046] [0047]); and
at least one of a first time-constant circuit (fig.1, 431, [0053]) connected between the clock signal output circuit (fig.1, 210, 230) and the plurality of clock signal lines (fig.1, clk1, clk2, clk3, clk4 ) or a second time-constant circuit connected between the driver circuit and the plurality of pixel circuits;
Bae is silent on a touch sensor layer including: a sensor electrode group; and a routed wire group electrically connected to the sensor electrode group, wherein the touch sensor layer includes a routing region in which the routed wire group is formed, and in a plan view,
the routing region overlaps with the plurality of clock signal lines.
However, Kim teaches a touch sensor layer including: a sensor electrode group (fig.8, TE-1-1, TE2); and a routed wire group (fig. 8, TL1, TL2) electrically connected to the sensor electrode group, wherein the touch sensor layer includes a routing region (fig. 9 TL region) in which the routed wire group is formed, and in a plan view (fig. 8, fig. 9),
the routing region (fig. 9, TL) overlaps with the plurality of clock signal lines (fig. 9, first clock signal line CL1, the second clock signal line CL2).
Therefore, it would have been obvious to one of the ordinary skilled in the art to combine Bae in light of Kim teaching so that it may include a touch sensor layer including: a sensor electrode group; and a routed wire group electrically connected to the sensor electrode group, wherein the touch sensor layer includes a routing region in which the routed wire group is formed, and in a plan view, the routing region overlaps with the plurality of clock signal lines.
The motivation is to provide display devices are provided with an input sensing layer as an input device that facilitates intuitive interface, space-saving design and faster task execution.
Claim 2 is canceled.
Regarding claim 3 Bae teaches wherein the first time-constant circuit (fig. 1, 431) distorts waveforms (fig. 2A) of a plurality of clock signals (fig. 3) to be input from the clock signal output circuit (fig.1, 210, 230).
Regarding claim 4 Bae teaches wherein the second time-constant circuit (fig. 1, 432) distorts waveforms (fig. 2B) of a plurality of clock signals (fig. 3) to be input from the clock signal output circuit (fig.1, 210, 230).
Regarding claim 5 Bae teaches further comprising a plurality of scan signal lines, wherein the driver circuit outputs a drive signal to each of the plurality of scan signal lines (fig. 2, see 230, GLi, GLj).
Claims 6-7 canceled.
Regarding claim 8 Bae teaches wherein each of the plurality of clock signal lines is supplied with a clock signal, and each of a rise period and a fall period of the clock signal (fig. 4, CK1 to CK4 got rise and fall time). While Bae does not expressly teach each of a rise period and a fall period of the clock signal is 1.5 micro-second or longer. However, it would have been obvious to a person having ordinary skill in the art at the time of the invention to implement each of a rise period and a fall period of the clock signal is 1.5 micro-second or longer since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 28 Bae in view of Kim teach further comprising: a touch sensor layer including a sensor electrode group (Kim: fig.8, TE-1-1, TE2) and a routed wire group (Kim: fig. 8, TL1, TL2) electrically connected to the sensor electrode group (Kim: fig. 8, fig. 9);
a first clock signal line that transmits the first clock signal; and a second clock signal line that transmits the second clock signal (fig.1), wherein the touch sensor layer includes a routing region in which the routed wire group is formed, and in a plan view, the routing region overlaps with the first clock signal line and the second clock signal line (Kim: fig. 9, first clock signal line CL1, the second clock signal line CL2).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 10-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US 20200342806).
Regarding claim 10 Bae teaches a display device (fig. 1), comprising:
a first driver (fig.1, 210) configured to receive a first clock signal and a second clock signal (fig. 1, CK1, CK2) and to generate a scan signal (GLi),
a second driver (fig.1, 230) configured to receive a third clock signal and a fourth clock signal (fig. 1, CK3, CK4) and to generate a discharge control signal (fig. 8, ), and a pixel circuit configured to receive the scan signal and the discharge control signal ([0106] The first discharging circuit 241 is in a second peripheral area PA2. The first discharging circuit 241 is electrically connected to a second end of the gate lines GLi-1 and Gli opposite to the first end, and discharges a high voltage VON of the gate signal applied to each gate line GLi-1 or GLi to a low voltage VOFF The first discharging circuit 241 includes a first discharging transistor TR1 and a voltage line VL transmitting the low voltage VOFF. As shown in FIG. 8, the first discharging transistor TR1 is in the second peripheral area PA2 between the stages SCj-1 and SCj-2 and is in the second peripheral area PA2 corresponding to (e.g., not exceeding) a width of the pixel row defined by a distance between the (i-1)-th and (j-1)-th gate lines GLi-1 and GLj-1), wherein a rise timing of the first clock signal is different from rise timings of the third clock signal and the fourth clock signal (fig, 3, CK1 rise time different from rise timings CK3 and CK4).
Regarding claim 11 Bae teaches wherein fall timing of the first clock signal (fig. 3, CK1) is different from fall timings of the third clock signal (fig.1, CK3) and the fourth clock signal (fig.1, CK4).
Regarding claim 12 Bae teaches wherein a rise timing of the second clock signal (fig. 3, CK2) is different from rise timings of the third clock signal (fig.1, CK3) and the fourth clock signal (fig.1, CK4).
Regarding claim 13 Bae teaches wherein a fall timing of the second clock signal (fig. 3, CK2) is different from fall timings of the third clock signal (fig. 3, CK3) and the fourth clock signal (fig. 3, CK4).
Regarding claim 14 Bae teaches wherein an active period of the third clock signal includes an active period of the first clock signal (fig. 3).
Regarding claim 15 Bae teaches wherein an active period of the fourth clock signal includes an active period of the second clock signal (fig. 3).
Allowable Subject Matter
Claims 20-22, 24, 26 allowed. As none of the prior art teaches “wherein a rise period of the fifth clock signal overlaps with a fall period of at least one of the second clock signal or the fourth clock signal.:
Claims 9, 16, 17 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
-Chung US 20070063933 teaches some aspect of independent claim.
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/TOWFIQ ELAHI/Primary Examiner, Art Unit 2625
