DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier.
Claims 1, and 11-17 are hereby interpreted under 35 U.S.C. 112(f). Claims 1, 11, and 17 include the language “compensation unit…configured to.” The supporting structure for this language is read as the structure mentioned in claims 2 and 18. Claims 12-16 are interpreted under 35 U.S.C. 112(f) for similar reasons for depending upon base claims that are interpreted under 35 U.S.C. 112(f).
Because these claim limitations are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitations interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitations to avoid them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al (Publication number: US 2017/0147121).
Consider Claim 1, Yang et al shows a display driving circuit (see figure 4), comprising:
(a) A first transistor connected to a display light-emitting unit (see figure 4; and paragraph 49); (The first transistor is read as DT0; and the light emitting unit is read as light emitting element 21).
(b) Wherein the display driving circuit further comprises: a storage unit, with a first end connected to a first end of the first transistor through a first node (see figure 4); (The storage unit is read as capacitor C1, and the first node is read as node B).
(c) A first light-emitting control unit, connected to a first light-emitting control line, a high-voltage end of a power supply, and the first node (see figure 4); (Read as T5).
(d) A compensation unit, connected to a second end of the storage unit through a second node, connected to a control end of the first transistor through a third node, and connected to a second end of the first transistor through a fourth node (See figure 4; and paragraphs 51-55); (The second node is read as node C; the third node is read node A; and the forth node is read as the node connecting elements 21, 05, and 03).
(e) Wherein the compensation unit is also connected to a first scanning line and a reference voltage line, and is configured to write a voltage of the reference voltage line, a voltage of a high-voltage end of the power supply, and a threshold voltage of the first transistor into the storage unit in response to a signal of the first scanning line (see figures 2 and 4; and paragraphs 36-40); (The reset control module 03 is configured to supply, under control of the reset control signal terminal Scan1, a signal at the second reference signal terminal Vint to the third node C and the anode layer 211 of the organic light-emitting element 21; the data writing module 01 is configured to supply, under control of the writing control signal terminal Scan2, a signal at the data signal terminal Data to the first node A; the compensation module 02 is configured to be charged or discharged according to on or off state of the reset control module 03 and the light-emitting control module 04 and to maintain a voltage difference between the second node B and the third node C as a fixed value when the third node C is in a floating state).
(f) A data writing unit, connected to the first scanning line, a data line, and the third node, wherein the data writing unit is configured to write a signal of the data line into the storage unit in response to the signal of the first scanning line (see figures 2 and 4; and paragraphs 36-40); (An input terminal of the data writing module 01 is connected to the data signal terminal Data, a control terminal thereof is connected to the writing control signal terminal Scan2, and an output terminal thereof is connected to a first node A; an input terminal of the light-emitting control module 04 is connected to the first reference signal terminal VDD, a control terminal thereof is connected to the light-emitting control terminal EM).
(g) A second light-emitting control unit, connected to a second light-emitting control line, the fourth node, and an anode of the display light-emitting unit (see figure 4); (Read as T3).
(h) Wherein a cathode of the display light-emitting unit is connected to a low-voltage end of the power supply (see figure 4); (see the light emitting diode 21 shown in figure 4).
Consider Claim 17, Yang et al shows a display panel (see figure 4), comprising
(a) A display driving circuit, wherein the display driving circuit comprises: a first transistor, connected to a display light-emitting unit (see figure 4; and paragraph 49); (The first transistor is read as DT0; and the light emitting unit is read as light emitting element 21).
(b) A storage unit, with a first end connected to a first end of the first transistor through a first node (see figure 4); (The storage unit is read as capacitor C1, and the first node is read as node B).
(c) A first light-emitting control unit, connected to a first light-emitting control line, a high-voltage end of a power supply, and the first node (see figure 4); (Read as T5).
(d) A compensation unit, connected to a second end of the storage unit through a second node, connected to a control end of the first transistor through a third node, and connected to a second end of the first transistor through a fourth node (See figure 4; and paragraphs 51-55); (The second node is read as node C; the third node is read node A; and the forth node is read as the node connecting elements 21, 05, and 03).
(e) Wherein the compensation unit is also connected to a first scanning line and a reference voltage line, and is configured to write a voltage of the reference voltage line, a voltage of a high-voltage end of the power supply, and a threshold voltage of the first transistor into the storage unit in response to a signal of the first scanning line (see figures 2 and 4; and paragraphs 36-40); (The reset control module 03 is configured to supply, under control of the reset control signal terminal Scan1, a signal at the second reference signal terminal Vint to the third node C and the anode layer 211 of the organic light-emitting element 21; the data writing module 01 is configured to supply, under control of the writing control signal terminal Scan2, a signal at the data signal terminal Data to the first node A; the compensation module 02 is configured to be charged or discharged according to on or off state of the reset control module 03 and the light-emitting control module 04 and to maintain a voltage difference between the second node B and the third node C as a fixed value when the third node C is in a floating state).
(f) A data writing unit, connected to the first scanning line, a data line, and the third node, wherein the data writing unit is configured to write a signal of the data line into the storage unit in response to the signal of the first scanning line (see figures 2 and 4; and paragraphs 36-40); (An input terminal of the data writing module 01 is connected to the data signal terminal Data, a control terminal thereof is connected to the writing control signal terminal Scan2, and an output terminal thereof is connected to a first node A; an input terminal of the light-emitting control module 04 is connected to the first reference signal terminal VDD, a control terminal thereof is connected to the light-emitting control terminal EM).
(g) A second light-emitting control unit, connected to a second light-emitting control line, the fourth node, and an anode of the display light-emitting unit (see figure 4); (Read as T3).
(h) Wherein a cathode of the display light-emitting unit is connected to a low-voltage end of the power supply (see figure 4); (see the light emitting diode 21 shown in figure 4).
Allowable Subject Matter
Claims 11-16 are allowed.
Claims 2-10, and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL A FARAGALLA whose telephone number is (571)270-1107. The examiner can normally be reached Mon-Fri 8:00-5:00.
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/MICHAEL A FARAGALLA/Primary Examiner, Art Unit 2624 06/08/2026
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