Detailed Action
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
2. Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1, 3, 11-12, 15-16, and 19 are rejected under 35 U.S.C. 103 as unpatentable over NA (US 20190385523 A1) in view of WANG (WO 2022226727 A1; using US 20230028312 A1 as a corresponding English translation).
Regarding claim 1, NA discloses a display panel (Fig. 1; display panel 10), comprising a plurality of pixel circuits, wherein a pixel circuit of the plurality of pixel circuits (Fig. 2; pixel circuit PX) comprising:
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a first light-emitting control unit (light-emitting control transistor T5), wherein the first light-emitting control unit (light-emitting control transistor T5) is electrically connected between a first node (node N0) in the pixel circuit and a second node (node N1) in the pixel circuit, and the first node (node N0) is configured to receive a first driving signal (voltage signal ELVDD);
a second light-emitting control unit (light-emitting control transistor T6), wherein the second light-emitting control unit (light-emitting control transistor T6) is electrically connected between a third node (node N2) in the pixel circuit and a fourth node (node N5) in the pixel circuit;
a driving unit (driving transistor T1), wherein the driving unit is electrically connected to the second node (node N1), the third node (node N2) and a fifth node (node N4) in the pixel circuit;
a first data writing unit (transistor T3), wherein the first data writing unit (transistor T3) is electrically connected between the third node (node N2) and a sixth node (node N3) in the pixel circuit;
an isolation unit (transistor T8), wherein the isolation unit (transistor T8) is electrically connected between the fifth node (node N4) and the sixth node (node N3); and
a light-emitting unit (light-emitting element EL), wherein one end of the light-emitting unit (light-emitting element EL) is electrically connected to the fourth node (node N5), and another end of the light-emitting unit (light-emitting element EL) is configured to receive a second driving signal (voltage signal ELVSS);
wherein there is a first time period in which the first data writing unit and the isolation unit are both turned on (e.g., Fig. 3A or 3B; during a time period t1, both transistor T3 and T8 are turned on), and after the first time period, the isolation unit is turned off before the first data writing unit (e.g., Fig. 3A or 3B; after the time period t1, transistor T8 is turned off before transistor T3 is turned off).
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NA (Fig. 2) discloses the first data writing unit (transistor T3) is a N-type transistor and an isolation unit (transistor T8) is a P-type transistor, but does not disclose the transistor T3 is an oxide transistor and T8 is a polysilicon transistor. However, it is well known that a N-type transistor can be implemented as an oxide transistor and a P-type transistor can be implemented as a polysilicon transistor. As a reference, Wang discloses a display panel comprising a pixel circuit (e.g., Fig. 12; pixel circuit) similar to that disclosed by NA, wherein the first data writing unit comprises a N-type transistor T4, an isolation unit comprises a P-type transistor T2, Wang further discloses the N-type transistor is implemented as an oxide transistor, and the P-type transistor is implemented as a polysilicon transistor (Figs. 4, 6, 8, 10, and 12 and [0119], [0141], [0161], [0183], and [0205]; N-type oxide transistor and P-type polysilicon transistor). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from WNAG to the display device of NA. The combination/motivation would be to provide a pixel circuit with a reduced current leakage and a high switching speed.
Regarding claim 3, NA in view of WANG discloses the display panel according to claim 1, wherein the oxide transistor of the first data writing unit is an N-type; and the polysilicon transistor of the isolation unit is P-type (NA (Fig. 2) discloses the transistor T3 of the first data writing unit is a N-type transistor and the transistor T8 of the isolation unit is a P-type transistor, Wang (Figs. 4, 6, 8, 10, and 12) further discloses the N-type transistor is implemented as an oxide transistor and the P-type transistor is implemented as a polysilicon transistor); wherein before the first time period, a rising edge of a gate signal of the oxide transistor is located before a falling edge of a gate signal of the polysilicon transistor; after the first time period, a falling edge of the gate signal of the oxide transistor is located after a rising edge of the gate signal of the polysilicon transistor (e.g., NA’s Fig. 3A or 3B; timing diagram of gate signal GW_N to turn on and off N-type transistor T3 and gate signal GW_P to turn on and off P-type transistor T8, time period t1 corresponding to the first time period). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from WNAG to the display device of NA for the same reason above.
Regarding claim 11, NA in view of WANG discloses a driving method for a display panel, applied to the display panel according to claim 1, NA discloses wherein the driving method (Figs. 2-3 are reproduced on pages 3-4) comprises: controlling the first data writing unit and the isolation unit to be turned on, enabling that there is the first time period in which the first data writing unit and the isolation unit are both turned on, and transmitting writing data to the driving unit (e.g., Fig. 3A or 3B; during the time period t1, both transistor T3 and T8 are turned on, driving transistor T1 is diode-connected); controlling, after the first time period, the isolation unit to be turned off first and then the first data writing unit to be turned off (e.g., Fig. 3A or 3B; after the time period t1, transistor T8 is turned off before transistor T3 is turned off); and controlling the first light-emitting control unit and the second light-emitting control unit to be turned on, enabling the light-emitting unit to emit light under action of the first driving signal and the second driving signal (e.g., Fig. 3A or 3B; first light-emitting control transistor T5 and the second light-emitting control T6 are turned on with light emission control signal EM, light-emitting element emits light, driving current Id is determined by high driving voltage ELVDD and low driving voltage ELVSS).
Regarding claim 12, NA in view of WANG discloses the driving method for the display panel according to claim 11, NA discloses wherein the pixel circuit comprises a first reset unit (Fig. 2; reset transistor T4), and there is a second time period in which the first data writing unit and the first reset unit are both turned on (Fig. 3B; in a time period t2, both transistor T3 and transistor T4 are turned on) and the driving method further comprises: controlling, before the second time period, the first reset unit to be turned on first (Fig. 3B; before the time period t2, transistor T4 is turned on first); and controlling, after the second time period, the first reset unit to be turned off first (Fig. 3B; after the time period t2, transistor T4 is turned off first); wherein the second time period lasts for at least one row scanning duration (Fig. 3B; the time period t2 lasts for at least one row scanning duration).
Regarding claim 15, NA in view of WANG discloses a driving circuit (NA, Fig. 1; driving circuits 20, 30, and 40 of display device), for performing the driving method for the display panel according to claim 11.
Regarding claim 16, NA in view of WANG discloses a display device (NA, Fig. 1; display device 1 including display panel 10), comprising the display panel according to claim 1.
Regarding claim 19, NA in view of WANG discloses a display device (NA, Fig. 1; display device 1), comprising the display panel according to claim 1 and a driving circuit (NA, Fig. 1; driving circuits 20, 30, and 40) for performing a driving method (Figs. 2-3 are reproduced on pages 3-4) for the display panel, wherein the driving method comprises: controlling the first data writing unit and the isolation unit to be turned on, so that there is the first time period in which the first data writing unit and the isolation unit are both turned on, and transmitting writing data to the driving unit (e.g., Fig. 3A or 3B; during the time period t1, both transistor T3 and T8 are turned on, driving transistor T1 is diode-connected); controlling, after the first time period, the isolation unit to be turned off first and then the first data writing unit to be turned off (e.g., Fig. 3A or 3B; after the time period t1, transistor T8 is turned off before transistor T3 is turned off); and controlling the first light-emitting control unit and the second light-emitting control unit to be turned on, so that the light-emitting unit emits light under action of the first driving signal and the second driving signal (e.g., Fig. 3A or 3B; first light-emitting control transistor T5 and the second light-emitting control T6 are turned on with light emission control signal EM, light-emitting element emits light, driving current Id is determined by high driving voltage ELVDD and low driving voltage ELVSS).
5. Claim 2 is rejected under 35 U.S.C. 103 as unpatentable over NA (US 20190385523 A1) in view of WANG (WO 2022226727 A1; using US 20230028312 A1 as a corresponding English translation) and further in view of ZHOU (US 20200211448 A1).
Regarding claim 2, NA in view of WANG discloses the display panel according to claim 1, but does not disclose wherein the oxide transistor of the first data writing unit is in a saturation region in the first time period. However, ZHOU discloses a display panel comprising a pixel circuit (Figs. 5-7 and 11-12), wherein the oxide transistor of the first data writing unit is in a saturation region in the first time period ([0058] and [0089]; N-type oxide transistor T7 is operated in a saturation state). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from ZHOU to the display device of NA in view of WANG. The combination/motivation would be to provide a pixel circuit with a reduced current leakage.
6. Claims 4-6, 10, and 13-14 are rejected under 35 U.S.C. 103 as unpatentable over NA (US 20190385523 A1) in view of WANG (WO 2022226727 A1; using US 20230028312 A1 as a corresponding English translation) and further in view of PARK (US 20160322446 A1).
Regarding claim 4, NA in view of WANG discloses the display panel according to claim 1, NA discloses wherein the pixel circuit (Fig. 2; pixel circuit PX) further comprises: a first reset unit (reset transistor T4), wherein the first reset unit (reset transistor T4) is electrically connected to the sixth node (node N3); wherein there is a second time period in which the first data writing unit and the first reset unit are both turned on, before the second time period, the first reset unit is turned on before the first data writing unit, after the second time period, the first reset unit is turned off before the first data writing unit, and the second time period is non-overlapping with the first time period (e.g., Fig. 3B reproduced on page 3; timing diagram of gate signal GW_N to turn on and off the transistor T3 and gate signal GW_P to turn on and off the transistor T8, time period t1 corresponding to the first time period, time period t2 corresponding to the second time period).
The electrical connection between the first reset unit and the sixth node is different from the claimed invention. However, PARK discloses a display comprising a pixel circuit, wherein the pixel circuit (Fig. 6; pixel circuit 140) further comprises: a first reset unit (reset transistor M4), wherein the first reset unit (reset transistor M4) is electrically connected to the sixth node (node N1), and the first reset unit (reset transistor M4) is configured to transmit a first reset signal (reset voltage signal Vint) to the sixth node (node N1). Park further discloses wherein there is a second time period in which the first data writing unit and the first reset unit are both turned on, before the second time period, the first reset unit is turned on before the first data writing unit, after the second time period, the first reset unit is turned off before the first data writing unit (e.g., Fig. 7; timing diagram of gate signal Si-1 to turn on and off the transistor M3 and gate signal GW_P to turn on and off the transistor M2’, a first time period during which both M2’ and M3 are turned on, and a second time period t2 during which both M2’ and M4 are turned on). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from PARK to the pixel circuit of the display device of NA in view of WANG. The combination/motivation would be to provide a pixel circuit with a reset circuit to initialize a voltage level of the pixel circuit.
Regarding claim 5, NA in view of WANG and further in view of PARK discloses the display panel according to claim 4, PARK discloses wherein before the second time period, there is at least one third time period in which the isolation unit and the first reset unit are both turned on, and before each third time period, the first reset unit is turned on before the isolation unit (e.g., Fig. 7; timing diagram, T11 corresponds to a third time period, during which both reset transistor M4 and transistor M3 are turned on, and reset transistor M4 is turned on before transistor M3 is turned on). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from PARK to the pixel circuit of the display device of NA in view of WANG for the same reason above.
Regarding claim 6, NA in view of WANG and further in view of PARK discloses the display panel according to claim 4, NA discloses wherein the pixel circuit (Fig. 2; pixel circuit PX) further comprises: a second data writing unit (writing transistor T2), wherein the second data writing unit (writing transistor T2) is electrically connected to the second node (node N1), and the second data writing unit (writing transistor T2) is configured to transmit a data signal (data signal DATA) to the second node (node N0); wherein the second data writing unit and the isolation unit have a same on or off state (transistor T2 and transistor T8 are turned on and off with a same gate signal GW_P).
Regarding claim 10, NA in view of WANG discloses the display panel according to claim 1, PARK (Figs. 6-7) discloses wherein the first light-emitting control unit is turned on for at least one row scanning duration before the second light-emitting control unit (Figs. 6-7; first light-emitting control signal Ei-1 and second light-emitting control signal Ei). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from PARK to the pixel circuit of the display device of NA in view of WANG. The combination/motivation would be to provide a pixel circuit with an emission control.
Regarding claim 13, NA in view of WANG discloses the driving method for the display panel according to claim 11, but does not disclose there is at least one third time period as claimed. However, PARK discloses wherein before the second time period, there is at least one third time period in which the isolation unit and the first reset unit are both turned on, and the driving method further comprises: controlling, before the second time period, the first reset unit to be turned on to transmit a first reset signal to the sixth node; and controlling, after the first reset unit is turned on, the isolation unit to be turned on for the at least one third time period to transmit the first reset signal to the fifth node, wherein each third time period lasts for at least one row scanning duration (e.g., Fig. 7; timing diagram, a time period T11 corresponds to a third time period, during which both reset transistor M4 and transistor M3 are turned on, reset transistor M4 is turned on before transistor M3 is turned on, before the time period T11, reset transistor M4 is turned on to transmit a reset voltage Vint to the sixth node N1, reset transistor M4 is turned on both reset transistor M4 and transistor M3 are turned on to transmit a reset voltage to the fifth node N2, time period T11 lasts for at least one row scanning duration). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from PARK to the pixel circuit of the display device of NA in view of WANG. The combination/motivation would be to provide a pixel circuit with a reset circuit to initialize a voltage level of the pixel circuit.
Regarding claim 14, NA in view of WANG discloses the driving method for the display panel according to claim 11, PARK discloses the driving method further comprising: controlling, before controlling the first light-emitting control unit and the second light- emitting control unit to be turned on (Figs. 6-7; first light-emitting control transistor M6 and second light-emitting control transistor M7), the first light-emitting control unit to be turned on for at least one row scanning duration earlier than the second light-emitting control unit (Figs. 6-7; first light-emitting control signal Ei-1 and second light-emitting control signal Ei). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from PARK to the pixel circuit of the display device of NA in view of WANG. The combination/motivation would be to provide a pixel circuit with a emission control.
7. Claims 7-8 are rejected under 35 U.S.C. 103 as unpatentable over NA (US 20190385523 A1) in view of WANG (WO 2022226727 A1; using US 20230028312 A1 as a corresponding English translation) and PARK (US 20160322446 A1) and further in view of OH (US 20210201764 A1).
Regarding claim 7, NA in view of WANG and further in view of PARK discloses the display panel according to claim 6, NA discloses wherein the pixel circuit (Fig. 2; pixel circuit PX) further comprises: a second reset unit (reset transistor T7), wherein the second reset unit (reset transistor T7) is electrically connected to the fourth node (node N5), and the second reset unit (reset transistor T7) is configured to transmit a second reset signal (voltage signal VINT) to the fourth node (node N5); and a capacitor (capacitor CST), wherein one end of the capacitor (capacitor CST) is electrically connected to the first node (node N0), and another end of the capacitor (capacitor CST) is electrically connected to the fifth node (node N4). NA does not disclose a third reset unit as claimed. However, OH discloses a display panel comprising a pixel circuit (Fig. 2; pixel circuit PX), the pixel circuit comprising a third reset unit (reset transistor M4), wherein the third reset unit (reset transistor M4) is electrically connected to the second node (node N1), and the third reset unit (reset transistor M4) is configured to transmit a third reset signal (voltage signal Vint1) to the second node (node N1). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from OH to the pixel circuit of the display device of NA in view of WANG and PARK. The combination/motivation would be to provide a pixel circuit with a reset circuit to initialize a voltage level of the pixel circuit.
Regarding claim 8, NA in view of WANG and further in view of PARK discloses the display panel according to claim 7, wherein the first reset unit comprises an oxide transistor (NA, Fig. 2; reset transistor T4 is an N-type oxide transistor); and/or the second data writing unit comprises a polysilicon transistor (NA, Fig. 2; data writing transistor T2 is an P-type polysilicon transistor); and/or the second reset unit comprises a polysilicon transistor (NA, Fig. 2; reset transistor T7 is an P-type polysilicon transistor); and/or the third reset unit comprises a polysilicon transistor (OH, Fig. 2; reset transistor M4 is an P-type polysilicon transistor); and/or the first light-emitting control unit comprises a polysilicon transistor (NA, Fig. 2; light-emitting control transistor T5 is an P-type polysilicon transistor); and/or the second light-emitting control unit comprises a polysilicon transistor (NA, Fig. 2; light-emitting control transistor T6 is an P-type polysilicon transistor); and/or the driving unit comprises a polysilicon transistor (NA, Fig. 2; driving transistor T1 is an P-type polysilicon transistor).
8. Claim 9 is rejected under 35 U.S.C. 103 as unpatentable over NA (US 20190385523 A1) in view of WANG (WO 2022226727 A1; using US 20230028312 A1 as a corresponding English translation) and PARK (US 20160322446 A1) and OH (US 20210201764 A1) and further in view of KIM (US 20190005883 A1).
Regarding claim 9, NA in view of WANG and further in view of PARK and OH discloses the display panel according to claim 8, but does not disclose wherein the driving unit is a P-type polysilicon transistor, and a potential of the third reset signal is greater than a potential of the first driving signal; or the driving unit is an N-type polysilicon transistor, and the potential of the third reset signal is less than the potential of the first driving signal. However, KIM discloses a display panel, wherein the driving unit is a P-type polysilicon transistor, and a potential of the third reset signal is greater than a potential of the first driving signal (Figs. 19-21; P-type polysilicon transistor M2, VDD2>VDD1). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from KIM to the pixel circuit of the display device of NA in view of WANG, PARK, and OH. The combination/motivation would be to provide a pixel circuit with a reset circuit to initialize a voltage level of the pixel circuit.
9. Claims 17-18 are rejected under 35 U.S.C. 103 as unpatentable over NA (US 20190385523 A1) in view of WANG (WO 2022226727 A1; using US 20230028312 A1 as a corresponding English translation) and further in view of OH (US 20210201764 A1).
Regarding claim 17, NA in view of WANG discloses the driving circuit according to claim 15, NA (Fig. 1) discloses wherein the driving circuit comprises: a light-emitting array driving circuit (emission driver 40), electrically connected to the pixel circuit and configured to provide a light-emitting control signal (emission control signal EM) to the pixel circuit; a gate array driving circuit (gate driver 20), electrically connected to the pixel circuit and configured to provide a first gate driving signal (gate signal GW, GI, and GB) to the pixel circuit. NA does not disclose the gate array driving circuit comprising a first gate array driving circuit and a second gate array driving circuit. However, OH discloses a display device (Fig. 1; display device 1000), wherein the driving circuit comprises: a light-emitting array driving circuit (emission driver 500), electrically connected to the pixel circuit and configured to provide a light-emitting control signal (emission control signal EM) to the pixel circuit; a first gate array driving circuit (gate driver 200), electrically connected to the pixel circuit and configured to provide a first gate driving signal (gate driving signal S1) to the pixel circuit; and a second gate array driving circuit (gate driver 300), electrically connected to the pixel circuit and configured to provide a second gate driving signal (gate driving signal S2) to the pixel circuit. Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from OH to the display device of NA in view of WANG. The combination/motivation would be to provide scanning driving circuits for emission signal and gate signal control of a pixel circuit.
Regarding claim 18, NA in view of WANG and further in view of OH discloses a display device (e.g., OH, Fig. 1; display device 1000), comprising the driving circuit according to claim 15.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YUZHEN SHEN whose telephone number is (571)272-1407. The examiner can normally be reached on Monday-Thursday 8:30am-5:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YUZHEN SHEN/Primary Examiner, Art Unit 2623
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