DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
2. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
3. Claim(s) 1-3, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sakariya et al. (US 2018/0182279 A1, hereinafter referred as “Sakariya”).
Regarding claim 1, Sakariya discloses a global scanning method with offset (¶0084 discloses output select module 1915 and routing to a group of display elements may be referred to as a timing offset circuit; and ¶0091 discloses FIG. 23A is schematic timing diagram 2300 of an emission pattern according to one embodiment of the disclosure where each row starts emitting at different times), comprising:
dividing multiple rows of micro-LEDs (¶0011 discloses array of micro LEDs) of at least one micro-display panel into a plurality of display groups, each of the plurality of display groups comprising one or more rows of micro-LEDs (¶0058 discloses the number of rows in an emission group may be adjustable from a single row to the full panel);
determining a scanning offset duration between display groups adjacent in terms of scanning time (¶0084 discloses output select module 1915 and routing to a group of display elements may be referred to as a timing offset circuit; and ¶0091 discloses emission controller may assert output select signal to cause (e.g., adjacent) display elements to begin emitting light at different times); and
scanning sequentially the plurality of display groups of the at least one micro-display panel according to the scanning offset duration (¶0078 discloses each successive row or each successive block of rows may emit with a staggered phase from the previous row or the previous block of rows, respectively).
Regarding claim 2, Sakariya discloses the global scanning method with offset according to claim 1, wherein one or more rows of micro-LEDs scanned using the same group of scanning signals are divided into a display group (¶0080 discloses Start logic: a shift register 1503 with a latch 1504 may generate a pulse for a group (e.g., rows)).
Regarding claim 3, Sakariya discloses the global scanning method with offset according to claim 1, wherein each display group comprises multiple rows of micro-LEDs (¶0058 discloses the number of rows in an emission group may be adjustable from a single row to the full panel), and the multiple rows of micro-LEDs are adjacent or not adjacent in positions (¶0078 discloses each successive block of rows may emit with a staggered phase from …the previous block of rows).
Regarding claim 20, Sakariya discloses a micro-display system, comprising: one or more micro-display panels (¶0011 discloses an array of micro LEDs in the active area and electrically connected to the array of micro driver chips); and a controller (¶0011 discloses an emission controller) configured to execute the global scanning method with offset (¶0084 discloses output select module 1915 and routing to a group of display elements may be referred to as a timing offset circuit; and ¶0091 discloses FIG. 23A is schematic timing diagram 2300 of an emission pattern according to one embodiment of the disclosure where each row starts emitting at different times) according to claim 1.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claim(s) 4 and 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakariya in view of Song et al. (US 2023/0007743 A1, hereinafter referred as “Song”).
Regarding claim 4, Sakariya doesn’t disclose the global scanning method with offset according to claim 1, wherein the scanning offset duration between display groups adjacent in terms of scanning time is determined according to a scanning period, a number of display groups, and a duty cycle of a frame of image data.
However, in the same field of endeavor, Song discloses wherein the scanning offset duration between display groups adjacent in terms of scanning time is determined according to a scanning period, a number of display groups (¶0053 discloses image processor may produce a plurality of groups, where each group of the plurality of groups can correspond to a duty cycle range; and ¶0054 discloses the duty cycle ranges may be defined based on the number of groups), and a duty cycle of a frame of image data.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sakariya in order to give the controller a controllable way to partition pixels having different on-times into groups that can be phase shifted differently.
Regarding claim 9, Sakariya doesn’t disclose the global scanning method with offset according to claim 1, wherein an interval between scanning start time points of two display groups adjacent in terms of scanning time equals the scanning offset duration.
However, in the same field of endeavor, Song discloses wherein an interval between scanning start time points of two display groups adjacent in terms of scanning time equals the scanning offset duration (¶0077 discloses each group may have a unique shift. The shift for a group may be determined based on the delay increment 708 and a number of the group).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sakariya in order to prevent pixels having similar duty cycles from turning on and off at substantially the same time.
Regarding claim 10, Sakariya doesn’t disclose the global scanning method with offset according to claim 1, wherein scanning sequentially the plurality of display groups of the at least one micro-display panel according to the scanning offset duration comprises: first scanning a first display group, then scanning a second display group after a first scanning offset duration, and so on, scanning M-th display group after (M−1)-th scanning offset duration, wherein M is a number of the plurality of display groups, and M is a positive integer.
However, in the same field of endeavor, Song discloses first scanning a first display group (¶0077 discloses for example, the shift for the first group 710 may be determined by multiplying the delay increment 708 by 0, thereby having no shift applied to the pixels in the first group), then scanning a second display group after a first scanning offset duration, and so on (¶0077 discloses the shift for the second group 712 may be determined by multiplying the delay increment 708 by 1, and so forth for the remaining groups), scanning M-th display group after (M−1)-th scanning offset duration, wherein M is a number of the plurality of display groups, and M is a positive integer (¶0077 discloses the shift for a group may be determined based on the delay increment 708 and a number of the group… accordingly, the shift for a group may be defined by the equation s=td′*(Gx−1), where s is the shift for a group, td′ is the delay increment to be utilized for the shift (i.e., the delay increment 708 in the illustrated embodiment), and (ix is the group number).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sakariya so that the final delayed display group completes its duty cycle defined emission before expiration of the scanning, thereby maintaining the intended brightness of each display group.
6. Claim(s) 5-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakariya in view of Song, and in further view of Seissegger et al. (US 2015/0327340 A1, hereinafter referred as “Seissegger”).
Regarding claim 5, Sakariya doesn’t disclose the global scanning method with offset according to claim 4, wherein the scanning period T, and the number of display groups M, the scanning offset duration t, and the duty cycle D of the frame of image data satisfy the following relationship: T ≥ (D*T) + t*(M-1) wherein M is a positive integer, t, T, and D are positive numbers, and the scanning offset duration t and the duty cycle D are fixed values.
However, in the same field of endeavor, Song at ¶0077 discloses the shift for each group may be determined by multiplying the delay increment 708 by one less than the group number for the group… the shift for a group may be defined by the equation s=td′*(Gx−1).
Further, in the same field of endeavor, Siessegger at ¶0022 discloses after the delay time T has lapsed, the output of the driver delivers current to the LEDs for a time period of D*TLED, where D is the duty cycle and TLED is the PWM period. The delay time T is a random time which is equally/uniformly distributed between 0 and TLED−D1*TLED.
Accordingly, for the Mth group: (M-1)*t ≤ T-D*T, which can be rewritten to T ≥ (D*T) + t*(M-1).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sakariya so that the final delayed display group completes its duty cycle defined emission before expiration of the scanning, thereby maintaining the intended brightness of each display group.
Regarding claim 6, Sakariya as modified doesn’t disclose the scanning method with offset according to claim 5, wherein the larger the duty cycle, the greater the number of display groups, the smaller the maximum value of the scanning offset duration.
However, in the same field of endeavor, Siessegger discloses wherein the larger the duty cycle, …, the smaller the maximum value of the scanning offset duration (¶0022 discloses the delay time T is a random time which is equally/uniformly distributed between 0 and TLED−D1*TLED, which can be expressed as tmax=T*(1-D), so as D increases, tmax necessarily decreases). Siessegger also discloses the greater the number of display groups, the smaller the maximum value of the scanning offset duration (¶0059 discloses it is desirable for the phase shift between channels to be 360°/N, where N equals the number of channels, in other words, t=360°/N, and as N increases, t decreases).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sakariya for the purpose of ensuring all display groups complete their respective emission intervals within the prescribed scanning, thereby maintaining the intended duty cycle.
Regarding claim 7, Sakariya discloses the global scanning method with offset according to claim 5, wherein the duty cycle D is less than 1 (¶0085 discloses a 240 Hz emission cycle with 1% emission duty, i.e., 0.01 emission duty cycle).
7. Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakariya in view of Seissegger.
Regarding claim 8, Sakariya doesn’t disclose the global scanning method with offset according to claim 1, wherein the scanning duration of each display group is the same.
However, in the same field of endeavor, Siessegger discloses wherein the scanning duration of each display group is the same (¶0056 discloses constant duty cycles of D1=D2=D3=D4=50% and D1=D2=D3=D4=12.5% are used in FIGS. 5 and 6, respectively).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sakariya in order to preserve consistent duty cycle controlled brightness among the display groups while allowing phased timing to distribute their emission over the scanning.
8. Claim(s) 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakariya in view of Chaji et al. (US 2019/0066567 A1, hereinafter referred as “Chaji”).
Regarding claim 11, Sakariya doesn’t disclose the global scanning method with offset according to claim 2, wherein a group of scanning signals comprises multiple bits of data.
However, in the same field of endeavor, Chaji discloses wherein a group of scanning signals comprises multiple bits of data (¶0069 discloses the drive current representing the desired output luminance grayscale is quantized by an N-bit digital signal).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sakariya in order to provide digital brightness and time control.
Regarding claim 12, Sakariya doesn’t disclose the global scanning method with offset according to claim 11, wherein during scanning, a group of scanning signals is transmitted by a plurality of signal lines.
However, in the same field of endeavor, Chaji discloses wherein during scanning, a group of scanning signals is transmitted by a plurality of signal lines (¶0042 discloses the gate/clock-drivers 130a, 130b provide control and clock signals to rows of pixel 150 elements; ¶0043 discloses the controller 162 within each pixel element 150 supervises the flow of data in the memory 164 devices based on the command signals on the WR (write) 161b and CLK (clock) 161a lines).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sakariya in order to increase data-transfer throughput during display programming.
9. Claim(s) 13-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakariya in view of Chaji and still in further view of Cok et al. (US 2017/0061867 A1, hereinafter referred as “Cok”).
Regarding claim 13, Sakariya as modified doesn’t disclose the global scanning method with offset according to claim 12, wherein each signal line transmits one bit of data.
However, in the same field of endeavor, Cok discloses wherein each signal line transmits one bit of data (¶0136 discloses the digit memory 24 is a one-bit memory, for example a digital latch or D flip-flop; and ¶0139 disclose the three D flip-flops are arranged in parallel and the three red, green, and blue digit values 25 are loaded in parallel at the same time, for example with a common clock signal 23, into the three D flip-flops).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Sakariya for the purpose of faster loading by parallel transmission.
Regarding claim 14, Sakariya discloses the global scanning method with offset according to claim 13, wherein under a case that a display group comprises multiple rows of micro-LEDs (¶0058 discloses the number of rows in an emission group may be adjustable from a single row to the full panel).
Sakariya doesn’t disclose the group of scanning signals comprises a plurality of sub-signal groups, and each sub-signal group comprises multiple bits of data.
However, in the same field of endeavor, Chaji discloses the group of scanning signals comprises a plurality of sub-signal groups, and each sub-signal group comprises multiple bits of data (¶0046 discloses the first bit of each pixel is loaded into the boundary registers 216, and thereafter the data is transferred to the respective pixel memory (reg_pixel) 218a, 218b. This operation continues until all of the data is loaded into the pixels of the row, and then is repeated for the next row; and ¶0069 discloses the drive current representing the desired output luminance grayscale is quantized by an N-bit digital signal).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Sakariya so that each row can be programmed separately using the same data loading circuitry, while reducing temporary storage and simplifying the data path.
Regarding claim 15, Sakariya discloses the global scanning method with offset according to claim 13, wherein under a case that a display group comprises one row of micro-LEDs (¶0058 discloses the number of rows in an emission group may be adjustable from a single row to the full panel).
Sakariya doesn’t disclose during scanning, an interval exists between transmission start time points of two bits of data adjacent in transmission times.
However, in the same field of endeavor, Chaji discloses during scanning, an interval exists between transmission start time points of two bits of data adjacent in transmission times (¶0070 discloses N-bit serial data is then clocked in and programmed in the shift register; ¶0046 discloses the operation can load the first bit of the data for the entire row (or column or entire display) and then move to the next bit; where successive clocked serial bits necessarily have distinct clock defined transmission start times).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Sakariya so that each bit is received into the proper register position before the next bit is transmitted.
Regarding claim 16, Sakariya discloses the global scanning method with offset according to claim 14, wherein under the case that a display group comprises multiple rows of micro-LEDs (¶0058 discloses the number of rows in an emission group may be adjustable from a single row to the full panel).
Sakariya doesn’t disclose during scanning, an interval exists between the transmission start time points of two bits of data adjacent in transmission times in each sub-signal group.
However, in the same field of endeavor, Chaji discloses during scanning, an interval exists between the transmission start time points of two bits of data adjacent in transmission times in each sub-signal group (¶0070 discloses N-bit serial data is then clocked in and programmed in the shift register; ¶0046 discloses the operation can load the first bit of the data for the entire row (or column or entire display) and then move to the next bit; where successive clocked serial bits necessarily have distinct clock defined transmission start times).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Sakariya so that each bit is received into the proper register position before the next bit is transmitted.
Regarding claim 17, Sakariya as modified doesn’t disclose the global scanning method with offset according to claim 15, wherein the interval between the transmission start time points of two bits of data adjacent in transmission times equals a pulse length during the transmission of the previous bit of data.
However, in the same field of endeavor, Cok discloses wherein the interval between the transmission start time points of two bits of data adjacent in transmission times equals a pulse length during the transmission of the previous bit of data (¶0139 discloses the digit memories 24 are sequentially connected in a serial three-bit D flip-flop shift register operated by a clock signal 23. In this embodiment, the red, green, and blue digit values 25 can be sequentially shifted into the flip-flops; for a contiguous synchronous serial stream, each bit occupies its clock defined transmission interval until the next bit begins).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Sakariya in order to conduct efficient, continuous bit transmission with deterministic timing.
Regarding claim 18, Sakariya as modified doesn’t disclose the global scanning method with offset according to claim 17, wherein the pulse length of each bit of data increases sequentially.
However, in the same field of endeavor, Cok discloses wherein the pulse length of each bit of data increases sequentially (¶0135 discloses successive binary bit periods of one, two, four, and eight bit periods; and the bit periods increase by successive powers of two for successive bits in numbers with successively more bits, for example, 8, 9, 10, 11, 12, 13, 14, 15, and 16 bits).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Sakariya so that successively more significant bits gives each bit its proper binary weight in the displayed brightness.
10. Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakariya in view of Song, in further view of Trisnadi et al. (US 2022/0075199 A1, hereinafter referred as “Trisnadi”).
Regarding claim 19, Sakariya discloses the global scanning method with offset according to claim 10, each… display panel comprising a plurality of display groups (¶0058 discloses the number of rows in an emission group may be adjustable from a single row to the full panel).
Sakariya doesn’t disclose wherein the at least one micro-display panel comprises a plurality of micro-display panels.
However, in the same field of endeavor, Trisnadi discloses wherein the at least one micro-display panel comprises a plurality of micro-display panels (¶0306 discloses the micro-displays 1030a, 1030b, 1030c may be micro-LED panels).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Sakariya so that separate monochrome micro-displays can output different color components, and their light is combined to form a full color image.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRIYANK J SHAH whose telephone number is (571)270-3732. The examiner can normally be reached on 10:00 - 6:00 M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ghebretinsae, Temesghen can be reached on (571) 272-3017. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PRIYANK J SHAH/Primary Examiner, Art Unit 2626
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