DETAILED ACTION
This action is responsive to 02/06/2026.
Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-3 and 8-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-13 of U.S. Patent No. 12,575,273 B2, hereinafter 273 patent. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims in the 395 Patent anticipate the claims in the instant application, and, therefore, a patent to the claims in the instant application would improperly extend the right to exclude granted by a patent to the claims in the instant application should the instant application issue as a patent. The claims are compared with each other in the following:
Claim Set A: US Patent 12,575,273 B2
Claim Set B: US App. 19/532,754
1. A display device, comprising: a substrate including an active area and a non-active area that is at least partially around the active area, the active area including a first active area and a second active area partially surrounded by the first active area;
1. A display device, comprising: a substrate including an active area in which an image is displayed, and a non-active area in which an image is not displayed, the active area including a first active area and a second active area partially surrounded by the first active area;
a thin film transistor disposed on the substrate in the active area and including an active layer, a gate electrode, a source electrode, and a drain electrode;
4. The display device according to claim 1, further comprising: a thin film transistor disposed on the substrate in the active area, and including an active layer, a gate electrode, a source electrode, and a drain electrode;
a first interlayer insulating layer disposed on the gate electrode;
a first interlayer insulating layer disposed on the gate electrode;
a second interlayer insulating layer disposed on the first interlayer insulating layer, the source electrode and the drain electrode disposed on the second interlayer insulating layer;
a second interlayer insulating layer disposed on the first interlayer insulating layer, the source electrode and the drain electrode disposed on the second interlayer insulating layer;
a first planarization layer disposed on the source electrode, the drain electrode and the second interlayer insulating layer;
a first planarization layer disposed on the source electrode, the drain electrode and the second interlayer insulating layer;
a connection electrode disposed on the first planarization layer and electrically connected to the drain electrode of the thin film transistor;
a second planarization layer disposed on the first planarization layer; and
a second planarization layer disposed on the first planarization layer and the connection electrode;
a light emitting diode disposed on the second planarization layer, and including a first electrode, an emission structure, and a second electrode; and an encapsulation unit disposed on the light emitting diode.
a conductive layer disposed on the first interlayer insulating layer in the active area, the conductive layer disposed between the first interlayer insulating layer and the second interlayer insulating layer;
a sensor in the second active area but not the first active area;
2. The display device according to claim 1, further comprising: at least one sensor in the second active area but not the first active area,
a first high potential voltage line that supplies a first high potential voltage to a plurality of first pixels in the first active area;
a first high potential voltage line that supplies a first high potential voltage to a plurality of first pixels in the first active area;
a first power line that is connected to the first high potential voltage line and includes a plurality of first sub power lines extending in a first direction in the first active area and a plurality of second sub power lines extending in a second direction that intersects the first direction in the first active area,
a first power line that is connected to the first high potential voltage line and includes a plurality of first sub power lines extending in a first direction in the first active area and a plurality of second sub power lines extending in a second direction that is different from the first direction in the first active area;
3. The display device according to claim 1, wherein the first direction and the second direction are perpendicular to each other.
the plurality of second sub power lines electrically connected to the plurality of first sub power lines;
a second high potential voltage line that supplies a second high potential voltage to a plurality of second pixels in the second active area;
a second high potential voltage line that supplies a second high potential voltage to a plurality of second pixels in the second active area;
a second power line that is connected to the second high potential voltage line and extends in the first direction such that the second power line overlaps the sensor in
a plan view of the display device; and
and a second power line that is connected to the second high potential voltage line and extends to the second active area,
a low potential voltage line that supplies a voltage to at least one of cathode electrodes of light emitting elements included in the plurality of first pixels in the first active area or cathode electrodes of light emitting elements included in the plurality of second pixels in the second active area, the low potential voltage line
disposed between the second high potential voltage line and the first active area in a plan view of the display device,
19. The display device according to claim 1, further comprising: a low potential voltage line that supplies a voltage to at least one of cathode electrodes of light emitting elements included in the plurality of first pixels in the first active area or cathode electrodes of light emitting elements included in the plurality of second pixels in the second active area, wherein a side of the non-active area includes a first portion in which the second power line extends in the first direction and second and third portions on both sides of the first portion in a plan view of the display device, and
wherein a portion of the second power line overlaps the sensor in the plan view without intersecting a power line that extends in the second direction,
20. The display device according to claim 2, wherein a portion of the second power line overlaps a sensor disposed in the second active area in a plan view of the display device without intersecting a power line that extends in the second direction.
wherein the first high potential voltage line and the second high potential voltage line are electrically isolated from each other,
wherein a side of the non-active area includes a first portion in which the second power line extends in the first direction and second and third portions on both sides of the first portion in a plan view of the display device,
wherein the low potential voltage line is disposed between the second high potential voltage line and the first active area in at least a portion of each of the second and third portions, and is opened in the first portion to be non-overlapping the second power line and intersecting the first direction in which the second power line extends,
19. … wherein the low potential voltage line is disposed between the second high potential voltage line and the first active area in at least a portion of each of the second and third portions, and is opened in the first portion to be non-overlapping the second power line and intersecting the first direction in which the second power line extends.
wherein the second active area includes an area including the sensor and an auxiliary area between the area including the sensor and the second high potential voltage line,
wherein the active area further includes an auxiliary area between the second active area and the second high potential voltage line,
wherein a second sub power line from the plurality of second sub power lines that is adjacent to the second high potential voltage line continuously extends from a first portion of the first active area across the auxiliary area to a second portion of the first active area such that the second sub power line intersects the second power line in the auxiliary area, and remaining second sub power lines from the plurality of second sub power lines do not intersect the second power line.
wherein at least one second sub power line of the plurality of second sub power lines continuously extends from a first portion of the first active area across the auxiliary area to a second portion of the first active area such that the at least one second sub power line intersects the second power line in the auxiliary area.
2. The display device according to claim 1, wherein the sensor is a camera in the second active area.
2. The display device according to claim 1, further comprising: at least one sensor in the second active area but not the first active area, wherein the at least one sensor includes a camera in the second active area.
3. The display device according to claim 1, wherein a number of first pixels per unit area from the plurality of first pixels is greater than a number of second pixels per unit area from the plurality of second pixels.
8. The display device according to claim 1, wherein a number of first pixels per unit area from the plurality of first pixels is greater than a number of second pixels per unit area from the plurality of second pixels.
4. The display device according to claim 3, wherein the first high potential voltage supplied to the plurality of first pixels is less than the second high potential voltage supplied to the plurality of second pixels.
9. The display device according to claim 8, wherein the first high potential voltage supplied to the plurality of first pixels is less than the second high potential voltage supplied to the plurality of second pixels.
5. The display device according to claim 4, wherein a maximum luminance of the first pixels per unit area in the first active area is equal to a maximum luminance of the second pixels per unit area in the second active area.
10. The display device according to claim 9, wherein a maximum luminance of the first pixels per unit area in the first active area is equal to a maximum luminance of the second pixels per unit area in the second active area.
6. The display device according to claim 1, wherein the first active area includes a first area comprising first pixels from the plurality of first pixels, and the second active area includes a second area comprising one second pixel from the
plurality of second pixels, wherein an area of the first area is a same as an area of the second area.
11. The display device according to claim 1, wherein the first active area includes a first area comprising first pixels from the plurality of first pixels, and the second active area includes a second area comprising one second pixel from the plurality of second pixels, wherein an area of the first area is [[a]] same as an area of the second area.
7. The display device according to claim 6, wherein each of the first pixels in the first area has a same maximum luminance that is less than a maximum luminance of the one second pixel in the second area.
12. The display device according to claim 11, wherein each of the first pixels in the first area has [[a]] same maximum luminance that is less than a maximum luminance of the one second pixel in the second area.
8. The display device according to claim 7, wherein a sum of the maximum luminance of the first pixels in the first area is equal to the maximum luminance of the one second pixel in the second area.
13. The display device according to claim 12, wherein a sum of the maximum luminance of the first pixels in the first area is equal to the maximum luminance of the one second pixel in the second area.
9. The display device according to claim 1, wherein the non-active area includes:
a first non-active area including a pad unit, the first non-active area extending from a first side of the active area that extends in a first direction;
14. The display device according to claim 1, wherein the non-active area includes: a first non-active area including a pad unit, the first non-active area extending from a first side of the active area that extends in a first direction;
a second non-active area extending from a third side and a fourth side of the active area, the third side and the fourth side extending in a second direction that intersects the first direction; and
a second non-active area extending from a third side and a fourth side of the active area, the third side and the fourth side extending in a second direction that intersects the first direction; and
a third non-active area extending from a fifth side of the active area that extends in the first direction and is parallel to the first side of the active area, wherein a part of the first high potential voltage line is in
the first non-active area, and a part of the second high potential voltage line encloses the active area in the first non-active area, the second non-active area, and the third non-active area.
a third non-active area extending from a fifth side of the active area that extends in the first direction and is parallel to the first side of the active area, wherein a part of the first high potential voltage line is in the first non-active area, and a part of the second high potential voltage line encloses the active area in the first non-active area, the second non-active area, and the third non-active area.
10. The display device according to claim 9, wherein the first high potential voltage line includes a first high potential voltage link line in the first non-active area and the first power line in the first active area, and the second high potential voltage line includes the second power line in the
second active area and a second high potential voltage link line in the first non-active area, the second non-active area,
and the third non-active area.
15. The display device according to claim 14, wherein the first high potential voltage line includes a first high potential voltage link line in the first non-active area and the first power line in the first active area, and the second high potential voltage line includes the second power line in the second active area and a second high potential voltage link line in the first non-active area, the second non-active area, and the third non-active area.
11. The display device according to claim 9, further comprising: a gate driving circuit between the second high potential voltage line and the active area in the second non-active area.
16. The display device according to claim 14, further comprising: a gate driving circuit between the second high potential voltage line and the active area in the second non-active area.
12. The display device according to claim 1, wherein the second high potential voltage line receives the second high
potential voltage from a data driving circuit or a power management integrated circuit.
17. The display device according to claim 1, wherein the second high potential voltage line receives the second high potential voltage from a data driving circuit or a power management integrated circuit.
13. The display device according to claim 1, wherein both of the first high potential voltage line and the second high potential voltage line are directly connected to a power management integrated circuit.
18. The display device according to claim 1, wherein both of the first high potential voltage line and the second high potential voltage line are directly connected to a power management integrated circuit.
From the comparison above, it is clear that all the elements of the aforementioned claims in the instant application are found in the aforementioned claims of the 273 patent, the difference being that the 273 patent includes more elements and is thus much more specific. Therefore, the invention in the 273 patent is in effect a “species” of the generic invention in the instant application. It has been held that a generic invention is “anticipated” by the “species” (see In re Goodman, 29 USPQ2d 2020 (fed. Cir. 1993), In re Slayter, 276 F.2d 408,411,125 USPQ 345, 347 (CCPA 1960)-see MPEP 2131.02), since a later patent to a genus would, necessarily, extend the right to exclude granted by an earlier patent directed to a species or sub-genus (see MPEP 804(II)(B)(1)).
Claims 4-5 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of the 273 patent in view of Zhang et al. (US Pub. 2022/0208910), hereinafter Zhang.
Regarding claim 4, the 273 patent discloses every element but for the limitations reciting “a connection electrode disposed on the first planarization layer and electrically connected to the drain electrode of the thin film transistor; a second planarization layer disposed on the connection electrode; a light emitting diode disposed on the second planarization layer, and including a first electrode, an emission structure, and a second electrode; and an encapsulation unit disposed on the light emitting diode.”
Zhang teaches a connection electrode (see fig. 2, which is a cross-sectional view of A-A in fig. 1, and which illustrates a second transparent part 400 (equated to claimed connection electrode)) disposed on the first planarization layer (the second transparent part is formed on a second insulating layer (see [0138]-[0139]) and electrically connected to the drain electrode of the thin film transistor (see fig. 2-second transparent part 400 is connected to one terminal (in this case source 213) of transistor 210); a second planarization layer disposed on the connection electrode (a third insulating layer is formed on a side of the second transparent part away from the second insulating layer-see fig. 22, step S06, also fig. 2); a light emitting diode disposed on the second planarization layer (see fig. 2), and including a first electrode (first electrode 500-see fig. 2 and [0044]), an emission structure (light-emitting layer 800-see fig. 2 and [0049]), and a second electrode (second electrode 900-see fig. 2 and [0049]); and an encapsulation unit disposed on the light emitting diode (the display panel may also include an encapsulation layer located on a side of the second electrode layer 900-see fig. 2 and [0050]).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the wiring structure of Zhang with invention in the 273 patent, in which a connection electrode is used to connect a pixel electrode of a light-emitting element with a drain/source of a light-emitting control transistor, as taught by Zhang, which constitutes combining prior art elements according to known methods to yield predictable results.
Regarding claim 5, Zhang is further relied upon to teach wherein the thin film transistor is electrically connected to the first electrode of the light emitting diode via the connection electrode (see fig. 2-first electrode 500 of the light emitting diode is coupled to source 213 of the transistor 210 via the second transparent part 400), and wherein the first electrode in the second active area includes at least one of a transparent conductive layer, an opaque conductive layer or a multi-layer thereof (see fig. 2 and [0044]).
Claims 6 is/are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 41 of the 273 patent in view of Zhang and Son et al. (US Pub. 2018/0366586), hereinafter Son.
Regarding claim 6, the 273 patent in view of Zhang does not appear to expressly teach wherein the active layer of the thin film transistor includes at least one of polysilicon, amorphous silicon, or oxide semiconductor.
Son, for example in fig. 3A and [0094]-[0095] and [0099], teaches a first TFT 210 connected to a light emitting display element 400 via a connection electrode 217 disposed on a first planarization layer 118, wherein a first active layer 211 of the first TFT 210 includes polycrystalline silicon (see [0094]).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Son with inventions in the 273 patent and Zhang by using a transistor of any commonly known active area material, such polysilicon or oxide semiconductor, as taught by Son, which constitutes choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success.
Claims 7 is/are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 41 of the 273 patent in view of Zhang and Lee et al. (US Patent 11,626,467), hereinafter Lee.
Regarding claim 7, the 273 patent in view of Zhang does not appear to expressly teach wherein the encapsulation unit includes a first inorganic encapsulation layer, a second inorganic encapsulation layer and an organic encapsulation layer therebetween.
Lee, in for example, figs. 7A-7B teaches a thin film encapsulation layer TFE that includes a first inorganic layer 71, an organic layer 72, and a second inorganic layer 73 disposed on a light emitting element layer DP-EDL.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Lee with inventions in the 273 patent and Zhang such that the encapsulation layer may an organic layer sandwiched between two inorganic layers, as taught by Lee, which constitutes combining prior art elements according to known methods to yield predictable results.
Conclusion
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/SARDIS F AZONGHA/Primary Examiner, Art Unit 2627
