DETAILED ACTION
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Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2 and 8 – 18 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhao et al. (US 2023/0196970).
As to claim 1, Zhao discloses a scan driving circuit (shift register of fig. 3), comprising:
an input module (trigger write module 102 of figs. 3 and 4), configured to generate a first control signal (signal on node at the output of 102 of figs. 3 and 4) at a first node (node at the output of 102 of figs. 3 and 4);
a level transmission module (Power introduction sub-module 103 of fig. 3), configured to generate a second control signal (signal output by the Power introduction sub-module of fig. 3) at a third node (output terminal of the Power introduction sub-module of fig. 3);
an output module (Output adjustment module 101 of fig. 3), comprising a first control terminal (node N2 of figs. 3 and 4) and a second control terminal (node N1 of fig. 3), wherein
the first control terminal (node N2 of figs. 3 and 4) is configured to electrically connect the input module (trigger write module 102 of figs. 3 and 4) , the second control terminal (node N1 of fig. 3) is configured to electrically connect the level transmission module (Power introduction sub-module 103 of fig. 3), so as to respond to the first control signal (signal on node at the output of 102 of figs. 3 and 4) and the second control signal (signal output by the Power introduction sub-module of fig. 3) to generate a corresponding scan output signal (OUT of fig. 3);
a first isolation module (First adjustment sub-module 104 of fig. 3), located between the second control terminal (node N1 of fig. 3) of the output module (Output adjustment module 101 of fig. 3) and the third node (output terminal of the Power introduction sub-module of fig. 3).
As to claim 2 (dependent on 1), Zhao discloses the scan driving circuit (shift register of fig. 3), wherein
the input module (trigger write module 102 of figs. 3 and 4) samples a scan input signal (IN of fig. 4) at least in response to a third clock signal (CLK1 of fig. 3) to generate the first control signal (signal on node at the output of 102 of figs. 3 and 4) at the first node (node at the output of 102 of figs. 3 and 4);
the level transmission module (Power introduction sub-module 103 of fig. 3) samples a first level signal (VGL of fig. 4) in response to a first clock signal (CLK2 of fig. 3) and a second clock signal (CLK3 of fig. 4) to generate the second control signal (signal output by the Power introduction sub-module of fig. 3) at the third node (output terminal of the Power introduction sub-module of fig. 3);
wherein
the first clock signal (CLK2 of fig. 3), the second clock signal (CLK3 of fig. 4), and the third clock signal (CLK1 of fig. 3) have the same period (fig. 6), a phase difference between the second clock signal (CLK3 of fig. 4) and the first clock signal (CLK2 of fig. 3) is half a period (fig. 6), and a rising edge of the third clock signal (CLK1 of fig. 3) occurs at or after a falling edge of the second clock signal (CLK3 of fig. 4).
As to claim 8 (dependent on 1), Zhao discloses the scan driving circuit (shift register of fig. 3), further comprising:
a second isolation module (M16 of fig. 4), disposed between the first control terminal (terminal at node at the output of 102 of figs. 3 and 4) of the output module (Output adjustment module 101 of fig. 3) and the first node (node at the output of 102 of figs. 3 and 4).
As to claim 9 (dependent on 1), Zhao discloses the scan driving circuit (shift register of fig. 3), wherein
the input module (trigger write module 102 of figs. 3 and 4) comprises:
a first input unit (1021 of fig. 4) configured to sample a scan input signal (IN of fig. 4) in response to a third clock signal (CLK1 of fig. 3).
As to claim 10 (dependent on 9), Zhao discloses the scan driving circuit (shift register of fig. 3), wherein
the input module (trigger write module 102 of figs. 3 and 4) further comprises a second input unit (1022 of fig. 4), the second input unit (1022 of fig. 4) being connected in series between the first input unit (1021 of fig. 4) and the first node (node at the output of 102 of figs. 3 and 4), and the second input unit (1022 of fig. 4) being configured to transmit the scan input signal (IN of fig. 4) output from the first input unit (1021 of fig. 4) as the first control signal (signal on node at the output of 102 of figs. 3 and 4) to the first node (node at the output of 102 of figs. 3 and 4) in response to a first clock signal (CLK2 of fig. 3).
As to claim 11 (dependent on 10), Zhao discloses the scan driving circuit (shift register of fig. 3), wherein
the first input unit (1021 of fig. 4) comprises a fourteenth transistor (M3 of fig. 4), a first terminal of the fourteenth transistor (M3 of fig. 4) is connected to a supply terminal of the scan input signal (IN of fig. 4), a control terminal of the fourteenth transistor (M3 of fig. 4) is connected to a supply terminal of the third clock signal (CLK1 of fig. 3), and a second terminal of the fourteenth transistor (M3 of fig. 4) is connected to the first node (node at the output of 102 of figs. 3 and 4).
As to claim 12 (dependent on 11), Zhao discloses the scan driving circuit (shift register of fig. 3), wherein
the second input unit (1022 of fig. 4) comprises a first transistor (M4 of fig. 1), a first terminal of the first transistor (M4 of fig. 1) is connected to the second terminal of the fourteenth transistor (M3 of fig. 4), a control terminal of the first transistor (M4 of fig. 1) is connected to a supply terminal of the first clock signal (CLK2 of fig. 3), and a second terminal of the first transistor (M4 of fig. 1) is connected to the first node (node at the output of 102 of figs. 3 and 4).
As to claim 13 (dependent on 1), Zhao discloses the scan driving circuit (shift register of fig. 3), wherein
the input module (trigger write module 102 of figs. 3 and 4) comprises:
a first input unit (1021 of fig. 4) and a second input unit (1022 of fig. 4), the second input unit (1022 of fig. 4) being connected in series between the first input unit (1021 of fig. 4) and the first node (node at the output of 102 of figs. 3 and 4), the first input unit (1021 of fig. 4) being configured to sample a scan input signal (IN of fig. 4) in response to a first clock signal (CLK1 of fig. 3), and the second input unit (1022 of fig. 4) being configured to transmit the scan input signal (IN of fig. 4) output from the first input unit (1021 of fig. 4) as the first control signal (signal on node at the output of 102 of figs. 3 and 4) to the first node (node at the output of 102 of figs. 3 and 4) in response to a third clock signal (CLK2 of fig. 3).
As to claim 14 (dependent on 13), Zhao discloses the scan driving circuit (shift register of fig. 3), wherein
the first input unit (1021 of fig. 4) comprises a fourteenth transistor (M3 of fig. 4), the second input unit (1022 of fig. 4) comprises a first transistor (M4 of fig. 1), a first terminal of the fourteenth transistor (M3 of fig. 4) is connected to a supply terminal of the scan input signal (IN of fig. 4), a control terminal of the fourteenth transistor (M3 of fig. 4) is connected to a supply terminal of the first clock signal (CLK1 of fig. 3), a second terminal of the fourteenth transistor (M3 of fig. 4) is connected to a first terminal of the first transistor (M4 of fig. 1), a control terminal of the first transistor (M4 of fig. 1) is connected to a supply terminal of the third clock signal (CLK2 of fig. 3), and a second terminal of the first transistor (M4 of fig. 1) is connected to the first node (node at the output of 102 of figs. 3 and 4).
As to claim 15 (dependent on 1), Zhao discloses the scan driving circuit (shift register of fig. 3), further comprising:
a first control module (clock write module 110 of fig. 4) ,configured to sample a first clock signal (CLK2 of fig. 3) and transmit the first clock signal (CLK2 of fig. 3) to the level transmission module (Power introduction sub-module 103 of fig. 3) in response to a potential of the first node (node at the output of 102 of figs. 3 and 4).
As to claim 16 (dependent on 15), Zhao discloses the scan driving circuit (shift register of fig. 3), further comprising:
a second control module, connected to the first control terminal (terminal at node at the output of 102 of figs. 3 and 4) and an output terminal of the first control module (clock write module 110 of fig. 4), and configured to sample a second clock signal (CLK3 of fig. 4) and a second level signal (VGH of fig. 4) ,and transmit the second clock signal (CLK3 of fig. 4) and the second level signal (VGH of fig. 4) to the first control terminal (terminal at node at the output of 102 of figs. 3 and 4) in response to a potential of the output terminal of the first control module (clock write module 110 of fig. 4) and the potential of the first node (node at the output of 102 of figs. 3 and 4).
As to claim 17 (dependent on 1), Zhao discloses the scan driving circuit (shift register of fig. 3), wherein
a scan input signal (IN of fig. 4) is a scan output signal (OUT of fig. 3) output from a previous-stage scan driving circuit (shift register of fig. 7, were output of previous stage 100 is an input to next stage 100).
As to claim 18 (dependent on 1), Zhao discloses the scan driving circuit (shift register of fig. 3), wherein
the scan input signal (IN of fig. 4) is a scan start signal of the scan driving circuit (fig. 8).
As to claim 20, Zhao discloses a display panel, wherein
the display panel (fig. 7) comprises:
a scan driving circuit (shift registers of fig. 3 and 7) and a pixel unit coupled to each other [0048];
wherein
the scan driving circuit (shift register of fig. 3) is the scan driving circuit (shift register of fig. 3), comprising:
an input module (trigger write module 102 of figs. 3 and 4), configured to generate a first control signal (signal on node at the output of 102 of figs. 3 and 4) at a first node (node at the output of 102 of figs. 3 and 4);
a level transmission module (Power introduction sub-module 103 of fig. 3), configured to generate a second control signal (signal output by the Power introduction sub-module of fig. 3) at a third node (output terminal of the Power introduction sub-module of fig. 3);
an output module (Output adjustment module 101 of fig. 3), comprising a first control terminal (node N2 of figs. 3 and 4) and a second control terminal (node N1 of fig. 3), wherein
the first control terminal (node N2 of figs. 3 and 4) is configured to electrically connect the input module (trigger write module 102 of figs. 3 and 4) , the second control terminal (node N1 of fig. 3) is configured to electrically connect the level transmission module (Power introduction sub-module 103 of fig. 3), so as to respond to the first control signal (signal on node at the output of 102 of figs. 3 and 4) and the second control signal (signal output by the Power introduction sub-module of fig. 3) to generate a corresponding scan output signal (OUT of fig. 3);
a first isolation module (First adjustment sub-module 104 of fig. 3), located between the second control terminal (node N1 of fig. 3) of the output module (Output adjustment module 101 of fig. 3) and the third node (output terminal of the Power introduction sub-module of fig. 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhao in view of Gan et al. (US 2022/0114941).
As to claim 6 (dependent on 1), Zhao discloses the scan driving circuit (shift register of fig. 3), wherein
the output module (Output adjustment module 101 of fig. 3) comprises:
a first output unit (1012 of fig. 4), wherein
a control terminal of the first output unit (1012 of fig. 4) serves as the first control terminal (terminal at node at the output of 102 of figs. 3 and 4) of the output module (Output adjustment module 101 of fig. 3), a first terminal of the first output unit (1012 of fig. 4) receives a first level signal (VGL of fig. 4), a second terminal of the first output unit (1012 of fig. 4) is connected to an output terminal of the output module (OUT of the Output adjustment module 101 of fig. 3), and the first output unit (1012 of fig. 4) transmits the first level signal (VGL of fig. 4) as the scan output signal (OUT of fig. 3) to the output terminal of the output module (Output adjustment module 101 of fig. 3) in response to the first control signal (signal on node at the output of 102 of figs. 3 and 4);
a second output unit (1011 of fig. 4), wherein
a control terminal of the second output unit (1011 of fig. 4) serves as the second control terminal (node N1 of fig. 3) of the output module (Output adjustment module 101 of fig. 3), a first terminal of the second output unit (1011 of fig. 4) receives a third clock signal (CLK1 of fig. 3), a second terminal of the second output unit (1011 of fig. 4) is connected to the output terminal of the output module (OUT of Output adjustment module 101 of fig. 3), and the second output unit (1011 of fig. 4) transmits the third clock signal (CLK1 of fig. 3) as the scan output signal (OUT of fig. 3) to the output terminal of the output module (Output adjustment module 101 of fig. 3) in response to the second control signal (signal output by the Power introduction sub-module of fig. 3);
a coupling unit (capacitor C3 of fig. 4), wherein
a first terminal of the coupling unit (capacitor C3 of fig. 4) is connected to the control terminal of the second output unit (1011 of fig. 4), but does not explicitly disclose that
a second terminal of the coupling unit is connected to the second terminal of the second output unit.
In the same field of endeavor, Gan discloses a shift register circuit wherein a capacitor (Cbt2 of fig. 3) is coupled between gate of an output transistor (T21 of fig. 3) and the output of the shift register (RD(n) of fig. 3).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zhao and the teachings of Gan, such that the second terminal of the coupling unit was connected to the second terminal of the second output unit as disclosed by Gan, with motivation to provide a simple design choice alternative to lower transistor instability due to noise which was well known and would have only required a routine skill.
As to claim 7 (dependent on 6), Zhao discloses the scan driving circuit (shift register of fig. 3), wherein
the first output unit (1012 of fig. 4) comprises a tenth transistor (M2 of fig. 4), the second output unit (1011 of fig. 4) comprises a ninth transistor (M1 of fig. 4), the coupling unit comprises a third capacitor (capacitor C3 of fig. 4), a first terminal of the tenth transistor (M2 of fig. 4) is connected to a providing terminal of the first level signal (VGL of fig. 4), a control terminal of the tenth transistor (M2 of fig. 4) is connected to the first control terminal (terminal at node at the output of 102 of figs. 3 and 4), a second terminal of the tenth transistor (M2 of fig. 4) is connected to the output terminal of the output module (Output adjustment module 101 of fig. 3), a first terminal of the ninth transistor (M1 of fig. 4) is connected to a providing terminal of the third clock signal (CLK1 of fig. 3), a control terminal of the ninth transistor (M1 of fig. 4) is connected to a first terminal of the third capacitor and the second control terminal (node N1 of fig. 3), and a second terminal of the ninth transistor (M1 of fig. 4) is connected the output terminal of the output module (Output adjustment module 101 of fig. 3), but fails to disclose to the second terminal of the ninth transistor is connected to the second terminal of the third capacitor.
In the same field of endeavor, Gan discloses a shift register circuit wherein a capacitor (Cbt2 of fig. 3) is coupled between gate of an output transistor (T21 of fig. 3) and the second terminal of the ninth transistor (T211of fig. 3).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zhao and the teachings of Gan, such that the second terminal of the capacitor was connected to the second terminal of the output transistor as disclosed by Gan, with motivation to provide a simple design choice alternative to lower transistor instability due to noise which was well known and would have only required a routine skill.
Claim(s) 3 – 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhao in view of Yuan et al. (US 2025/0037632).
As to claim 3 (dependent on 1), Zhao discloses the scan driving circuit (shift register of fig. 3) according to claim 1, further comprising:
an inversion module (105 of fig. 4), wherein
the inversion module (105 of fig. 4) samples a second level signal (VGH of fig. 4) in response to the first control signal (signal on node at the output of 102 of figs. 3 and 4) at the first node (node at the output of 102 of figs. 3 and 4) and transmits the second level signal (VGH of fig. 4), but fails to disclose that
the inversion module samples a second level signal in response to a second clock signal, and transmits the second level signal to the third node.
In the same field of endeavor, Yuan discloses a gate driver circuit (TITLE) comprising a shift register (fig. 2), further comprising an inversion module (feedback module 90 of fig. 2), wherein
the inversion module (feedback module 90 of fig. 1) samples a second level signal (VGH of fig. 1) in response to the first control signal at the first node (signal on node P of fig. 1) and a second clock signal (CK of fig. 1) and transmits the second level signal (VGH of fig. 1) to the third node (node K of fig. 1).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zhao and the teachings of Yuan, such that the inversion module was provide as disclosed by Yuan, with motivation to alleviate the technical problem of small pulse amplitude of a gate drive signal (Yuan [0005]).
As to claim 4 (dependent on 3), Zhao discloses the scan driving circuit (shift register of fig. 3), wherein
the inversion module (105 of fig. 4) comprises:
an inversion unit (M7 of fig. 4), connected to the first node (gate connected to node at the output of 102 of figs. 3 and 4), configured to sample the second level signal (VGH of fig. 4) in response to the first control signal (signal on node at the output of 102 of figs. 3 and 4) at the first node (node at the output of 102 of figs. 3 and 4); but does not disclose
a phase delay unit , connected to the inversion unit and the third node, wherein
the phase delay unit performs phase delay on the second level signal output by the inversion unit in response to the second clock signal and transmits the second level signal to the third node.
In the same field of endeavor, Yuan discloses a gate driver circuit (TITLE) comprising a shift register (fig. 2), further comprising an inversion module (feedback module 90 of fig. 2), comprising
a phase delay unit (T4 of fig. 1), connected to the inversion unit (T5 of fig. 1) and the third node (node K of fig. 1), wherein
the phase delay unit performs phase delay on the second level signal (VGH of fig. 1) output by the inversion unit (T5 of fig. 1) in response to the second clock signal (CK of fig. 1) and transmits the second level signal to the third node (node K of fig. 1).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zhao and the teachings of Yuan, such that the inversion module was provide as disclosed by Yuan, with motivation to alleviate the technical problem of small pulse amplitude of a gate drive signal (Yuan [0005]).
As to claim 5 (dependent on 4), Zhao discloses the scan driving circuit (shift register of fig. 3), wherein
the inversion unit (second switch module 107 of fig. 4) comprises a sixth transistor (M7 of fig. 4), a first terminal of the sixth transistor (M7 of fig. 4) is connected to a providing terminal of the second level signal (VGH of fig. 4), a control terminal of the sixth transistor (M7 of fig. 4) is connected to the first node (node at the output of 102 of figs. 3 and 4), but does not disclose that
the phase delay unit comprises a fifteenth transistor, a second terminal of the sixth transistor is connected to a first terminal of the fifteenth transistor, a control terminal of the fifteenth transistor is connected to a providing terminal of the second clock signal, and a second terminal of the fifteenth transistor is connected to the third node.
In the same field of endeavor, Yuan discloses a gate driver circuit (TITLE) comprising a shift register (fig. 2), further comprising an inversion module (feedback module 90 of fig. 2), wherein
the phase delay unit comprises a fifteenth transistor (T4 of fig. 1), a second terminal of the sixth transistor (T5 of fig. 1) is connected to a first terminal of the fifteenth transistor (T4 of fig. 1), a control terminal of the fifteenth transistor (T4 of fig. 1) is connected to a providing terminal of the second clock signal (CK of fig. 1), and a second terminal of the fifteenth transistor is connected to the third node (K of fig. 1).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zhao and the teachings of Yuan, such that the inversion module was provide as disclosed by Yuan, with motivation to alleviate the technical problem of small pulse amplitude of a gate drive signal (Yuan [0005]).
Allowable Subject Matter
Claim 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 19, the Prior Art of record alone or in combination fails to disclose a driving method, applied to the scan driving circuit according to claim 1, comprising: in a first phase, providing the scan input signal as a first level state, and the first clock signal, a second clock signal and a third clock signal comprising the first level state, to generate a first control signal at a first node, and an output module generating a first scan output signal in response to the first control signal; in a second phase, providing the scan input signal as a second level state, providing the first clock signal and the third clock signal as the first level state, and the output module continuously generating the first scan output signal; in a third phase, providing the second clock signal as the first level state, to generate a second control signal at a third node, and the output module generating a second scan output signal in response to the second control signal; in a fourth phase, providing the scan input signal as the first level state, providing the second clock signal as the second level state, providing the first clock signal and the third clock signal as the first level state, to generate the first control signal at the first node, and the output module generating the first scan output signal in response to the first control signal; in a fifth phase, providing the second clock signal as the first level state, and the output module continuously generating the first scan output signal. (Emphasis Added.)
Conclusion
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/DMITRIY BOLOTIN/Primary Examiner, Art Unit 2623
