Prosecution Insights
Last updated: October 25, 2026
Application No. 19/571,820

TOUCH-PANEL-INTEGRATED DISPLAY DEVICE

Non-Final OA §103
Filed
Mar 19, 2026
Priority
Mar 21, 2025 — JP 2025-047510
Examiner
FARAGALLA, MICHAEL A
Art Unit
2624
Tech Center
2600 — Communications
Assignee
Sharp Display Technology Corporation
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
2y 3m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
872 granted / 1020 resolved
+23.5% vs TC avg
Moderate +8% lift
Without
With
+8.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
32 currently pending
Career history
1058
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
73.8%
+33.8% vs TC avg
§102
11.1%
-28.9% vs TC avg
§112
6.8%
-33.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1020 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-3, 6, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Kida et al (Publication number: US 2022/0236817) in view of Asada et al (Publication number: US 2022/0236820). Consider Claim 1, Kida touch-panel-integrated display device (see figures 1 and 5), comprising: (a) A plurality of pixel electrodes (see figures 4-5; and paragraphs 26-28); (Read as pixel electrodes 11). (b) A common electrode layer disposed opposite the plurality of pixel electrodes (see paragraph 27); (Pixel electrodes 11 and touch sensor electrodes 12 for forming electric fields are formed on the active-matrix substrate 10. The touch sensor electrodes 12 function as common electrodes, each of which is disposed opposite a plurality of pixel electrodes 11. The touch sensor electrodes 12 are each shared by a plurality of pixel electrodes 11). (c) A wiring layer stacked and disposed on the common electrode layer via an insulation layer (see figures 3 and 5; and paragraphs 28-29). (d) A touch panel driver, wherein each of the common electrode layer and the wiring layer contains a plurality of nodes that are arranged two-dimensionally, in each of the plurality of nodes, the common electrode layer contains: at least one drive electrode; at least one detection electrode forming an electrostatic capacitance between the at least one detection electrode and the at least one drive electrode (see figure 7; and paragraphs 32-34); (The touch detection driver 53 is disposed on the active matrix substrate 10. The touch detection driver 53 includes an integrated circuit that performs control processing relating to touch detection. The plurality of touch sensor electrodes 12 here may be made up of a plurality of drive electrodes 71 and a plurality of detection electrodes 72. The plurality of drive electrodes 71 may each be a transmitter electrode (Tx) to which touch detection driving signals are supplied. The plurality of detection electrodes 72 are disposed side-by-side in plan view with the plurality of drive electrodes 71, and may form capacitance between themselves and the plurality of drive electrodes 71. The plurality of detection electrodes 72 are each a receiver electrode (Rx) that supplies mutual capacitance detection signals to the touch detection driver 53). (e) A common electrode located between the at least one drive electrode and the at least one detection electrode and an adjacent one of the plurality of nodes, and in each of the plurality of nodes, the wiring layer contains: a drive-electrode-connection wire overlapping the at least one drive electrode in a plan view and connecting the at least one drive electrode and the touch panel driver (see paragraph 27); (Pixel electrodes 11 and touch sensor electrodes 12 for forming electric fields are formed on the active-matrix substrate 10. The touch sensor electrodes 12 function as common electrodes, each of which is disposed opposite a plurality of pixel electrodes 11. The touch sensor electrodes 12 are each shared by a plurality of pixel electrodes 11). (f) A detection-electrode-connection wire overlapping the at least one detection electrode in a plan view and connecting the at least one detection electrode and the touch panel driver (see figure 7; and paragraphs 32-34); (The touch detection driver 53 is disposed on the active matrix substrate 10. The touch detection driver 53 includes an integrated circuit that performs control processing relating to touch detection. The plurality of touch sensor electrodes 12 here may be made up of a plurality of drive electrodes 71 and a plurality of detection electrodes 72. The plurality of drive electrodes 71 may each be a transmitter electrode (Tx) to which touch detection driving signals are supplied. The plurality of detection electrodes 72 are disposed side-by-side in plan view with the plurality of drive electrodes 71, and may form capacitance between themselves and the plurality of drive electrodes 71. The plurality of detection electrodes 72 are each a receiver electrode (Rx) that supplies mutual capacitance detection signals to the touch detection driver 53). However, Kida et al does not specifically show a dummy line overlapping the common electrode in a plan view. In related art, Asada et al shows a dummy line overlapping the common electrode in a plan view (see figures 4 and 8; and paragraphs 37-38); (A dummy wiring line 14c is provided in an upper layer above the common electrode 13 at a position different from that of the touch sensor line 14 in plan view. The dummy wiring line 14c extends parallel to the touch sensor line 14 and is not directly connected to the touch detection driver 43. Note that the state in which the dummy wiring line 14c is not directly connected to the touch detection driver 43 includes a state in which, for example, the dummy wiring line 14c is electrically connected to the touch detection driver 43 with the common electrode 13 and the touch sensor line 14 interposed therebetween). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the dummy wiring line of Asada et al above the common electrode of Kida et al in order to protect against parasitic capacitance (see Asada et al; paragraphs 5-7). Consider Claim 2, Kida et al shows that the common electrode layer contains: a plurality of detection electrodes including the at least one detection electrode, and the at least one drive electrode, and the at least one drive electrode is located between the plurality of detection electrodes (see paragraph 27); (Pixel electrodes 11 and touch sensor electrodes 12 for forming electric fields are formed on the active-matrix substrate 10. The touch sensor electrodes 12 function as common electrodes, each of which is disposed opposite a plurality of pixel electrodes 11. The touch sensor electrodes 12 are each shared by a plurality of pixel electrodes 11). Consider Claim 3, Kida et al shows that the plurality of detection electrodes is arranged in m rows and n columns where m and n are natural numbers, and at least one drive electrode is shaped like a grid located between the plurality of detection electrodes (see paragraphs 50-52). Consider Claim 6, Asada et al shows a plurality of thin film transistors; a plurality of gate lines connected to gates of the plurality of thin film transistors and extending in a row direction; and a plurality of source lines connected to sources of the plurality of thin film transistors and extending in a column direction, wherein the detection-electrode-connection wire extends in the column direction and overlaps one of the plurality of source lines in a plan view, the drive-electrode-connection wire extends in the row direction and overlaps one of the plurality of gate lines in a plan view, and the dummy line extends in the column direction and overlaps another one of the plurality of source lines in a plan view (see figures 4 and 8; and paragraphs 37-38); (A dummy wiring line 14c is provided in an upper layer above the common electrode 13 at a position different from that of the touch sensor line 14 in plan view. The dummy wiring line 14c extends parallel to the touch sensor line 14 and is not directly connected to the touch detection driver 43. Note that the state in which the dummy wiring line 14c is not directly connected to the touch detection driver 43 includes a state in which, for example, the dummy wiring line 14c is electrically connected to the touch detection driver 43 with the common electrode 13 and the touch sensor line 14 interposed therebetween). Consider Claim 11, Asada et al shows that the dummy line is connected to the common electrode (see figures 4 and 8; and paragraphs 37-38). Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kida et al (Publication number: US 2022/0236817) in view of Asada et al (Publication number: US 2022/0236820) in view of Lee et al (Publication number: US 2021/0141492). Consider Claim 5, Kida et al in view of Asada et al do not specifically show that the common electrode is connected to a reference potential. In related art, Lee et al shows that the common electrode is connected to a reference potential (see paragraphs 249-251); (The common electrode CE receives a reference voltage and the pixel electrode PE receives a pixel voltage corresponding to the data voltage. The common electrode CE and the pixel electrode PE form a horizontal electric field). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the teaching of Lee et al into the teaching of Kida et al and Asada et al in order to form a horizontal electric field (see Lee et al; paragraphs 249-251). Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kida et al (Publication number: US 2022/0236817) in view of Asada et al (Publication number: US 2022/0236820) in view of Lee et al (Publication number: US 2021/0191208). Consider Claim 10, Kida et al in view of Asada et al do not specifically show that the dummy line and the common electrode are electrically insulated from each other, and the dummy line is floated. In related art, Lee et al shows that the dummy line and the common electrode are electrically insulated from each other, and the dummy line is floated (see paragraphs 72-74). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the teaching of Lee et al into the teaching of Kida et al and Asada et al in order for the dummy line to be electrically separated from other wires (see Lee et al; paragraphs 73-74). Allowable Subject Matter Claims 4, and 7-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL A FARAGALLA whose telephone number is (571)270-1107. The examiner can normally be reached Mon-Fri 8:00-5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached at 571-270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL A FARAGALLA/Primary Examiner, Art Unit 2624 09/30/2026
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Prosecution Timeline

Mar 19, 2026
Application Filed
Oct 02, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
94%
With Interview (+8.2%)
2y 11m (~2y 3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1020 resolved cases by this examiner. Grant probability derived from career allowance rate.

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