DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
RESPONSE TO AMENDMENT
Claim rejections based on prior art
Applicant’s arguments filed 09/07/2025 with respect to claims 1-30 have been fully considered but are not persuasive.
Note, even though prosecution is now closed, to help expedite any further potential prosecution of this application, Applicant is encouraged to contact the Examiner to discuss the invention, and a potential allowance.
In regards to claims 1, 27 and 29, see paragraph 0175 or claim 17 of Jayaraman which discloses translation from H2D to D2H; for example claim 17 of Jayaraman disclose “translate the H2D message received from the first host CPU to a second D2H message, the second D2H message to indicate an address for the cache line in the shared region of memory for which the first host CPU has requested to read or write; send, through the interface, the second D2H message to the second host CPU”, or paragraph 0175, which discloses “the circuitry configured to translate the H2D message received from the first host CPU to a second D2H message, the second D2H message to indicate an address for the cache line in the shared region of memory for which the first host CPU has requested to read or write. The circuitry can also be configured to send, through the interface, the second D2H message to the second host CPU. The circuitry can also be configured to receive, through the interface from the second host CPU, a response to indicate that the second host CPU does not have a cached copy of the cache line via a second H2D message”.
With respect to claim limitation: wherein the first entity comprises a first host, and the CXL.cache H2D request comprises a first address belonging to a first Host Physical Address (HPA) space utilized by the first host; and wherein the second entity comprises a second host, and wherein the CXL.cache D2H request comprises a second address belonging to a second HPA space utilized by the second host (see paragraph 0025 and particularly paragraph 0037, which “as shown in FIG. 3, a system address memory map 315-P can represent a map of host physical addresses of memory 314-P. Primary node 310-P, in some examples, can earmark a region of memory 314-P from system address memory map 315-P and include that earmarked region in shared region 317. In some examples, shared region 317 can be shared with secondary nodes 320-S1, S2, S3 and mapped by these secondary systems in their respective system address memory maps 325-S1, S2, S3. The mapped shared memory for secondary node 320-S1, for example, is shown in FIG. 3 as shared map 321-S1. Shared maps 321-S1, S2, S3 can be mapped to regions of respective memories 324-S1, S2, S3 as a CXL.mem based HDM-D as described by CXL 2.0, CXL 3.0 and/or subsequent CXL specifications, or as a CXL.mem based HDM-DB as described by CXL 3.0, and/or subsequent CXL specifications”).
With respect to claim limitation: receiving from the second host a CXL.cache H2D Data, translating the CXL.cache H2D Data to a CXL.cache Device-to-Host (D2H) Data, and sending the CXL.cache D2H Data to the first host (see paragraph 0046, which discloses “for these examples, logic and/or features of ECB 132 translates or converts M2S/D2H, S2M/H2D requests/messages and H2D snoops generated by primary node 110-P or secondary nodes 120-S1, S2, S3 according to CXL 2.0 and/or CXL 3.0 protocols”).
With respect to claim limitation: exposing a CXL Type-1 device or a CXL Type-2 device to the first entity via a first interface, and exposing a CXL Type-1 device or a CXL Type-2 device to the second entity via a second interface [see paragraph 0036, which discloses “in order to further facilitate dielet or chiplet communications (e.g., ECB 332 to IO die 316-1-P or IO die 326-1-S1), links 330-1 to 330-4 can be configured to operate according to the UCIe specification and use protocols described in CXL 2.0, CXL 3.0 and/or subsequent CXL specifications (e.g., CXL over UCIe links)”].
With respect to claim limitation: exposing a cache abstraction to the first entity via a CXL.cache interface, wherein the cache abstraction acts as a proxy for a cache included in the second entity, and the CXL.cache H2D request targets the cache abstraction (note, this language is being interpreted to recite a proxy, representation cache access; therefore, see paragraph 0033, which discloses “in some examples, as shown in FIG. 2, a system address memory map 215-P can represent a map of host physical addresses of memory 214-P. Primary node 210-P, in some examples, can earmark a region of memory 214-P from system address memory map 215-P and include that earmarked region in shared region 217. In some examples, shared region 217 can be shared with secondary nodes 220-S1, S2, S3 and mapped by these secondary systems in their respective system address memory maps 225-S1, S2, S3”).
With respect to claim limitation: an active cable comprising first and second pluggable modules coupled by a physical medium; wherein the active cable further comprises hardware circuitry, integrated into the active cable, configured to perform the method of claim 1 (see fig. 1 and paragraph 0034, which discloses ‘links’).
With respect to claim limitation: wherein the first entity comprises a first host utilizing the first HPA space, and the second entity comprises a second host utilizing the second HPA space; and wherein the computer is further configured to identify an intent indicated by the CXL.cache H2D request, wherein the intent comprises a cacheline state intent for a cacheline address, and wherein the translating is based at least in part on the identified intent (see paragraphs 0025 and 0175).
With respect to claims 3, 4, 6, 8-12, 14 and 16-19, please note, acronyms such as “SnpInv”, “RdOwnNoData”, “SnpData”, “GO opcode”, “FwD”, ”GO-I”, “GO-S”, “GO-E” and “GO-M” are not well-known terms in the art.
OBJECTIONS TO THE CLAIMS
Claims 23, 25 and 26 are objected to as being indefinite for failing to particularly point out and distinctly claim the subject matter which applicant regards as the invention.
As per claims 23, 25 and 26, it’s not clear if these claims are written as independent or dependent claims. Correction is needed.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
1. Claims 1, 2, 5, 15 and 20-30 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jayaraman et al. (US pub. 2023/0236995), hereinafter, “Jayaraman”.
At the outset, Applicant is reminded that claims subject to examination will be given their broadest reasonable interpretation in light of the supporting disclosure. In re Morris, 127 F.3d 1048, 1054-55, 44 USPQ2d 1023,1027-28 (Fed. Cir. 1997). With this in mind, the discussion will focus on how the terms and relationships between the terms in the claims are met by the references.
2. As per claim 1, Jayaraman discloses a method for translating between Compute Express Link (CXL) messages, comprising: receiving, from a first entity (a first host CPU, as discloses in claim 17 of Jayaraman), a CXL.cache Host-to-Device (H2D) request; translating the CXL.cache H2D request to a CXL.cache Device-to-Host (D2H) request; and sending the CXL.cache D2H request to a second entity (a second host CPU, as discloses in claim 17 of Jayaraman) (see claim 17 of Jayaraman which disclose “translate the H2D message received from the first host CPU to a second D2H message, the second D2H message to indicate an address for the cache line in the shared region of memory for which the first host CPU has requested to read or write; send, through the interface, the second D2H message to the second host CPU”).
3. As per claim 2, Jayaraman discloses “The method of claim 2” [See rejection to claim 2 above], wherein the first entity comprises a first host, and the CXL.cache H2D request comprises a first address belonging to a first Host Physical Address (HPA) space utilized by the first host; and wherein the second entity comprises a second host, and wherein the CXL.cache D2H request comprises a second address belonging to a second HPA space utilized by the second host (see paragraph 0025 and particularly paragraph 0037, which “as shown in FIG. 3, a system address memory map 315-P can represent a map of host physical addresses of memory 314-P. Primary node 310-P, in some examples, can earmark a region of memory 314-P from system address memory map 315-P and include that earmarked region in shared region 317. In some examples, shared region 317 can be shared with secondary nodes 320-S1, S2, S3 and mapped by these secondary systems in their respective system address memory maps 325-S1, S2, S3. The mapped shared memory for secondary node 320-S1, for example, is shown in FIG. 3 as shared map 321-S1. Shared maps 321-S1, S2, S3 can be mapped to regions of respective memories 324-S1, S2, S3 as a CXL.mem based HDM-D as described by CXL 2.0, CXL 3.0 and/or subsequent CXL specifications, or as a CXL.mem based HDM-DB as described by CXL 3.0, and/or subsequent CXL specifications”).
4. As per claim 5, Jayaraman discloses further comprising receiving from the second host a CXL.cache H2D Data, translating the CXL.cache H2D Data to a CXL.cache Device-to-Host (D2H) Data, and sending the CXL.cache D2H Data to the first host (see paragraph 0046, which discloses “for these examples, logic and/or features of ECB 132 translates or converts M2S/D2H, S2M/H2D requests/messages and H2D snoops generated by primary node 110-P or secondary nodes 120-S1, S2, S3 according to CXL 2.0 and/or CXL 3.0 protocols”).
5. As per claim 15, Jayaraman discloses further comprising exposing a CXL Type-1 device or a CXL Type-2 device to the first entity via a first interface, and exposing a CXL Type-1 device or a CXL Type-2 device to the second entity via a second interface [see paragraph 0036, which discloses “in order to further facilitate dielet or chiplet communications (e.g., ECB 332 to IO die 316-1-P or IO die 326-1-S1), links 330-1 to 330-4 can be configured to operate according to the UCIe specification and use protocols described in CXL 2.0, CXL 3.0 and/or subsequent CXL specifications (e.g., CXL over UCIe links)”].
6. As per claim 20, Jayaraman discloses further comprising exposing a cache abstraction to the first entity via a CXL.cache interface, wherein the cache abstraction acts as a proxy for a cache included in the second entity, and the CXL.cache H2D request targets the cache abstraction (note, this language is being interpreted to recite a proxy, representation cache access; therefore, see paragraph 0033, which discloses “in some examples, as shown in FIG. 2, a system address memory map 215-P can represent a map of host physical addresses of memory 214-P. Primary node 210-P, in some examples, can earmark a region of memory 214-P from system address memory map 215-P and include that earmarked region in shared region 217. In some examples, shared region 217 can be shared with secondary nodes 220-S1, S2, S3 and mapped by these secondary systems in their respective system address memory maps 225-S1, S2, S3”).
7. As per claim 21, Jayaraman discloses wherein the translating enables cacheline state orchestration between a first cache maintained by the first entity and a second cache maintained by the second entity (see paragraphs 0026 and 0027).
8. As per claim 22, Jayaraman discloses wherein the cacheline state orchestration comprises cross invalidation of cacheline states; and/or wherein the cacheline state orchestration enables cache-coherent memory sharing between the first entity and the second entity (see paragraph 0037).
9. As per claim 23, Jayaraman discloses a non-transitory computer-readable medium comprising instructions which, when executed by a processor, cause the processor to perform the method of claim 1 (see paragraph 0141).
10. As per claim 24, Jayaraman discloses one or more integrated circuits configured to perform the method of claim 1, wherein the one or more integrated circuits comprise at least one of: (i) a general-purpose processing unit, comprising or connected to communication interfaces, configured to perform the method via software and/or firmware execution, (ii) circuitry comprising firmware and/or hardware logic integrated into an electronic device, wherein the circuitry utilizes operations that benefit from hardware acceleration and/or specialized processing capabilities not typically provided by a general-purpose processing unit, or (iii) one or more chiplets within one or more integrated circuit packages (see paragraph 0141).
11. As per claim 25, Jayaraman discloses an active cable comprising first and second pluggable modules coupled by a physical medium; wherein the active cable further comprises hardware circuitry, integrated into the active cable, configured to perform the method of claim 1 (see fig. 1 and paragraph 0034, which discloses ‘links’).
12. As per claim 26, Jayaraman discloses an apparatus configured to operate as a switch, wherein the apparatus comprises switching circuitry and is configured to perform the method of claim 1 (see fig. 1).
13. As per claims 27 and 29, Jayaraman discloses a system comprising: first and second interfaces based on Compute Express Link (CXL); a computer coupled to the first and second interfaces, wherein the computer is configured to: receive, from a first entity via the first interface, a CXL.cache Host-to-Device (H2D) request comprising a first address belonging to a first Host Physical Address (HPA) space; translate the CXL.cache H2D request to a CXL.cache Device-to-Host (D2H) request comprising a second address belonging to a second HPA space; and send the CXL.cache D2H request to a second entity via the second interface (see claim 17 of Jayaraman which disclose “translate the H2D message received from the first host CPU to a second D2H message, the second D2H message to indicate an address for the cache line in the shared region of memory for which the first host CPU has requested to read or write; send, through the interface, the second D2H message to the second host CPU”).
.
14. As per claim 28, Jayaraman discloses wherein the first entity comprises a first host utilizing the first HPA space, and the second entity comprises a second host utilizing the second HPA space; and wherein the computer is further configured to identify an intent indicated by the CXL.cache H2D request, wherein the intent comprises a cacheline state intent for a cacheline address, and wherein the translating is based at least in part on the identified intent (see paragraphs 0025 and 0175).
15. As per claim 30, Jayaraman discloses wherein the cacheline state orchestration comprises cross invalidation of cacheline states, and wherein the cacheline state orchestration enables cache-coherent memory sharing between the first entity and the second entity (see paragraph 0025).
Claim Rejections - 35 USC § 103
16. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
17. Claims 3, 4, 6-14 and 16-19 are rejected under 35 U.S.C. 103(a) as being unpatentable over Jayaraman et al. (US pub. 2023/0236995), hereinafter, “Jayaraman”, in view of Johns et al. (US pub. 2025/0007722), hereinafter, “Johns”.
18. As per claim 3, Jayaraman discloses “The method of claim 2” [See rejection to claim 2 above], but fails to expressly discloses wherein the CXL.cache H2D request comprises snoop invalidate (SnpInv) and Unique Queue ID (UQID), and wherein the CXL.cache D2H request comprises CacheLine Flush (CLFlush) and command queue identifier (CQID).
Johns discloses wherein the CXL.cache H2D request comprises snoop invalidate (SnpInv) and Unique Queue ID (UQID), and wherein the CXL.cache D2H request comprises CacheLine Flush (CLFlush) and command queue identifier (CQID) (see paragraph 0050).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the Applicant’s claimed invention to combine Jayaraman with Johns because both are directed to the same field of endeavor of communicating using Compute Express Link method. One of ordinary skill in the art would have been motivated to utilize Johns’ Master to Subordinate Request packaging opcode, tag, and address in Jayaraman’s CXL transaction processing to further improve the communication system with multiple hosts (Johns, paragraph 0025).
19. As per claim 4, Jayaraman discloses “The method of claim 2” [See rejection to claim 2 above], but fails to expressly discloses wherein the CXL.cache H2D request comprises snoop invalidate (SnpInv) and Unique Queue ID (UQID), and the CXL.cache D2H request comprises command queue identifier (CQID) and Read for Ownership No Data (RdOwnNoData) or Read for Ownership (RdOwn).
Johns discloses wherein the CXL.cache H2D request comprises snoop invalidate (SnpInv) and Unique Queue ID (UQID), and the CXL.cache D2H request comprises command queue identifier (CQID) and Read for Ownership No Data (RdOwnNoData) or Read for Ownership (RdOwn) (see paragraphs 0051 and 0055).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the Applicant’s claimed invention to combine Jayaraman with Johns because both are directed to the same field of endeavor of communicating using Compute Express Link method. One of ordinary skill in the art would have been motivated to utilize Johns’ Master to Subordinate Request packaging opcode, tag, and address in Jayaraman’s CXL transaction processing to further improve the communication system with multiple hosts (Johns, paragraph 0025).
20. As per claim 6, Jayaraman discloses “The method of claim 2” [See rejection to claim 2 above], but fails to expressly discloses wherein the CXL.cache H2D request comprises SnpData and Unique Queue ID (UQID), and the CXL.cache D2H request comprises RdShared and command queue identifier (CQID).
Johns discloses wherein the CXL.cache H2D request comprises SnpData and Unique Queue ID (UQID), and the CXL.cache D2H request comprises RdShared and command queue identifier (CQID) (see paragraph 0050).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the Applicant’s claimed invention to combine Jayaraman with Johns because both are directed to the same field of endeavor of communicating using Compute Express Link method. One of ordinary skill in the art would have been motivated to utilize Johns’ Master to Subordinate Request packaging opcode, tag, and address in Jayaraman’s CXL transaction processing to further improve the communication system with multiple hosts (Johns, paragraph 0025).
21. As per claim 7, Jayaraman discloses “The method of claim 2” [See rejection to claim 2 above], but fails to expressly discloses wherein the CXL.cache H2D request comprises SnpData and Unique Queue ID (UQID), and the CXL.cache D2H request comprises RdOwn and command queue identifier (CQID).
Johns discloses wherein the CXL.cache H2D request comprises SnpData and Unique Queue ID (UQID), and the CXL.cache D2H request comprises RdOwn and command queue identifier (CQID) (see paragraph 0050).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the Applicant’s claimed invention to combine Jayaraman with Johns because both are directed to the same field of endeavor of communicating using Compute Express Link method. One of ordinary skill in the art would have been motivated to utilize Johns’ Master to Subordinate Request packaging opcode, tag, and address in Jayaraman’s CXL transaction processing to further improve the communication system with multiple hosts (Johns, paragraph 0025).
22. As per claim 8, Jayaraman discloses “The method of claim 2” [See rejection to claim 2 above], but fails to expressly discloses wherein the CXL.cache H2D request comprises snoop invalidate (SnpInv) and Unique Queue ID (UQID), the CXL.cache D2H request comprises RdOwn and command queue identifier (CQID), and further comprising receiving from the second host a CXL.cache H2D Data message comprising cacheline data.
Johns discloses wherein the CXL.cache H2D request comprises snoop invalidate (SnpInv) and Unique Queue ID (UQID), the CXL.cache D2H request comprises RdOwn and command queue identifier (CQID), and further comprising receiving from the second host a CXL.cache H2D Data message comprising cacheline data (see paragraphs 0051 and 0055).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the Applicant’s claimed invention to combine Jayaraman with Johns because both are directed to the same field of endeavor of communicating using Compute Express Link method. One of ordinary skill in the art would have been motivated to utilize Johns’ Master to Subordinate Request packaging opcode, tag, and address in Jayaraman’s CXL transaction processing to further improve the communication system with multiple hosts (Johns, paragraph 0025).
23. As per claim 9, Jayaraman discloses “The method of claim 1” [See rejection to claim 1 above], but fails to expressly discloses further comprising: receiving, from the second entity, a CXL.cache H2D Data message comprising cacheline data and command queue identifier (CQID); translating the CXL.cache H2D Data message to a CXL.cache D2H Data message comprising the cacheline data and Unique Queue ID (UQID); and sending the CXL.cache D2H Data message to the first entity.
Johns discloses further comprising: receiving, from the second entity, a CXL.cache H2D Data message comprising cacheline data and command queue identifier (CQID); translating the CXL.cache H2D Data message to a CXL.cache D2H Data message comprising the cacheline data and Unique Queue ID (UQID); and sending the CXL.cache D2H Data message to the first entity (see paragraphs 0050 and 0051).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the Applicant’s claimed invention to combine Jayaraman with Johns because both are directed to the same field of endeavor of communicating using Compute Express Link method. One of ordinary skill in the art would have been motivated to utilize Johns’ Master to Subordinate Request packaging opcode, tag, and address in Jayaraman’s CXL transaction processing to further improve the communication system with multiple hosts (Johns, paragraph 0025).
24. As per claim 10, Jayaraman discloses “The method of claim 1” [See rejection to claim 1 above], but fails to expressly discloses further comprising receiving, from the second entity, a CXL.cache H2D response comprising a GO opcode and command queue identifier (CQID); translating the CXL.cache H2D response to a CXL.cache D2H response comprising Rsp* and Unique Queue ID (UQID); and sending the CXL.cache D2H response to the first entity.
Johns discloses further comprising receiving, from the second entity, a CXL.cache H2D response comprising a GO opcode and command queue identifier (CQID); translating the CXL.cache H2D response to a CXL.cache D2H response comprising Rsp* and Unique Queue ID (UQID); and sending the CXL.cache D2H response to the first entity (see paragraphs 0050 and 0058).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the Applicant’s claimed invention to combine Jayaraman with Johns because both are directed to the same field of endeavor of communicating using Compute Express Link method. One of ordinary skill in the art would have been motivated to utilize Johns’ Master to Subordinate Request packaging opcode, tag, and address in Jayaraman’s CXL transaction processing to further improve the communication system with multiple hosts (Johns, paragraph 0025).
25. As per claim 11, the combination of Jayaraman and Johns discloses “The method of claim 10” [See rejection to claim 10 above], wherein the CXL.cache H2D response comprises a GO opcode and a field indicating an Invalid state (GO-I), and wherein the CXL.cache D2H response comprises RspIHitI (see paragraphs 0041 and 0104 of Johns).
26. As per claim 12, Jayaraman discloses “The method of claim 1” [See rejection to claim 1 above], but fails to expressly discloses further comprising receiving, from the second entity, a CXL.cache H2D Data comprising command queue identifier (CQID); translating the CXL.cache H2D Data to a CXL.cache D2H response comprising *Fwd* and Unique Queue ID (UQID); and sending the CXL.cache D2H response to the first entity.
Johns discloses further comprising receiving, from the second entity, a CXL.cache H2D Data comprising command queue identifier (CQID); translating the CXL.cache H2D Data to a CXL.cache D2H response comprising *Fwd* and Unique Queue ID (UQID); and sending the CXL.cache D2H response to the first entity (see paragraphs 0050 and 0051).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the Applicant’s claimed invention to combine Jayaraman with Johns because both are directed to the same field of endeavor of communicating using Compute Express Link method. One of ordinary skill in the art would have been motivated to utilize Johns’ Master to Subordinate Request packaging opcode, tag, and address in Jayaraman’s CXL transaction processing to further improve the communication system with multiple hosts (Johns, paragraph 0025).
27. As per claim 13, the combination of Jayaraman and Johns discloses “The method of claim 12” [See rejection to claim 12 above], wherein the CXL.cache D2H request comprises RdCurr and command queue identifier (CQID); and further comprising translating the CXL.cache H2D Data to a CXL.cache D2H response comprising RspVFwdV and Unique Queue ID (UQID) (see paragraphs 0050 and 0051 of Johns).
28. As per claim 14, Jayaraman discloses “The method of claim 1” [See rejection to claim 1 above], but fails to expressly discloses further comprising receiving, from the second entity, a CXL.cache H2D response comprising a GO opcode and command queue identifier (CQID); translating the CXL.cache H2D response to a CXL.cache D2H Data comprising Unique Queue ID (UQID); and sending the CXL.cache D2H Data to the first entity.
Johns discloses further comprising receiving, from the second entity, a CXL.cache H2D response comprising a GO opcode and command queue identifier (CQID); translating the CXL.cache H2D response to a CXL.cache D2H Data comprising Unique Queue ID (UQID); and sending the CXL.cache D2H Data to the first entity (see paragraphs 0050 and 0058).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the Applicant’s claimed invention to combine Jayaraman with Johns because both are directed to the same field of endeavor of communicating using Compute Express Link method. One of ordinary skill in the art would have been motivated to utilize Johns’ Master to Subordinate Request packaging opcode, tag, and address in Jayaraman’s CXL transaction processing to further improve the communication system with multiple hosts (Johns, paragraph 0025).
29. As per claim 16, Jayaraman discloses “The method of claim 1” [See rejection to claim 1 above], but fails to expressly discloses wherein the translating comprises performing translations between the CXL.cache H2D request and the CXL.cache D2H request, wherein the translations comprise translations between Unique Queue ID (UQID) and command queue identifier (CQID), translations between reserved fields, and/or translations between reserved and non-reserved fields.
Johns discloses wherein the translating comprises performing translations between the CXL.cache H2D request and the CXL.cache D2H request, wherein the translations comprise translations between Unique Queue ID (UQID) and command queue identifier (CQID), translations between reserved fields, and/or translations between reserved and non-reserved fields (see paragraphs 0050 and 0051).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the Applicant’s claimed invention to combine Jayaraman with Johns because both are directed to the same field of endeavor of communicating using Compute Express Link method. One of ordinary skill in the art would have been motivated to utilize Johns’ Master to Subordinate Request packaging opcode, tag, and address in Jayaraman’s CXL transaction processing to further improve the communication system with multiple hosts (Johns, paragraph 0025).
30. As per claim 17, Jayaraman discloses “The method of claim 1” [See rejection to claim 1 above], but fails to expressly discloses further comprising: receiving, from the second entity, a CXL.cache H2D response comprising a GO-S indication and command queue identifier (CQID); translating the CXL.cache H2D response to a CXL.cache D2H response comprising RspSHitSE and Unique Queue ID (UQID); and sending the CXL.cache D2H response to the first entity.
Johns discloses further comprising: receiving, from the second entity, a CXL.cache H2D response comprising a GO-S indication and command queue identifier (CQID); translating the CXL.cache H2D response to a CXL.cache D2H response comprising RspSHitSE and Unique Queue ID (UQID); and sending the CXL.cache D2H response to the first entity (see paragraphs 0050 and 0112).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the Applicant’s claimed invention to combine Jayaraman with Johns because both are directed to the same field of endeavor of communicating using Compute Express Link method. One of ordinary skill in the art would have been motivated to utilize Johns’ Master to Subordinate Request packaging opcode, tag, and address in Jayaraman’s CXL transaction processing to further improve the communication system with multiple hosts (Johns, paragraph 0025).
31. As per claim 18, Jayaraman discloses “The method of claim 1” [See rejection to claim 1 above], but fails to expressly discloses further comprising: receiving, from the second entity, a CXL.cache H2D response comprising a GO-E indication and command queue identifier (CQID); translating the CXL.cache H2D response to a CXL.cache D2H response comprising an opcode selected from RspIHitI, RspIHitSE, or RspIFwdM, and comprising Unique Queue ID (UQID); and sending the CXL.cache D2H response to the first entity.
Johns discloses further comprising: receiving, from the second entity, a CXL.cache H2D response comprising a GO-E indication and command queue identifier (CQID); translating the CXL.cache H2D response to a CXL.cache D2H response comprising an opcode selected from RspIHitI, RspIHitSE, or RspIFwdM, and comprising Unique Queue ID (UQID); and sending the CXL.cache D2H response to the first entity (see paragraphs 0050 and 0077).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the Applicant’s claimed invention to combine Jayaraman with Johns because both are directed to the same field of endeavor of communicating using Compute Express Link method. One of ordinary skill in the art would have been motivated to utilize Johns’ Master to Subordinate Request packaging opcode, tag, and address in Jayaraman’s CXL transaction processing to further improve the communication system with multiple hosts (Johns, paragraph 0025).
32. As per claim 19, Jayaraman discloses “The method of claim 1” [See rejection to claim 1 above], but fails to expressly discloses further comprising: receiving, from the second entity, a CXL.cache H2D response comprising a GO-M indication and command queue identifier (CQID), and a CXL.cache H2D Data message comprising cacheline data; translating the CXL.cache H2D response to a CXL.cache D2H response comprising RspIFwdM and Unique Queue ID (UQID); and sending the CXL.cache D2H response to the first entity.
Johns discloses further comprising: receiving, from the second entity, a CXL.cache H2D response comprising a GO-M indication and command queue identifier (CQID), and a CXL.cache H2D Data message comprising cacheline data; translating the CXL.cache H2D response to a CXL.cache D2H response comprising RspIFwdM and Unique Queue ID (UQID); and sending the CXL.cache D2H response to the first entity (see paragraphs 0050 and 0077).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the Applicant’s claimed invention to combine Jayaraman with Johns because both are directed to the same field of endeavor of communicating using Compute Express Link method. One of ordinary skill in the art would have been motivated to utilize Johns’ Master to Subordinate Request packaging opcode, tag, and address in Jayaraman’s CXL transaction processing to further improve the communication system with multiple hosts (Johns, paragraph 0025).
CLOSING COMMENTS
Conclusion
a. STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
a(1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-30 have received a final action on the merits.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
b. DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Ernest Unelus whose telephone number is (571) 272-8596. The examiner can normally be reached on Monday to Friday 9:00 AM to 5:00 PM.
IMPORTANT NOTE
If attempts to reach the above noted Examiner by telephone are unsuccessful, the Examiner's supervisor, Mr. Idriss Alrobaye, can be reached at the following telephone number: Area Code (571) 270-1023.
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/Ernest Unelus/
Primary Examiner
Art Unit 2181
