DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Obvious-type Double Patenting (ODP) Rejections
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
This is a provisional obviousness-type double patenting rejection because the conflicting claims have not in fact been patented. (Do not use against patented applications).
Claims 1, 11, 15, and 20 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claim 1 of copending Application No. 19/629017 hereinafter ‘017. Although the conflicting claims are not identical, they are not patentably distinct from each other. For example, Claims 1, 11, 15, and 20 of instant Application, respectively contain elements of claim 1 of the ‘017 as follows:
Claims
Instant
Claim
‘017
1, 11, 15, 20
CXL messages
PCIe TLPs
receiving by
a computer
a first entity
a CXL.mem M2S request
translating to
a PCIe memory request
sending to
a second entity
receiving
a PCIe Completion
translating to
a CXL.mem S2M response
sending to
the first entity the response
1
CXL messages
PCIe TLPs
receiving by
a computer
a first entity
a PCIe memory request*
translating to
a CXL.mem M2S request*
sending to
a second entity
receiving
a CXL.mem M2S request*
translating to
a PCIE Completion*
sending to
the first entity the completion*
Claims 1, 11, 15, and 20 of instant Application does not expressly disclose arrangement of CXL.mem M2S request, PCIe memory request, PCIe Completion, and CXL.mem S2M response as it is in ‘017. However, they are merely describing bidirectional nature of communication/translation between the first entity and the second. At the time of the invention it would have been obvious to a person of ordinary skill in the art to incorporate common sense of communicating between two entities that speaks/communicate different language/protocol. The suggestion/motivation for doing so would have been to open communication channels.
Claim Rejections - 35 USC § 112 2nd
The following is a quotation of the second paragraph of 35 U.S.C. 112:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-4, 6, and 9 are rejected under 35 U.S.C. 112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which applicant regards as the invention.
Use of the abbreviated word ‘MemRd*’ in claims 3 and 9 fails to particularly point out and distinctly claim the subject matter. At least, it should be spelled out and explained first time it appears in the claims.
Use of the abbreviated word ‘MemRd*’ in claims 4 and 6 fails to particularly point out and distinctly claim the subject matter. At least, it should be spelled out and explained first time it appears in the claims.
Use of the abbreviated word ‘UIO’ in claims 3-4, 6, and 9 fails to particularly point out and distinctly claim the subject matter. At least, it should be spelled out and explained first time it appears in the claims.
Applicant is required to review the claim and correct all language which does not comply with 35 U.S.C. § 112, second paragraph.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 11-12, 14-15, 17, and 20-24 are rejected under 35 U.S.C. 103 as being unpatentable over Das Sharama (U.S. Publication 2021/0240655), hereinafter Das in view of Paliwal et al. (U.S. Publication 2021/0112132), hereinafter Paliwal.
Referring to claim 1, Paliwal teaches, as claimed, a method for translating between Compute Express Link (CXL) messages and Peripheral Component Interconnect Express (PCIe) Transaction Layer Packets (TLPs), comprising:
receiving, by a computer (microprocessor, see Paragraph 19) from a first entity (handheld devices, see Paragraph 19), a CXL.mem (CXL.mem Master, see Paragraph 61) Master-to-Subordinate (M2S) (Subordinate, see Paragraph 61) request (requests, see Paragraph 19);
translating (a translator such as a binary translator, translates code either statistically or dynamically, see Paragraph 127), by the computer, the CXL.mem M2S (CXL, see Paragraph 56; and see Fig. 6, 615A) request
sending, by the computer to a second entity (see Fig. 6, CPU 605), the PCIe memory request;
receiving, by the computer from the second entity, a PCIe (PCIe or CXL -based interconnects… indications in TLPs, see Paragraph 64) Completion (Completions, see Paragraph 65) corresponding to the PCIe memory request;
translating (a translator such as a binary translator, translates code either statistically or dynamically, see Paragraph 127), by the computer, the PCIe Completion
sending, by the computer to the first entity, the CXL.mem S2M response (CXL memory protocol, see Paragraph 62).
Das does not disclose expressly communicating the CXL to PCIe and communicating PCIe to CXL.
Paliwal does disclose communicating the CXL (see Fig. 6, 618 CXL.io Transaction Layer and 628 CXL.io Link Layer) to PCIe (see Fig. 6, 616 PCIe Transaction Layer and 626 PCIe Data Link Layer) and communicating PCIe (see Fig. 6, 616 PCIe Transaction Layer and 626 PCIe Data Link Layer) to CXL (see Fig. 6, 618 CXL.io Transaction Layer and 628 CXL.io Link Layer).
At the time of the invention it would have been obvious to a person of ordinary skill in the art to incorporate multi-protocol link of Paliwal into flexible device interconnects of Das.
The suggestion/motivation for doing so would have been to provide alternative way to conserve energy and efficiency (see Paliwal, Paragraphs 3 and 19).
As to claim 2, the modification teaches the method of claim 1, wherein the CXL.mem M2S request comprises a first physical address (physical address translations, see Das, Paragraph 120) belonging to a first physical address space (physical memory, see Das, Paragraph 120) utilized by the first entity, and wherein translating the CXL.mem M2S request to the PCIe memory request comprises generating the PCIe memory request comprising a second physical address (physical address translations, see Das, Paragraph 120; Note, same concept of physical address in the first applies to the second) belonging to a second physical address space (physical memory, see Das, Paragraph 120) utilized by the second entity.
As to claim 11, the modification teaches the non-transitory computer-readable medium comprising instructions which, when executed by a processor, cause the processor to perform the method of claim 1 (claim 11 is directed to a program to implement the method as set forth in claim 1.
As to claim 12, the modification teaches the nne or more integrated circuits configured to perform the method of claim 1, wherein the one or more integrated circuits comprise at least one of: (i) a general-purpose processing unit (computing platforms, see Das, Paragraph 19), comprising or connected to communication interfaces, configured to perform the method via software and/or firmware execution, (ii) circuitry comprising firmware and/or hardware logic integrated into an electronic device, wherein the circuitry utilizes operations that benefit from hardware acceleration and/or specialized processing capabilities not typically provided by a general-purpose processing unit, or (iii) one or more chiplets within one or more integrated circuit packages.
As to claim 14, the modification teaches the apparatus configured to operate as a switch (switches, see Das, Paragraph 19), wherein the apparatus comprises switching circuitry and is configured to perform the method of claim 1.
As to claims 15, 20, and 24, they are directed to a method/system and method on multiple entities (see Das, Fig. 10) to implement the method as set forth in claim 1. Therefore, they are rejected on the same basis as set forth hereinabove.
As to claim 17, the modification teaches the apparatus of claim 15, wherein the first physical address space comprises the second physical address space (Note, it is implicit a memory comprises a segment of memory).
As to claim 21, the modification teaches the system of claim 20, wherein the second entity and the second memory form a memory pool (pooled memories, see Paliwal, Paragraph 68), and wherein the computer is configured to expose the memory pool to the first entity.
As to claim 22, the modification teaches the system of claim 20, wherein the second memory comprises DDR4 memory (DDR memory devices, see Das, Paragraph 56), and wherein the first memory comprises DDR5 memory.
As to claim 23, the modification teaches the system of claim 20 wherein the CPU comprises a pre-CXL generation CPU (CXL maybe built upon the well-established… , see Paragraph 53), and the pre-CXL generation CPU is installed in a datacenter (datacenter, see Paliwal, Paragraph 72) server.
Claims 13 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Das in view of Paliwal further in view of Jason, “Exploring the History of Active Optical Cables” hereinafter Jason.
As to claims 13 and 18, the modification teaches method of claim 1.
The Das/Paliwal modification does not expressly disclose the active cable comprising first and second pluggable modules coupled by a physical medium; wherein the active cable further comprises hardware circuitry, integrated into the active cable.
Jason does disclose the active cable (Fiber Optic cable, see Figure in Page 1) comprising first and second pluggable modules (Optical transceiver module circuit at both end of the cable, see Figure in Page 1) coupled by a physical medium (Optical signals, see Figure in Page 1); wherein the active cable further comprises hardware circuitry (Electronic connectors, see Figure in Page 1), integrated into the active cable.
At the time of the invention it would have been obvious to a person of ordinary skill in the art to incorporate Jason’s Active Optical Cable in Das/Paliwal modification.
The suggestion/motivation for doing so would have been to provide better support higher bandwidth communication (see Jason, 1st Paragraph in Page 1).
As to claim 19, the modification teaches the apparatus of claim 18, wherein the physical medium comprises a twinaxial cable (see Jason Figure in Page 1), a multimode fiber (MMF), or a single-mode fiber (SMF); and wherein the cable is configured to couple to the first entity or the second entity via a connector selected from Octal Small Form Factor Pluggable Module (OSFP), Octal Small Form Factor eXtra Dense Pluggable Module (OSFP-XD), Quad Small Form-Factor Pluggable (QSFP) (QSFP+, see Jason, Page 2), or Quad Small Form-Factor Pluggable Double Density (QSFP-DD).
Allowable Subject Matter
Claims 3-8, 16, and 25-30 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims; and if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph (and ODP), set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hyun Nam whose telephone number is (571) 270-1725 and fax number is (571) 270-2725. The examiner can normally be reached on Monday through Friday 8:30 AM to 5:00 PM EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on (571) 272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HYUN NAM/Primary Examiner, Art Unit 2183
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