DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112 2nd
The following is a quotation of the second paragraph of 35 U.S.C. 112:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 13, 18, and 27 are rejected under 35 U.S.C. 112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which applicant regards as the invention.
Claim 1 recites the limitation "the other" in line 8. There is insufficient antecedent basis for this limitation in the claim.
Claim 13 recites the limitation "the other" in line 12. There is insufficient antecedent basis for this limitation in the claim.
Claim 18 recites the limitation "the other" in line 11. There is insufficient antecedent basis for this limitation in the claim.
Claim 27 recites the limitation "the other" in line 7. There is insufficient antecedent basis for this limitation in the claim.
Applicant is required to review the claim and correct all language which does not comply with 35 U.S.C. § 112, second paragraph.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 13, 18, and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Das Sharma (U.S. Publication 2021/0240655), hereinafter Das in view of Paliwal et al. (U.S. Publication 2021/0112132), hereinafter Paliwal.
Referring to claim 1, Das teaches, as claimed, a method for translating between Peripheral Component Interconnect Express (PCIe) Transaction Layer Packets (TLPs), comprising:
receiving, from a first entity (see Fig. 9, Peripheral Device 904a), a first PCIe Memory Read request (split transactions, see Paragraphs 31 and 67 and Fig. 9, Memory 908a) comprising a first address (Address field, see Paragraph 40) and a first Tag (Tag field, see Paragraph 40);
translating, by a computer (see Fig. 9, CPU 902a), the first PCIe Memory Read request
sending, to a second entity (see Fig. 9, CPU 902b), the second PCIe Memory Read request (see Fig. 9, Memory 908b);
receiving, from the second entity, a second PCIe Completion (completion, see Paragraph 40) comprising the second Tag and a data payload (payload, see Paragraph 34);
translating, by the computer, the second PCIe Completion
sending, to the first entity, the first PCIe Completion.
Das does not disclose expressly translating to/from PCIe and another PCIe.
Paliwal does disclose translating to/from PCIe (see Fig. 6, PCIe Transaction Layer 615) and another PCIe (see Fig. 6, PCIe Transaction Layer 616).
At the time of the invention it would have been obvious to a person of ordinary skill in the art to incorporate Paliwal into Das.
The suggestion/motivation for doing so would have been to handle muti-protocols while backward compatibility.
Referring to claim 27, Das teaches, as claimed, a system for enabling Unordered Input/Output (UIO) transactions over
a first interface (see Fig. 9, PCIe) configured to operate in a first data stream mode and to communicate with a first entity (see Fig. 9, Peripheral Device 904a));
a second interface (see Fig. 9, PCIe+) configured to operate in a second data stream mode (Note, a normal mode) different from the first data stream mode and to communicate with a second entity (see Fig. 9, CPU 902b); wherein one of the first data stream mode and the second data stream mode comprises
a computer (see Fig. 9, CPU 902a) coupled between the first interface and the second interface (see Fig.9 ), the computer configured to:
receive, via the first interface, a first Peripheral Component Interconnect Express (PCIe) Transaction Layer (transaction layer, see Paragraph 31) Packet (TLP);
translate the first PCIe TLP TLP comprises a non-UIO TLP and the second PCIe TLP comprises a UIO TLP; and
send, via the second interface, the second PCIe TLP.
Das does not disclose expressly flit mode and translating to/from PCIe and another PCIe.
Paliwal does disclose flit mode (flit packing, Paragraph 44) translating to/from PCIe (see Fig. 6, PCIe Transaction Layer 615) and another PCIe (see Fig. 6, PCIe Transaction Layer 616).
At the time of the invention it would have been obvious to a person of ordinary skill in the art to incorporate Paliwal into Das.
The suggestion/motivation for doing so would have been to handle muti-protocols while backward compatibility.
As to claims 13 and 18, they are directed to a system/method to implement the method/system as set forth in claims 1 and 27 respectively. Therefore, they are rejected on the same basis as set forth hereinabove.
Allowable Subject Matter
Claims 2-12, 14-17, 19-26, and 28-29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims; and if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hyun Nam whose telephone number is (571) 270-1725 and fax number is (571) 270-2725. The examiner can normally be reached on Monday through Friday 8:30 AM to 5:00 PM EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on (571) 272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HYUN NAM/Primary Examiner, Art Unit 2183
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