Prosecution Insights
Last updated: October 26, 2026

Onasis Mora, USPTO Patent Examiner

Listed by the USPTO as MORA, ONASIS

Tech Center 4100 • Art Units: 2898 4100

This examiner grants 0% of resolved cases

Performance Statistics

—
Allow Rate
-60.0% vs TC avg
7
Total Applications
—
Interview Lift
0
Avg Prosecution Days
Based on 0 resolved cases, 2023–2026

Rejection Statute Breakdown

0%
§101 Eligibility
30.0%
§102 Novelty
70.0%
§103 Obviousness
0%
§112 Clarity

Currently Pending Office Actions

App #TitleStatusAssignee
18594049 SEMICONDUCTOR DEVICE Non-Final OA SAMSUNG ELECTRONICS CO., LTD.
18592860 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE Non-Final OA Kioxia Corporation
18598197 SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME Non-Final OA TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
18582953 MEMORY CELL STRUCTURES WITH GATE-CUT FEATURES ON CELL BOUNDARIES Non-Final OA Taiwan Semiconductor Manufacturing Company, Ltd.
18609511 NANOSTRUCTURE FIELD-EFFECT TRANSISTOR DEVICE AND METHODS OF FORMING Non-Final OA Taiwan Semiconductor Manufacturing Co., Ltd.

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Frequently Asked Questions

Which art unit does examiner Onasis Mora work in?

Onasis Mora examines applications in Art Unit 2898 in Tech Center 4100.

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