DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on August 22, 2025 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-7, 10, 11, 22-32, and 33-41 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1. Claim 1 recites the limitation " the first semiconductor wafer” and “the second semiconductor wafer" in the last paragraph of the claim language. There is insufficient antecedent basis for this limitation in the claim.
It is unclear to the examiner as to what is encompassed in the first and second semiconductor wafer structure.
For the purpose of examination and compact prosecution, Examiner shall interpret the first and second semiconductor wafer to be the first and second semiconductor wafer substrate.
Claims 1-7, 10, 11, 22-28, and 37, 38 are rejected for dependence upon a 112(b) rejected instance claim
Regarding claims 29. Claim 29 recites the limitation " the first semiconductor" in the second paragraph of the claim language. There is insufficient antecedent basis for this limitation in the claim.
For the purpose of examination and compact prosecution, Examiner shall interpret the first semiconductor to be the first semiconductor wafer substrate.
Claims 34 and 39 rejected for dependence upon a 112(b) rejected instance claim
Regarding claims 31. Claim 31 recites the limitation " the first semiconductor wafer structure” and “the second semiconductor wafer structure" in the last paragraph of the claim language. There is insufficient antecedent basis for this limitation in the claim.
It is unclear to the examiner as to what is encompassed in the first and second semiconductor wafer structure.
For the purpose of examination and compact prosecution, Examiner shall interpret the first and second semiconductor wafer structure to be the first and second semiconductor wafer substrate.
Claims 35 and 40 rejected for dependence upon a 112(b) rejected instance claim
Regarding claims 32. Claim 32 recites the limitation "the first semiconductor wafer” in the eleventh line of the claim language. There is insufficient antecedent basis for this limitation in the claim.
For the purpose of examination and compact prosecution, Examiner shall interpret the first semiconductor wafer to be the first semiconductor wafer substrate.
Claims 36 and 41 rejected for dependence upon a 112(b) rejected instance claim
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 7, 25, 26, 31 and 35 are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Gupta et al (U.S. 2005/0184304).
Regarding claim 1. Gupta et al discloses a method of forming a wafer level package (FIG. 1, item 10) comprising:
forming a microelectromechanical system structure (FIG. 1, item 30; Title; [0041]) and at least one pad (FIG. 1, item 36) on a first surface (FIG. 1, item 22) of a first semiconductor wafer substrate (FIG. 1, item 20; [0031]);
forming a second semiconductor wafer substrate (FIG. 1, item 40; [0033]) having a width (annotated FIG. 1, item 40 width) narrower (FIG. 1 Shows Width of item 40 is narrower than width of item 20) that a width (annotated FIG. 1, item 20 width) of the first semiconductor wafer (FIG. 1, item 20; [0031]).
forming a cavity (FIG. 1, item 50; [0029]) the second semiconductor wafer substrate (FIG. 1, item 40; [0033]); and
mounting the second semiconductor wafer substrate (FIG. 1, item 40) on the first surface (FIG. 1, item 22) of the first semiconductor wafer substrate (FIG. 1, item 20) after the cavity (FIG. 1, item 50) is formed such that the MEMS structure (FIG. 1, item 30) is positioned inside the a cavity (FIG. 1, item 50) in the second semiconductor wafer substrate (FIG. 1, item 200) and the at least one pad (FIG. 1, item 36) is positioned outside ([0031]) of the second semiconductor wafer (FIG. 1, item 40), at least one vertical sidewall (annotated FIG. 1, vertical sidewall of item 40) of the second semiconductor wafer (FIG. 1, item 40) being flush ([0014]; annotated FIG. 1 shows a vertical sidewall of item 40 is flush with a vertical sidewall of item 20; FIG. 7, item 112) with a vertical sidewall (annotated FIG. 1, vertical sidewall of item 20) of the first semiconductor wafer (FIG. 1, item 20).
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Regarding claim 7. Gupta et al discloses all the limitations of the method of claim 1 above.
Gupta et al further discloses wherein forming ([0033]) the cavity (FIG. 1, item 50) comprises etching ([0033], i.e. recesses may be formed in optical window 40 by etching) the cavity (FIG. 1, item 50) in the second semiconductor wafer (FIG. 1, item 40)
Regarding claim 25. Gupta et al discloses all the limitations of the method of claim 1 above.
Gupta et al further discloses wherein the MEMS structure (FIG. 1, item 30; Title; [0041]) and the at least one pad (FIG. 1, item 36) are formed on a non-recessed portion (FIG. 1, item 22 of item 20) of the first surface (FIG. 1, item 22).
Regarding claim 26. Gupta et al discloses all the limitations of the method of claim 1 above.
Gupta et al further discloses wherein the at least one pad (FIG. 1, item 36) has an uppermost surface (FIG. 1, item 36; [0053]) that is not coplanar ([0053]) with the first surface (FIG. 1, item 22) of the first semiconductor wafer substrate (FIG. 1, item 20).
Regarding claim 31. Gupta et al discloses a method comprising:
forming a microelectromechanical system (MEMS) structure (FIG. 1, item 30; Title; [0041]) and at least one pad (FIG. 1, item 36) on a first surface (FIG. 1, item 22) of a first semiconductor wafer substrate (FIG. 1, item 20);
forming a second semiconductor wafer substrate (FIG. 1, item 40; [0033]) having a width (annotated FIG. 1, item 40 width) less (FIG. 1 Shows Width of item 40 is narrower than width of item 20) that a width (annotated FIG. 1, item 20 width) of the first semiconductor wafer (FIG. 1, item 20; [0031]);
forming a cavity (FIG. 1, item 50; [0029]) the second semiconductor wafer substrate (FIG. 1, item 40; [0033]); and
mounting the second semiconductor wafer substrate (FIG. 1, item 40) on the first surface (FIG. 1, item 22) of the first semiconductor wafer substrate (FIG. 1, item 20), such that the MEMS structure (FIG. 1, item 30) is positioned inside the cavity (FIG. 1, item 50) in the second semiconductor wafer substrate (FIG. 1, item 40), the at least one pad (FIG. 1, item 36) is positioned on a portion (FIG. 1, item 22) of the first surface (FIG. 1, item 22) of the first semiconductor wafer substrate (FIG. 1, item 20) not covered by the second semiconductor wafer substrate (FIG. 1, item 40), and a vertical surface (annotated FIG. 1, vertical sidewall of item 40) of the second semiconductor wafer structure (FIG. 1, item 40; [0033]) being flush ([0029]; annotated FIG. 1 shows a vertical sidewall of item 40 is flush with a vertical sidewall of item 20; FIG. 7, item 112) with a vertical surface (annotated FIG. 1, vertical sidewall of item 20) of the first semiconductor wafer structure (FIG. 1, item 20).
Regarding claim 35. Gupta et al discloses all the limitations of claim 31 above.
Gupta et al further discloses wherein a portion formed on the first surface of the first semiconductor wafer substrate is bonded to a portion formed on a surface of the second semiconductor wafer substrate ([0035] Optical window 40 is attached either directly to or via a spacer 26 to substrate surface 22 of substrate 20 with, for example, a solder bond, a thermocompression bond, or other wafer-to-wafer bond such as a eutectic bond, a glass frit bond, a polymeric bond, or an adhesive bond).
Claims 1 and 31 are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Lee et al (U.S. 2004/0106294).
Regarding claim 1. Lee et al discloses a method of forming a wafer level package comprising:
forming a microelectromechanical system (MEMS) structure (FIG. 10B, item 300) and at least one pad (FIG. 10B, item 400a) on a first surface (FIG. 10B, top surface of item 200) of a first semiconductor wafer substrate (FIG. 10B, item 200);
forming a second semiconductor wafer substrate (FIG. 10A, item 100) having a width (FIG. 10A, a width of item 100) narrower (FIG. 10A, middle section of item 100 with cavities 120 width is less than the width of item 200 between items 400a) that a width (FIG. 10A, a width of item 200) of the first semiconductor wafer substrate (FIG. 10A, item 200);
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forming a cavity (FIG. 10A, item 140) in the second semiconductor wafer substrate (FIG. 10A, item 100); and
mounting the second semiconductor wafer substrate (FIG. 10B, item 100) on the first surface of the first semiconductor wafer substrate (FIG. 10B, item 200) such that the MEMS structure (FIG. 10B, item 300) is positioned inside the cavity (FIG. 10B, item 140) in the second semiconductor wafer substrate (FIG. 10B, item 100) and the at least one pad (FIG. 10B, item 400a) is positioned outside (FIG. 10B, shows item 400a is positioned outside the annotated width of item 100) the second semiconductor wafer (FIG. 10B, item 100),
and at least one vertical sidewall (annotated FIG. 10B, vertical sidewall of item 100) of the second semiconductor wafer (FIG. 10B, item 100) being flush (FIG. 10B shows show a vertical sidewall of item 100 is flush with a vertical sidewall of item 200) with a vertical sidewall (annotated FIG. 10B, vertical sidewall of item 200) of the first semiconductor wafer (FIG. 10B, item 200).
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Regarding claim 31. Lee et al discloses a method of forming a wafer level package comprising:
forming a microelectromechanical system (MEMS) structure (FIG. 10B, item 300) and at least one pad (FIG. 10B, item 400a) on a first surface (FIG. 10B, top surface of item 200) of a first semiconductor wafer substrate (FIG. 10B, item 200);
forming a second semiconductor wafer substrate (FIG. 10A, item 100) having a width less than a width (FIG. 10A, middle section of item 100 with cavities 120 width is less than the width of item 200 between items 400a) of the first semiconductor wafer substrate (FIG. 10A, item 200);
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forming a cavity (FIG. 10A, item 140) in the second semiconductor wafer substrate (FIG. 10A, item 100); and
mounting the second semiconductor wafer substrate (FIG. 10B, item 100) on the first surface of the first semiconductor wafer substrate (FIG. 10B, item 200) such that the MEMS structure (FIG. 10B, item 300) is positioned inside the cavity (FIG. 10B, item 140) in the second semiconductor wafer substrate (FIG. 10B, item 100) and the at least one pad (FIG. 10B, item 400a) is positioned on a portion of the first surface (FIG. 10B, top surface of item 200) of the first semiconductor wafer substrate (FIG. 10B, item 200) not covered (FIG. 10B, item 120) by the second semiconductor wafer substrate (FIG. 10B, item 100),
and a vertical surface (annotated FIG. 10B, vertical sidewall of item 100) of the second semiconductor wafer structure (FIG. 10B, item 100) being flush (FIG. 10B shows show a vertical sidewall of item 100 is flush with a vertical sidewall of item 200) with a vertical surface (annotated FIG. 10B, vertical sidewall of item 200) of the first semiconductor wafer structure (FIG. 10B, item 200).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2, 3, 27, 28 are rejected under 35 U.S.C. 103 as being unpatentable over Gupta et al (U.S. 2005/0184304) as applied to claim 1 above, and further in view of Chanchani et al (U.S. 8,597,985).
Regarding claim 2. Gupta et al discloses all the limitations of the method of claim 1 above.
Gupta et al further discloses further comprising thinning the semiconductor wafer substrate ([0057], i.e. optical window 40 is optionally planarized, for example, by lapping, grinding or polishing, to form a relatively flat outer surface 44,).
Gupta et al fails to explicitly disclose thinning the first semiconductor wafer.
However, Chanchani et al teaches thinning the first semiconductor wafer (FIG. 4B, item 51; thin MEMS).
Since both Gupta et al and Chanchani et al teach mems packaging, It would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method as disclosed to modify in Gupta et al with the thinning the first semiconductor wafer as disclosed by Chanchani et al. The use of thin MEMS in Chanchani et al provides for the predictable result of having wafer-level packaging for MEMS in a hermetic microenvironment, using wafer level processes such as eutectic bonding, Bosch etching and mechanical lapping and thinning, which are more cost-effective than processes required to produce the aforementioned through-silicon vias and membrane lids of the prior art (Chanchani et al, Col 2, lines 23-28).
Regarding claim 3. Gupta et al in view of Chanchani et al discloses all the limitations of the method of claim 2 above.
Gupta et al teaches wherein the mounting the second semiconductor wafer substrate comprises bonding portions of the second semiconductor wafer substrate of proper size, thickness and configuration ([0035]).
Gupta et al fails to explicitly disclose to sufficiently stabilize the first semiconductor wafer substrate during thinning to prevent cracking and warping of the first semiconductor wafer substrate.
However, Chanchani teaches wherein the mounting the second semiconductor wafer substrate (FIG. 4B, item 11) comprises bonding portions (Col 2, lines 55-58, i.e. the MEMS and lid wafers are then aligned, and their seal ring stacks are bonded (in vacuum or in a nitrogen environment in some embodiments) at or above the Au-Ge eutectic temperature) of a second semiconductor wafer substrate of proper size, thickness (FIG. 4B, item 11; Col 3, lines12-14, i.e. the lid wafer 11 has a diameter of 150 mm and a thickness of 675 um) and configuration to sufficiently stabilize the first semiconductor wafer substrate during thinning (FIG 4B, item 51; Col 5, lines 17-18, i.e. the MEMS wafer is first thinned to around 100 um) to prevent cracking and warping of the first semiconductor wafer substrate (FIG 4B, item 51; Col 2, lines 61-63, i.e. the MEMS-side of the bonded wafer assembly is thinned to about 100 um (or less) in some embodiments, with nearly scratch-free and crack-free surface).
Since both Gupta et al and Chanchani et al teach mems packaging, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method as disclosed to modify Gupta et al with the sufficiently stabilize the first semiconductor wafer substrate during thinning to prevent cracking and warping of the first semiconductor wafer substrate as disclosed by Chanchani et al. The use of sufficiently stabilize the first semiconductor wafer substrate during thinning to prevent cracking and warping of the first semiconductor wafer substrate MEMS-side of the bonded wafer assembly is thinned to about 100 um (or less) in some embodiments, with nearly scratch-free and crack-free surface in Chanchani et al provides for the predictable result of having wafer-level packaging for MEMS in a hermetic microenvironment, using wafer level processes such as eutectic bonding, Bosch etching and mechanical lapping and thinning, which are more cost-effective than processes required to produce the aforementioned through-silicon vias and membrane lids of the prior art (Chanchani et al, Col 2, lines 23-28).
Regarding claim 27. Gupta et al discloses all the limitations of the method of claim 1 above.
Gupta et al fails to explicitly disclose wherein mounting the second semiconductor wafer substrate on the first semiconductor wafer substrate forms a die having a thickness of 200-600um after a thinning operation is performed on the bottom surface of the first semiconductor wafer substrate.
However, Chanchani et al teaches wherein mounting the second semiconductor wafer substrate (FIG. 4B, item 11) on the first semiconductor wafer substrate (FIG. 4B, item 51) forms a die having a thickness of 200-600 um (Col 3, line 3-5, i.e. The resulting MEMS wafer/lid wafer assembly is sawed to produce individually packaged MEMS devices (having a thickness of 200 um or less) after a thinning operation (Col 2, lines58-59, i.e. The bonded wafers are then mechanically thinned and polished) is performed on the bottom surface (Col 2, lines 59-60, i.e. The MEMS-side of the bonded wafer assembly is thinned to about 100 um) of the first semiconductor wafer substrate (FIG. 4B, item 51).
Since both Gupta et al and Chanchani et al teach mems packaging, It would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the wafer level packaging as disclosed to modify Gupta et al with the teachings of the lateral void extending completely through the second semiconductor wafer substrate in the z direction as disclosed by Chanchani et al. The use of the lid wafer to open the ends of the cavities provides opening to completes the process of separating the lid wafer into individual lid portions for singulation wherein the wafer assembly is mounted on UV tape, and sawed to singulate the packaged MEMS devices in Chanchani et al provides for packaging MEMS devices using relatively low cost wafer level processes such as eutectic bonding, Bosch etching and mechanical lapping and thinning. This in turn provides for lower costs and higher production yields than are typically available with the aforementioned prior art technologies that require through-silicon vias or hermetic membranes (Chanchani et al, Col 5, lines 49-56).
“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Regarding claim 28. Gupta et al in view of Chanchani et al discloses all the limitations of the method of claim 27 above.
Chanchani et al further discloses wherein a ratio of the height of the second semiconductor wafer substrate (Col 3, lines 12-14; i.e. In some embodiments, the lid wafer 11 has a diameter of 150 mm and a thickness of 675 um ) to the height of the first semiconductor wafer substrate (Col 2, lines 59-60, i.e. The MEMS-side of the bonded wafer assembly is thinned to about 100 um (or less) in some embodiments) is approximately 3:1 to 10:1 (Col 3, 675 um : Col 2, 100 um) after a thinning operation is performed (Col 2, lines58-59, i.e. The bonded wafers are then mechanically thinned and polished) on the bottom surface (Col 2, lines 59-60, i.e. The MEMS-side of the bonded wafer assembly is thinned to about 100 um) of the first semiconductor wafer substrate (FIG. 4B, item 51).
Since both Gupta et al and Chanchani et al teach mems packaging, It would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method as disclosed to modify Gupta et al with the teachings of the wherein a ratio of the height of the second semiconductor wafer substrate to the height of the first semiconductor wafer substrate is between approximately 3:1 to 10:1, after a thinning operation is performed on the bottom surface of the first semiconductor wafer substrate as disclosed by Chanchani et al. The use of the lid wafer 11 has a diameter of 150 mm and a thickness of 675 um and the MEMS-side of the bonded wafer assembly is thinned to about 100 um (or less) in Chanchani et al provides for having wafer-level packaging for MEMS in a hermetic microenvironment, using wafer level processes such as eutectic bonding, Bosch etching and mechanical lapping and thinning, which are more cost-effective than processes required to produce the aforementioned through-silicon vias and membrane lids of the prior art (Chanchani et al, Col 2, lines 23-28).
“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Claims 2 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Gupta et al (U.S. 2005/0184304) as applied to claim 1 above, and further in view of Schaper et al (U.S. 2005/0006738).
Regarding claim 2. Gupta et al discloses all the limitations of the method of claim 1 above.
Gupta et al further discloses further comprising thinning the semiconductor wafer substrate ([0057], i.e. optical window 40 is optionally planarized, for example, by lapping, grinding or polishing, to form a relatively flat outer surface 44,).
Gupta et al fails to explicitly disclose thinning the first semiconductor wafer.
However, Schaper et al teaches thinning the first semiconductor wafer (FIG. 4, item 10; [0034], i.e. as shown in FIG. 4, a substantial lower portion of the silicon substrate 10 is removed in a thinning operation by back-grinding and/or plasma etching).
Since both Gupta et al and Schaper et al teach MEMS packaging, It would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method as disclosed to modify Gupta et al with the teachings of the thinning the first semiconductor wafer as disclosed by Schaper et al. All the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. The use of a substantial lower portion of the silicon substrate is removed in a thinning operation by back-grinding and/or plasma etching in Schaper provides for the predictable result of having an improved package for MEMS and other devices in accordance with the invention can provide, as desired, a physical housing to protect the device, functional interconnects to mechanical systems, avenues for managing by-products like heat and for reducing functional losses like insertion loss of the system, and electrical interfaces to electronic control system (Schaper et al, page1, 5th paragraph).
Regarding claim 10. Gupta et al in view of Schaper et al discloses all the limitations of the method of claim 2 above.
Schaper et al discloses wherein said thinning the first semiconductor wafer substrate comprises etching the first semiconductor wafer substrate (FIG. 4, item 10; [0034], i.e. as shown in FIG. 4, a substantial lower portion of the silicon substrate 10 is removed in a thinning operation by back-grinding and/or plasma etching ).
Since both Gutpa et al and Schaper et al teach MEMS packaging, It would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method as disclosed to modify Gupta et al with thinning the first semiconductor wafer substrate comprises etching the first semiconductor wafer substrate as disclosed by Schaper et al. All the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. The use of a substantial lower portion of the silicon substrate is removed in a thinning operation by back-grinding and/or plasma etching in Schaper provides for the predictable result of having an improved package for MEMS and other devices in accordance with the invention can provide, as desired, a physical housing to protect the device, functional interconnects to mechanical systems, avenues for managing by-products like heat and for reducing functional losses like insertion loss of the system, and electrical interfaces to electronic control system (Schaper et al, page1, 5th paragraph).
Claims 4 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Gupta et al (U.S. 2005/0184304) as applied to claim 1 above, and further in view of Fazzio et al (U.S. 2008/0144863).
Regarding claim 4. Gupta et al disclose all the limitations of the method of claim 1 above.
Gupta et al discloses the MEMS structure (FIG. 1, item 30; Title; [0041]).
Gupta et al fail to explicitly disclose further comprising forming a hole through the first semiconductor wafer substrate that exposes the MEMS structure.
However, Fazzio et al teaches further comprising forming a hole (FIG. 2B, item 103) through the first semiconductor wafer substrate (FIG. 2B, item 101) that exposes the MEMS structure (FIG. 2B, item 102; Page 2, ¶ [0030], i.e. the mic 102 may be a cantilevered piezoelectric structure such as described in U.S. Pat. No. 6,438,697 entitled "Cavity Spanning Bottom Electrode of Substrate Mounted Bulk Wave Acoustic Resonator").
Since both Gupta et al and Fazzio et al teach MEMS, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method as disclosed to modify Gupta et al with the forming a hole through the first semiconductor wafer substrate that exposes the MEMS structure as disclosed by Fazzio et al. The use of Cavity Spanning Bottom Electrode of Substrate Mounted Bulk Wave Acoustic Resonator in Fazzio et al provides for the predictable result of having overcome the comparatively labor-intensive and costly manufacturing and packaging of micromachined transducers (Fazzio et al, [0003-0004]).
Regarding claim 11. Gutpa et al and further view of Fazzio disclose all the limitations of the method of claim 4 above.
Gupta et al discloses the MEMS structure (FIG. 1, item 30; Title; [0041]).
Gutpa et al fail to disclose wherein the forming the hole through the first semiconductor wafer substrate that exposes the MEMS structure comprises etching the hole that exposes the MEMS structure.
However, Fazzio et al teaches wherein forming the hole (FIG. 2B, item 103; Page 2, ¶ [0029], first sentence, i.e. the cavity 103 may be formed by one of a variety of known dry or wet etching methods) through the first semiconductor wafer substrate (FIG 2B, item 101) that exposes (Page 2, ¶ [0028], last sentence, removal of a portion of the substrate 101 to provide the cavity 103, results in vibration of the membrane of the mic 102) the MEMS structure (FIG. 2B, item 102; Page 2, ¶ [0030], i.e. the mic 102 may be a cantilevered piezoelectric structure such as described in U.S. Pat. No. 6,438,697 entitled "Cavity Spanning Bottom Electrode of Substrate Mounted Bulk Wave Acoustic Resonator") comprises etching the hole (Page 1, ¶ [0006], i.e. etching the cavity) that exposes the MEMS structure (FIG. 2B, item 102; Page 2, ¶ [0030], i.e. the mic 102 may be a cantilevered piezoelectric structure such as described in U.S. Pat. No. 6,438,697 entitled "Cavity Spanning Bottom Electrode of Substrate Mounted Bulk Wave Acoustic Resonator").
Since both Gupta et al and Fazzio et al teach MEMS,It would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method as disclosed to modify Gupta et al with the teachings of the forming the hole through the first semiconductor wafer substrate that exposes the MEMS structure comprises etching the hole that exposes the MEMS structure as disclosed by Fazzio et al. The use of etching the cavity, removal of a portion of the substrate 101 to provide the cavity 103, results in vibration of the membrane of the mic, the mic may be a cantilevered piezoelectric structure such as described in U.S. Pat. No. 6,438,697 entitled "Cavity Spanning Bottom Electrode of Substrate Mounted Bulk Wave Acoustic Resonator” in Fazzio et al provides for the predictable result of having overcome the comparatively labor-intensive and costly manufacturing and packaging of micromachined transducers (Fazzio et al, [0003-0004]).
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Gupta et al (U.S. 2005/0184304) as applied to claim 1 above, and further in view of Sengupta (U.S. 2009/0134481).
Regarding claims 5-6. Gupta et al discloses all the limitations of the method of claim 1 above.
Gupta et al discloses the first semiconductor wafer substrate (FIG. 1, item 20) and the at least one pad (FIG. 1, item 36) on the first semiconductor wafer substrate (FIG. 1, item 20).
Gupta et al fails to explicitly disclose further comprising mounting the first substrate on a die attachment pad portion of a leadframe and connecting the at least one pad on the first substrate to at least one lead of the leadframe with at least one bond wire, covering the first and second semiconductor wafer substrates, the at least one bond wire, and at least a portion of the leadframe with encapsulant.
However, Sengupta teaches discloses further comprising mounting the first semiconductor wafer substrate (FIG. 3, item 14) on a die attachment pad portion (FIG. 3, item 24) of a leadframe (FIG. 3, item 22) and connecting ([0028], i.e. the sensor assembly (e.g., the MEMS sensor 14 and/or the cap 16) may be electrically connected to the base 22 using an electrical connection 30, such as leads and wire bonds or solder bumps) the at least one pad (FIG. 3, portion of item 30 directly electrically connected to item 32) on the first semiconductor wafer substrate ( FIG. 3, item 32) to at least one lead (FIG. 3, item 24) of the leadframe (FIG. 3, item 22) with at least one bond wire (FIG. 3, item 30), covering the first (FIG. 3, item 32) and second semiconductor wafer (FIG. 3, item 16) substrates, the at least one bond wire (FIG. 3, item 30), and at least a portion (FIG. 3, item 24) of the leadframe (FIG. 3, item 22) with encapsulant (FIG. 3, item 34; [0034], i.e. moldable material 34 may contact a portion of the assembled layers and the electrical connection(s) 30 and mold them together in a molding step).
Since both Gupta et al and Sengupta teach MEMS devices, It would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method of forming a wafer level package as disclosed to modify Gupta et al with the teachings of the comprising mounting the first semiconductor wafer substrate on a die attachment pad portion of a leadframe and connecting the at least one pad on the first semiconductor wafer substrate to at least one lead of the leadframe with at least one bond wire as disclosed by Sengupta. All the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. The use of the sensor assembly (e.g., the MEMS sensor and/or the cap) may be electrically connected to the base using an electrical connection, such as leads and wire bonds or solder bumps and moldable material may contact a portion of the assembled layers and the electrical connection(s) and mold them together in a molding step in Sengupta provides for the interior area being substantially free of the moldable material (Sengupta, [abstract]).
Claims 5, 6, 23, 37, and 38 are rejected under 35 U.S.C. 103 as being unpatentable over Gupta et al (U.S. 2005/0184304) as applied to claim 1 above, and further in view of Ramos et al (U.S. 2008/0258278).
Regarding claim 5. Gupta et al discloses all the limitations of the method of claim 1 above.
Gupta et al discloses the first semiconductor wafer substrate (FIG. 1, item 20) and the at least one pad (FIG. 1, item 36) on the first semiconductor wafer substrate (FIG. 1, item 20).
Gupta et al fails to explicitly disclose further comprising mounting the first substrate on a die attachment pad portion of a leadframe and connecting the first substrate to at least one lead of the leadframe with at least one bond wire.
However, Ramos teaches discloses further comprising mounting the first semiconductor wafer substrate (FIG. 38, item 1220) on a die attachment pad portion (FIG. 38, item 1210) of a leadframe (FIG. 38, item 1210) and connecting ([abstract], i.e. a partially patterned strip of metal formed into a web-like lead frame on one side so that the web-like lead frame is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level) the first semiconductor wafer substrate ( FIG. 38, item 1220) to at least one lead (FIG. 38, item 1205) of the leadframe (FIG. 38, item 1220) with at least one bond wire (FIG. 38, item 1225).
Since both Gupta et al and Ramos teach packaging devices, It would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method of forming a wafer level package as disclosed to modify Gupta et al with the teachings of mounting the first substrate on a die attachment pad portion of a leadframe and connecting the first substrate to at least one lead of the leadframe with at least one bond wire as disclosed by Ramos et al. All the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. The use of a partially patterned strip of metal formed into a web-like lead frame on one side so that the web-like lead frame is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level in Ramos et al provides for resultant package being electrically isolated enables strip testing and reliable singulation (Ramos, [abstract]).
Regarding claim 6. Gupta et al in view of Ramos et al discloses all the limitations of the method of claim 5 above.
Gupta et al teaches the first (FIG. 1, item 20) and second (FIG. 1, item 40) semiconductor wafer substrates.
Ramos et al further discloses further comprising covering the first (FIG. 38, item 1220) and second semiconductor (FIG. 38, item 1250) wafer substrates, the at least one bond wire (FIG. 38, item 1225), and at least a portion of the leadframe (FIG. 38, item 1210 and 1205) with encapsulant (FIG. 38. item 1230).
Regarding claim 23. Gupta et al in view of Ramos et al discloses all the limitations of the method of claim 5 above.
Gupta et al discloses the first semiconductor wafer substrate (FIG. 1, item 20).
Ramos et al further discloses comprising using an epoxy die attachment film (FIG. 38, item 1215) to mount the first semiconductor wafer substrate (FIG. 38, item 1220) on the die attachment pad portion (FIG 38, item 1210) of a leadframe. (FIG 38, item 1210).
Regarding claim 37. Gupta et al discloses all the limitations of the method of claim 1 above.
Gupta et al fails to explicitly disclose further including covering the second semiconductor wafer structure and exposed portions of the first semiconductor wafer substrate and the pad with an encapsulation material.
Ramos et al further discloses further including covering ([Abstract], i.e. the chip and wires, is hermetically sealed with an encapsulant) the second semiconductor wafer structure (FIG 38, item 1250) and exposed portions (FIG 38, item 1220) of the first semiconductor wafer substrate (FIG. 38, item 1210), and the pad ([0173], i.e. The chips (1220, 1250) are electrically connected to the electrical leads (1205) via wire bonding (1225)) with an encapsulation material (FIG. 38, item 1230).
Since both Gupta et al and Ramos teach packaging devices, It would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method of forming a wafer level package as disclosed to modify Gupta et al with the teachings of covering the second semiconductor wafer structure and exposed portions of the first semiconductor wafer substrate and the pad with an encapsulation material as disclosed by Ramos et al. All the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. The use of the chip and wires, is hermetically sealed with an encapsulant in Ramos et al provides for resultant package being electrically isolated enables strip testing and reliable singulation (Ramos, [abstract]).
Regarding claim 38. Gupta et al in view of Ramos et al discloses all the limitations of the method of claim 5 above.
Ramos et al further discloses further including covering the second semiconductor wafer structure (FIG 38, item 1250), the bond wire (FIG. 38, item 1225) and exposed portions (FIG 38, item 1220) of the first semiconductor wafer substrate (FIG. 38, item 1210), the pad ([0173], i.e. The chips (1220, 1250) are electrically connected to the electrical leads (1205) via wire bonding (1225)) and the at least one lead (FIG. 38, item 1205) of the leadframe (FIG. 38, item 1210) with an encapsulation material (FIG. 38, item 1230).
Claim 40 is rejected under 35 U.S.C. 103 as being unpatentable over Gupta et al (U.S. 2005/0184304) as applied to claim 31 above, and further in view of Ramos et al (U.S. 2008/0258278).
Regarding claim 40. Gupta et al discloses all the limitations of the method of claim 31 above.
Gupta et al fails to explicitly disclose further including covering the second semiconductor wafer structure and exposed portions of the first semiconductor wafer substrate and the pad with an encapsulation material.
Ramos et al further discloses further including covering ([Abstract], i.e. the chip and wires, is hermetically sealed with an encapsulant) the second semiconductor wafer structure (FIG 38, item 1250) and exposed portions (FIG 38, item 1220) of the first semiconductor wafer substrate (FIG. 38, item 1210), and the pad ([0173], i.e. The chips (1220, 1250) are electrically connected to the electrical leads (1205) via wire bonding (1225)) with an encapsulation material (FIG. 38, item 1230).
Since both Gupta et al and Ramos teach packaging devices, It would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method of forming a wafer level package as disclosed to modify Gutpa et al with the teachings of covering the second semiconductor wafer structure and exposed portions of the first semiconductor wafer substrate and the pad with an encapsulation material as disclosed by Ramos et al. All the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. The use of the chip and wires, is hermetically sealed with an encapsulant in Ramos et al provides for resultant package being electrically isolated enables strip testing and reliable singulation (Ramos, [abstract]).
Claims 4 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (U.S. 2004/1016294) as applied to claim 1 above, and further in view of Fazzio et al (U.S. 2008/0144863).
Regarding claim 4. Lee et al disclose all the limitations of the method of claim 1 above.
Lee et al discloses the MEMS structure (FIG. 10B, item 300).
Lee et al fail to explicitly disclose further comprising forming a hole through the first semiconductor wafer substrate that exposes the MEMS structure.
However, Fazzio et al teaches further comprising forming a hole (FIG. 2B, item 103) through the first semiconductor wafer substrate (FIG. 2B, item 101) that exposes the MEMS structure (FIG. 2B, item 102; Page 2, ¶ [0030], i.e. the mic 102 may be a cantilevered piezoelectric structure such as described in U.S. Pat. No. 6,438,697 entitled "Cavity Spanning Bottom Electrode of Substrate Mounted Bulk Wave Acoustic Resonator").
Since both Lee et al and Fazzio et al teach MEMS, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method as disclosed to modify Lee et al with the forming a hole through the first semiconductor wafer substrate that exposes the MEMS structure as disclosed by Fazzio et al. The use of Cavity Spanning Bottom Electrode of Substrate Mounted Bulk Wave Acoustic Resonator in Fazzio et al provides for the predictable result of having overcome the comparatively labor-intensive and costly manufacturing and packaging of micromachined transducers (Fazzio et al, [0003-0004]).
Regarding claim 11. Lee et al and further view of Fazzio disclose all the limitations of the method of claim 4 above.
Lee et al discloses the MEMS structure (FIG. 10B, item 300).
Lee et al fail to disclose wherein the forming the hole through the first semiconductor wafer substrate that exposes the MEMS structure comprises etching the hole that exposes the MEMS structure.
However, Fazzio et al teaches wherein forming the hole (FIG. 2B, item 103; Page 2, ¶ [0029], first sentence, i.e. the cavity 103 may be formed by one of a variety of known dry or wet etching methods) through the first semiconductor wafer substrate (FIG 2B, item 101) that exposes (Page 2, ¶ [0028], last sentence, removal of a portion of the substrate 101 to provide the cavity 103, results in vibration of the membrane of the mic 102) the MEMS structure (FIG. 2B, item 102; Page 2, ¶ [0030], i.e. the mic 102 may be a cantilevered piezoelectric structure such as described in U.S. Pat. No. 6,438,697 entitled "Cavity Spanning Bottom Electrode of Substrate Mounted Bulk Wave Acoustic Resonator") comprises etching the hole (Page 1, ¶ [0006], i.e. etching the cavity) that exposes the MEMS structure (FIG. 2B, item 102; Page 2, ¶ [0030], i.e. the mic 102 may be a cantilevered piezoelectric structure such as described in U.S. Pat. No. 6,438,697 entitled "Cavity Spanning Bottom Electrode of Substrate Mounted Bulk Wave Acoustic Resonator").
Since both Gupta et al and Fazzio et al teach MEMS,It would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method as disclosed to modify Lee et al with the teachings of the forming the hole through the first semiconductor wafer substrate that exposes the MEMS structure comprises etching the hole that exposes the MEMS structure as disclosed by Fazzio et al. The use of etching the cavity, removal of a portion of the substrate 101 to provide the cavity 103, results in vibration of the membrane of the mic, the mic may be a cantilevered piezoelectric structure such as described in U.S. Pat. No. 6,438,697 entitled "Cavity Spanning Bottom Electrode of Substrate Mounted Bulk Wave Acoustic Resonator” in Fazzio et al provides for the predictable result of having overcome the comparatively labor-intensive and costly manufacturing and packaging of micromachined transducers (Fazzio et al, [0003-0004]).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (U.S. 2004/1016294) as applied to claim 1 above, and further in view of Tabrizi (U.S. 2010/0244161).
Regarding claim 22. Lee et al discloses all the limitations of the method of claim 1 above.
Lee et al discloses the MEMS structure (FIG. 10B, item 300)
Lee et al fails to explicitly disclose wherein the MEMS structure includes a bulk acoustic wave (BAW) filter.
However, Tabrizi teaches wherein the MEMS structure includes a bulk acoustic wave (BAW) filter ([0043], i.e. device package according to various embodiments may include RFICs, MEMS devices such as SAW or BAW filters, pressure sensors or accelerometers, or any of multiple other types of devices known in the art).
Since Both Lee et al and Tabrizi teach MEMS devices, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method as disclosed to modify Lee et al with the MEMS structure includes a bulk acoustic wave (BAW) filter as disclosed by Tabrizi. The use of device package according to various embodiments may include RFICs, MEMS devices such as SAW or BAW filters, pressure sensors or accelerometers, or any of multiple other types of devices known in the art in Tabrizi provides for a device package with a small overall height be desired, for example, for inclusion in an ultra-thin laptop or cell phone (Tabrizi, [0050]).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (U.S. 2004/1016294) as applied to claim 1 above, and further in view of Thompson et al (U.S. 2007/0269934).
Regarding claim 24. Lee et al discloses all the limitations of the method of claim 1 above.
Lee fails to explicitly disclose wherein the first surface of the first semiconductor wafer substrate is planar.
However, Thompson et al teaches wherein the first surface of the first semiconductor wafer substrate is planar ([0045], i.e. tolerance associated with the grinding process may be about +/-25 um across the width of a six inch wafer).
Since Both Lee et al and Thompson et al teach MEMS devices, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method as disclosed to modify Lee et al with the wherein the first surface of the first semiconductor wafer substrate is planar as disclosed by Tabrizi. The use of tolerance associated with the grinding process may be about +/-25 um across the width of a six inch wafer in Thompson provides for a tolerance requirements only to assure that a sufficient thickness of lid material remains to provide an uncompromised seal over the MEMS device (Thompson [0050]).
Claims 29-30, 32, 34 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Gupta et al (U.S. 2005/0184304), and further in view of Chanchani et al (U.S. 8,597,985).
Regarding claim 29. Gupta et al discloses a method of forming a wafer level package (FIG. 1, item 10) comprising:
forming a microelectromechanical system (MEMS) structure (FIG. 1, item 30; Title; [0041]) and at least one pad (FIG. 1, item 36) on a first surface (FIG. 1, item 22) of a first semiconductor wafer substrate (FIG. 1, item 20; [0031]);
forming a cavity (FIG. 1, item 50; [0029]) in a second semiconductor wafer substrate (FIG. 1, item 40; [0033]), the second semiconductor wafer substrate (FIG. 1, item 40; [0033]) having a width (annotated FIG. 1, item 40 width) narrower (FIG. 1 Shows Width of item 40 is narrower than width of item 20) than a width (annotated FIG. 1, item 20 width) of the first semiconductor wafer (FIG. 1, item 20; [0031]).
mounting the second semiconductor wafer substrate (FIG. 1, item 40) on the first surface (FIG. 1, item 22) of the first semiconductor wafer substrate (FIG. 1, item 20) such that the MEMS structure (FIG. 1, item 30) is positioned inside the cavity (FIG. 1, item 50) in the second semiconductor wafer substrate (FIG. 1, item 20) and the pad (FIG. 1, item 36) is positioned outside ([0031]) of the second semiconductor wafer substrate(FIG. 1, item 40), at least one vertical surface (annotated FIG. 1, vertical sidewall of item 40) of the second semiconductor wafer substrate (FIG. 1, item 40) being flush ([0014]; annotated FIG. 1 shows a vertical sidewall of item 40 is flush with a vertical sidewall of item 20; FIG. 7, item 112) with a corresponding vertical surface (annotated FIG. 1, vertical sidewall of item 20) of the first semiconductor wafer substrate (FIG. 1, item 20).
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thinning the semiconductor wafer substrate ([0057], i.e. optical window 40 is optionally planarized, for example, by lapping, grinding or polishing, to form a relatively flat outer surface 44).
Gupta et al fails to explicitly disclose thinning a second surface of the first semiconductor wafer after the second semiconductor wafer is mounted on the first semiconductor wafer substrate.
However, Chanchani et al teaches thinning (FIG. 4B, thin MEMS) a second surface (FIG. 4B, arrows pointing to bottom of item 51) of the first semiconductor wafer substrate (FIG. 4B, item 51) after the second semiconductor wafer substrate (FIG. 4B, item 11) is mounted on the first semiconductor wafer substrate (FIG. 4B, item 51).
Chanchani states in their specification in column 2, lines 23-28, that the present work provides wafer-level packaging for MEMS in a hermetic microenvironment, using wafer level processes such as eutectic bonding, Bosch etching and mechanical lapping and thinning, which are more cost-effective than processes required to produce the aforementioned through-silicon vias and membrane lids of the prior art.
Since both Gupta et al and Chanchani et al teach mems packaging, It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the disclosure of Gupta et al with the teachings of Chanchani to incorporate the alignment and eutectic bonding of the substrates together for rigidity and 150 mm wafer of 675 um thickness for stability during thinning as taught by Chanchani to mount the second semiconductor wafer substrate on the first semiconductor wafer substrate as disclosed by Gupta et al. The use of the wafer thinning in Chanchani provides wafer-level packaging for MEMS in a hermetic microenvironment, using wafer level processes such as eutectic bonding, Bosch etching and mechanical lapping and thinning, which are more cost-effective than processes required to produce the aforementioned through-silicon vias and membrane lids of the prior art (Chanchani, column 2, lines 23-28).
Regarding claim 30. Gupta et al in view of Chanchani et al discloses all the limitations of the method of claim 29 above.
Gupta et al further discloses wherein the at least one pad (FIG. 1, item 36) is not formed under ([0031], Electrical traces carry the control signals from electrical bond pads 36 into sealed cavity 50 and to actuatable micromirrors 30) the MEMS structure (FIG. 1, item 30).
Regarding claim 32. Gupta et al discloses a method of forming a wafer level package comprising:
forming a microelectromechanical system (MEMS) structure (FIG. 1, item 30; Title; [0041]) and at least one pad (FIG. 1, item 36) on a first surface (FIG. 1, item 22) of a first semiconductor wafer substrate (FIG. 1, item 20; [0031]) having a width (annotated FIG. 1, item 40 width) greater (FIG. 1 Shows Width of item 40 is narrower than width of item 20) than a width (annotated FIG. 1, item 20 width) of the second semiconductor wafer substrate(FIG. 1, item 40; [0033]).
forming a cavity (FIG. 1, item 50; [0029]) in a second semiconductor wafer substrate (FIG. 1, item 40; [0033]);
mounting the second semiconductor wafer substrate (FIG. 1, item 40) on the first surface (FIG. 1, item 22) of the first semiconductor wafer substrate (FIG. 1, item 20) such that the MEMS structure (FIG. 1, item 30) is positioned inside the cavity (FIG. 1, item 50) in the second semiconductor wafer substrate (FIG. 1, item 20), the at least one pad (FIG. 1, item 36) is positioned on a portion ([0031]) of the first surface (FIG. 1, item 22) of the first semiconductor wafer substrate (FIG. 1, item 20) not covered by the second semiconductor wafer substrate (FIG. 1, item 40), and a vertical surface (annotated FIG. 1, vertical sidewall of item 40) of the second semiconductor wafer (FIG. 1, item 40) is flush ([0014]; annotated FIG. 1 shows a vertical sidewall of item 40 is flush with a vertical sidewall of item 20; FIG. 7, item 112) with a vertical surface (annotated FIG. 1, vertical sidewall of item 20) of the first semiconductor wafer (FIG. 1, item 20).
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Gupta et al fails to explicitly disclose thinning a second surface of the first semiconductor wafer after the second semiconductor wafer is mounted on the first semiconductor wafer substrate.
However, Chanchani et al teaches thinning (FIG. 4B, thin MEMS) a second surface (FIG. 4B, arrows pointing to bottom of item 51) of the first semiconductor wafer substrate (FIG. 4B, item 51) after the second semiconductor wafer substrate (FIG. 4B, item 11) is mounted on the first semiconductor wafer substrate (FIG. 4B, item 51).
Chanchani states in their specification in column 2, lines 23-28, that the present work provides wafer-level packaging for MEMS in a hermetic microenvironment, using wafer level processes such as eutectic bonding, Bosch etching and mechanical lapping and thinning, which are more cost-effective than processes required to produce the aforementioned through-silicon vias and membrane lids of the prior art.
Since both Gupta et al and Chanchani et al teach MEMS packaging, It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the disclosure of Gupta et al with the teachings of Chanchani to incorporate the alignment and eutectic bonding of the substrates together for rigidity and 150 mm wafer of 675 um thickness for stability during thinning as taught by Chanchani to mount the second semiconductor wafer substrate on the first semiconductor wafer substrate as disclosed by Gupta et al. The use of the wafer thinning in Chanchani provides wafer-level packaging for MEMS in a hermetic microenvironment, using wafer level processes such as eutectic bonding, Bosch etching and mechanical lapping and thinning, which are more cost-effective than processes required to produce the aforementioned through-silicon vias and membrane lids of the prior art (Chanchani, column 2, lines 23-28).
Regarding claim 34. Gupta et al and Chanchani et al discloses all the limitations of claim 29 above.
Gupta et al further discloses wherein a portion formed on the first surface of the first semiconductor wafer substrate is bonded to a portion formed on a surface of the second semiconductor wafer substrate ([0035] Optical window 40 is attached either directly to or via a spacer 26 to substrate surface 22 of substrate 20 with, for example, a solder bond, a thermocompression bond, or other wafer-to-wafer bond such as a eutectic bond, a glass frit bond, a polymeric bond, or an adhesive bond).
Regarding claim 36. Gupta et al and Chanchani et al discloses all the limitations of claim 32 above.
Gupta et al further discloses wherein a portion formed on the first surface of the first semiconductor wafer substrate is bonded to a portion formed on a surface of the second semiconductor wafer substrate ([0035] Optical window 40 is attached either directly to or via a spacer 26 to substrate surface 22 of substrate 20 with, for example, a solder bond, a thermocompression bond, or other wafer-to-wafer bond such as a eutectic bond, a glass frit bond, a polymeric bond, or an adhesive bond).
Claims 39 and 41 are rejected under 35 U.S.C. 103 as being unpatentable over Gupta et al (U.S. 2005/0184304) and Chanchani et al (U.S. 8,597,985) as applied to claims 29, and 32 above, and further in view of Ramos et al (U.S. 2008/0258278).
Regarding claims 39 and 41. Gupta et al and Chanchani et al discloses all the limitations of claims 29, and 32 above.
Gupta et al and Chanchani et al fails to explicitly disclose further including covering the second semiconductor wafer structure and exposed portions of the first semiconductor wafer substrate and the pad with an encapsulation material.
However, Ramos et al discloses further including covering ([Abstract], i.e. the chip and wires, is hermetically sealed with an encapsulant) the second semiconductor wafer structure (FIG 38, item 1250) and exposed portions (FIG 38, item 1220) of the first semiconductor wafer substrate (FIG. 38, item 1210), and the pad ([0173], i.e. The chips (1220, 1250) are electrically connected to the electrical leads (1205) via wire bonding (1225)) with an encapsulation material (FIG. 38, item 1230).
Since Gupta et al, Chanchani et al and Ramos teach packaging devices, It would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method of forming a wafer level package as disclosed to modify Gupta et al and Chanchani et al with the teachings of covering the second semiconductor wafer structure and exposed portions of the first semiconductor wafer substrate and the pad with an encapsulation material as disclosed by Ramos et al. All the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. The use of the chip and wires, is hermetically sealed with an encapsulant in Ramos et al provides for resultant package being electrically isolated enables strip testing and reliable singulation (Ramos, [abstract]).
Response to Arguments
Applicant's arguments filed August 22, 2025 have been fully considered but they are not persuasive.
5) Regarding claim 31 102(a)(1)/102(a)(2)) rejected under Lee et al (U.S. 2004/0106294)
On pages 21-25 of applicant’s remarks applicant appears to be arguing that Lee fails to disclose applicant’s amended claim limitation of having a width less than a width of the first semiconductor wafer substrate and alleges that Lee’s Figures 10C and 10D do not disclose applicant’s invention.
Examiner respectfully points out that FIGs 10C and 10D were not used in the rejection and that FIGS 10A and 10B were used.
Applicant further remarks that Lee is only a continuous upper substrate and is not a width of applicant’s invention.
Examiner respectfully points that applicant’s disclosure does not define with any particular dimension of applicant’s disclosure that is “a width” to any particular dimension of applicant’s invention. Under broadest reasonable interpretations, Lee discloses applicant’s invention. Lee shows the width of the upper wafer is shorter the lower wafer between the pads that encompasses the cavity.
Regarding claims 1, 7, 8, 21, 24-26, & 31, under Thompson et al (U.S. 2007/0269934), claims 29 - 32 rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chanchani et al (U.S. 8,597,985), claim 31 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Humpston et al (WO 2007059193), claims 2, 3, 27, 28, rejected under 35 U.S.C. 103 being obvious over Thompson et al (U.S. 2007/0269934) as applied to claim 1 above and Chanchani (U.S. 8,597,985), claims 29, 30, and 32 rejected under 35 U.S.C. 103 being obvious over Thompson et al (U.S. 2007/0269934) and Chanchani (U.S. 8,597,985), claims 4 and 11 rejected under 35 U.S.C. 103 being obvious over Thompson et al (U.S. 2007/0269934) as applied to claim 1 above and Fazzio et al (U.S. 2008/0269934), claims 2 and 10 rejected under 35 U.S.C. 103 being obvious over Thompson et al (U.S. 2007/0269934) as applied to claim 1 above and Schaper et al (U.S. 2005/0006738), claims 5, 6 rejected under 35 U.S.C. 103 being obvious over Thompson et al (U.S. 2007/0269934) and Sangupta et al (U.S. 2009/0134481), claims 5, 6, 23, 37, 38, and 40 rejected under 35 U.S.C. 103 being obvious over Thompson et al (U.S. 2007/0269934) and Ramos et al (U.S. 2008/0258278), claims 22, 27, 28 rejected under 35 U.S.C. 103 being obvious over Thompson et al (U.S. 2007/0269934) as applied to claim 1 above, and further in view of Tabrizi et al (U.S. 2010/0244161),claims 34-36 rejected under 35 U.S.C. 103 being obvious over Chanchani et al (U.S. 8,597,985) as applied to claims 29, 31, 32 above, and further in view of Peng (U.S. 2011/0014750), claims 39-41 rejected under 35 U.S.C. 103 being obvious over Chanchani et al (U.S. 8,597,985) and Ramos et al (U.S. 2008/0258278).
On pages 81-83 of applicant’s remarks, applicant appears to be arguing that Chanchani et al in view of Ramos et al fail to disclose claims 39-41.
Applicant’s arguments with respect to claims recited have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/S.E.B./Examiner, Art Unit 2815
/JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815