DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/26/2026 has been entered.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-3, 13, 16-21, 30-32, 39-42, 44, 45, 47, and 48 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chaparala et al. (US 2015/0221571 A1) in view of Topaloglu (US 2009/0097186 A1) and Tong (US 2014/0370658).
Regarding claim 1, Chaparala discloses a bonded structure (Fig. 1) comprising:
an element (10-2 in Fig. 1 of Chaparala) having a lateral contact surface (bottom surface) including first and fourth conductive features (any two of the multiple conductive features shown in Fig. 1), and a first nonconductive region (nonconductive interstitial region between the conductive features along the bottom surface of 10-2 in Fig. 1 of Chaparala); and
a passive electronic component (102 in Fig. 1 of Chaparala) bonded to the element (see Fig. 1).
Chaparala further discloses that the passive element comprises a capacitor (¶ 0020).
Chaparala does not disclose the composition and structure of the capacitor component.
However, Topaloglu, in the same field of endeavor, shows that it was known in the art that capacitors (portions of Figs. 1 and 2 of Topaloglu above substrate 102) can be formed to have a configuration having a first surface (top surface in Fig. 1 of Topaloglu) and a second surface (bottom surface) opposite the first surface, the passive electronic component having (see annotations by the Examiner in the copies of Figs. 1 and 2 of Topaloglu, below, listing the following components) a second conductive feature and a third conductive feature on the first surface of the passive electronic component and a second nonconductive region on the first surface of the passive electronic component, the passive electronic component comprising a first electrode having a first conductive portion (middle 120 in the annotated copies of Topaloglu, below), a second electrode having second and third conductive portions electrically spaced from the first conductive portion along a direction non-parallel to the lateral contact surface (the vertical direction is non-parallel to the lateral contact surface and the second and third conductive portions are electrically spaced from the first conductive portion along the vertical direction), and a dielectric layer between the first and second electrodes, the first conductive portion of the first electrode electrically connected to the second conductive feature by a first longitudinal conductive interconnect, and the second and third conductive portions of the second electrode electrically connected to the third conductive feature by a second longitudinal conductive interconnect, the first conductive portion extending laterally outward from the first longitudinal conductive interconnect toward the second longitudinal interconnect; and
Topaloglu further discloses a fifth conductive feature (bottom-right 120 in Fig. 1 of Topaloglu) at the second surface, the first longitudinal conductive interconnect electrically connected to the fifth conductive feature and extending from the second conductive feature to the fifth conductive feature, the fifth conductive feature comprising an electrical contact (bottom surface) to bond to an external element (102 in Figs. 1 and 2 of Topaloglu).
There was a benefit to such a configuration for a capacitor in that Topaloglu teaches that it allows for an increased capacitance to size ratio (¶¶ 0005-0006 of Topaloglu), resulting in reduced device sizes, a recognized advantage in the art.
It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to use the capacitor structure of Topaloglu for the passive component in the device of Chaparala for this benefit.
Chaparala in view of Topaloglu do not disclose direct bonding as claimed.
However, Tong, in the same field of endeavor, shows that it was well known in the art to directly bond the conductive and nonconductive portions of two adjacent components without the use of an adhesive (see Fig. 2c of Tong; ¶ 0009).
There is a benefit to such a technique in that it reduces the amount of material within the device, a recognized advantage in the art.
It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to use direct bonding between the element and the passive electronic component as taught by Tong in the device of the combination of Chaparala and Topaloglu for this benefit.
In the resulting configuration of Chaparala, Topaloglu, and Tong, the second conductive feature of the passive component comprises a contact pad (as the second conductive feature is an electrical contact, it may be considered a contact pad) that would be directly bonded to the first conductive feature (choosing the first conductive feature to be the conductive feature of Chaparala providing power to the second conductive feature of Topaloglu) of the contact surface without an intervening adhesive as taught by Tong, wherein the second nonconductive region between the second and third conductive features would be directly bonded to the first nonconductive region of the contact surface without an intervening adhesive between the first and fourth conductive features; and the fifth conductive feature extends from the contact pad.
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Regarding claim 2, the combination of Chaparala, Topaloglu, and Tong disclose the structure of claim 1, as discussed above. Topaloglu further discloses that the passive electronic component is a capacitor (¶ 0010 of Topaloglu).
Regarding claim 3, the combination of Chaparala, Topaloglu, and Tong disclose the structure of claim 2, as discussed above. Topaloglu further discloses that the capacitor comprises three or more metallic layers spaced apart by a plurality of dielectric layers (see Figs. 1 and 2 of Topaloglu).
Regarding claim 13, the combination of Chaparala, Topaloglu, and Tong disclose the structure of claim 1, as discussed above. Chaparala further discloses that the passive component is provided within a passive component layer (layer directly beneath the element in Fig. 1 of Chaparala) at or near the first surface directly bonded to the element, the passive component layer covering a majority of the element (See Fig. 1 of Chaparala).
Regarding claim 16, the combination of Chaparala, Topaloglu, and Tong disclose the structure of claim 1, as discussed above. Topaloglu further discloses wherein the first longitudinal conductive interconnect defines an electrical pathway between the element and the electrical contact at or near the second surface of the passive electronic component (see annotated copy of Fig. 1, above).
Regarding claim 17, the combination of Chaparala, Topaloglu, and Tong disclose the structure of claim 1, as discussed above. Toploglu further discloses that the first and second electrodes are embedded with one or more dielectric layers (110 in Fig. 1 of Topaloglu) disposed between the first and second surfaces of the passive electronic component, the one or more dielectric layers including the dielectric layer (see Fig. 1 of Topaloglu).
Regarding claim 18, the combination of Chaparala, Topaloglu, and Tong disclose the structure of claim 17, as discussed above. Topaloglu further discloses that the first longitudinal conductive interconnect extends vertically within the passive electronic component relative to the lateral contact surface (see Fig. 1 of Topaloglu) and one or more lateral conductive portions (120’s) extend laterally outward from the first longitudinal conductive interconnect, the first longitudinal conductive interconnect defining a resistive electrical pathway and the one or more lateral conductive portions defining a capacitive electrical pathway in parallel with the resistive electrical pathway, the one or more lateral conductive portions including the first conductive portion (see Fig. 1 of Topaloglu).
Regarding claim 19, the combination of Chaparala, Topaloglu, and Tong disclose the structure of claim 18, as discussed above. Topaloglu further discloses that the second longitudinal conductive interconnect extends from the first surface of the passive electronic component to a sixth conductive feature at the second surface (see annotated copy of Fig. 1, above).
Regarding claim 20, the combination of Chaparala, Topaloglu, and Tong disclose the structure of claim 19, as discussed above. Topaloglu further discloses one or more second lateral conductive portions (second electrode in Fig. 1, above) extend laterally outward from the second longitudinal conductive interconnect, the second longitudinal conductive interconnect defining a second resistive electrical pathway and the one or more second lateral conductive portions defining a second capacitive electrical pathway in parallel with the second resistive electrical pathway, the one or more second lateral conductive portions including the second conductive portion (see Fig. 1, above).
Regarding claim 21, the combination of Chaparala, Topaloglu, and Tong disclose the structure of claim 20, as discussed above. Topaloglu further discloses the lateral conductive portion and the second lateral conductive portion are interleaved with one another and separated by an intervening dielectric material (see Fig. 1 of Topaloglu).
Regarding claim 30, Chaparala discloses a bonded structure (Fig. 1) comprising:
an integrated device die (10-2) having one or more active devices formed therein (¶ 0020); and
a passive electronic component (102) bonded to the integrated device die (see Fig. 1).
Chaparala further discloses that the passive integrated device die comprises a capacitor (¶ 0020).
Chaparala does not disclose the composition and structure of the capacitor component.
However, it was known in the art that capacitors (portions of Figs. 1 and 2 of Topaloglu above 102) can be formed to have a configuration having a first surface (top surface in Fig. 1 of Topaloglu) and a second surface (bottom surface) opposite the first surface, the passive electronic component having (see annotations by Examiner in the copies of Figs. 1 and 2, below) a first conductive feature comprising a corresponding contact pad (as the first conductive feature is an electrical contact, it may be considered a contact pad) and a second conductive feature on the first surface of the passive electronic component and a first nonconductive region between the first and second conductive features on the first surface of the passive electronic component, the passive electronic component comprising a first electrode having a first conductive portion, a second electrode having second and third conductive portions electrically spaced from the first conductive portion along a vertical direction (which is non-parallel to the horizontal direction which, as will be discussed below, is the direction of the lateral contact surface of the integrated device die), and a dielectric layer between the first and second electrodes, the first conductive portion of the first electrode electrically connected to the first conductive feature by a first longitudinal conductive interconnect, and the third conductive portion of the second electrode electrically connected to the third conductive feature by a second longitudinal conductive interconnect, the first conductive portion extending laterally outward from the first longitudinal conductive interconnect toward the second longitudinal interconnect (see Fig. 1, below); and
Topaloglu further discloses a third conductive feature (see Fig. 1, below) at the second surface, the first longitudinal conductive interconnect electrically connected to the third conductive feature and extending from the corresponding contact pad to the third conductive feature, the third conductive feature comprising an electrical contact (top surface) to bond to an external element.
There was a benefit to such a configuration for a capacitor in that Topaloglu teaches that it allows for an increased capacitance to size ratio (¶¶ 0005-0006), resulting in reduced device sizes, a recognized advantage in the art.
It would have been obvious to one having ordinary skill in the art before the Application’s effective filing date to use the capacitor structure of Topaloglu for the passive component in the device of Chaparala for this benefit.
Chaparala in view of Topaloglu do not disclose direct bonding as claimed.
However, it was well known in the art to directly bond the conductive and nonconductive portions of two adjacent components without the use of an adhesive (see Fig. 2c of Tong; ¶ 0009).
There was a benefit to such a technique in that it reduces the amount of material within the device, a recognized advantage in the art.
It would have been obvious to one having ordinary skill in the art before the Application’s effective filing date to use direct bonding as taught by Tong between the integrated device die and the passive electronic component in the device of Chaparala in view of Topaloglu for this benefit.
In the resulting configuration, the integrated device will have a lateral contact surface including a contact pad and a nonconductive region (corresponding to 21 and 25 in Fig. 2c of Tong, respesctively) with the corresponding contact pad of the passive component (corresponding to 23 of Tong) directly bonded to the contact pad of the lateral contact surface of the integrated die without an intervening adhesive and the first nonconductive region of the passive electronic component will be directly bonded to the nonconductive region of the lateral contact surface of the integrated device die without an intervening adhesive.
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Regarding claim 31, the combination of Chaparala, Topaloglu, and Tong disclose the structure of claim 30, as discussed above. Topaloglu further discloses that the passive electronic component comprises a capacitive sheet (see Fig. 1).
Regarding claim 32, the combination of Chaparala, Topaloglu, and Tong disclose the structure of claim 30, as discussed above. Chaparala further discloses that the passive electronic component is on a carrier (see Fig. 1 of Chaparala). As discussed in the rejection of claim 30, there is a benefit to using direct bonding as taught by Tong and it would similarly be obvious to one having ordinary skill in the art to attach the passive electronic component in the device of the combination of Chaparala, Topaloglu, and Tong to the carrier without an intervening adhesive for this benefit.
Regarding claim 39, the combination of Chaparala, Topaloglu, and Tong disclose the structure of claim 1, as discussed above. Chaparala et al. further disclose that the element comprises an integrated device die having one or more active devices formed therein (¶ 0020).
Regarding claim 40, the combination of Chaparala, Topaloglu, and Tong disclose the structure of claim 1, as discussed above. Chaparala et al. further disclose a carrier (20), the passive electronic component directly bonded to the carrier (see fig. 1). As discussed above, the conductive features (which would include the fifth conductive feature on the second surface of the passive electronic component) are directly bonded to corresponding conductive features of the carrier without an intervening adhesive.
Regarding claim 41, the combination of Chaparala, Topaloglu, and Tong disclose the structure of claim 40, as discussed above. Tong further discloses that there are additional areas of contact between nonconductive regions of the components (see Fig. 2c) which would correspond to a third nonconductive region on the second surface of the passive electronic component, the third nonconductive region being directly bonded to a corresponding nonconductive region of the carrier without an intervening adhesive.
Regarding claim 42, the combination of Chaparala, Topaloglu, and Tong disclose the structure of claim 40, as discussed above. Chaparala et al. further disclose that the carrier comprises a package substrate (¶ 0019).
Regarding claim 44, the combination of Chaparala, Topaloglu, and Tong disclose the structure of claim 1, as discussed above. As further discussed in the rejection of claim 1, above, in the device of the combination it would have been obvious to one having ordinary skill in the art to use the direct bonding technique of Tong for all connections. As such, in the device of the combination of Chaparala, Topaloglu, and Tong, the third conductive feature would be directly bonded to the fourth conductive feature of the of the element without an intervening adhesive (compare Fig. 1 of Chaparala and Fig. 2c of Tong).
Regarding claim 45, the combination of Chaparala, Topaloglu, and Tong disclose the structure of claim 30, as discussed above. As further discussed in the rejection of claim 30, above, in the device of the combination it would have been obvious to one having ordinary skill in the art to use the direct bonding technique of Tong for all connections. As such, in the device of the combination of Chaparala, Topaloglu, and Tong, the second conductive feature would be directly bonded to a second corresponding contact pad of the integrated device die without an intervening adhesive (compare Fig. 1 of Chaparala and Fig. 2c of Tong).
Regarding claim 47, the combination of Chaparala, Topaloglu, and Tong disclose the structure of claim 1, as discussed above. Topaloglu discloses that the passive electronic component is directly bonded to the external element (see Fig. 1).
Regarding claim 48, the combination of Chaparala, Topaloglu, and Tong disclose the structure of claim 1, as discussed above. Topaloglu discloses that the second and third conductive portions are electrically spaced from the first conductive portion along a vertical direction relative to the lateral contact surface of the element (see Fig. 1).
Claims 5-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chaparala et al., Topaloglu and Tong et al. as applied to claims 1 and 2 above, and further in view of Timler et al. (US 2013/0063863 A1). Regarding claim 5, the combination of Chaparala, Topaloglu, and Tong disclose the structure of claim 1, as discussed above. Chaparala, Topaloglu, and Tong do not explicitly disclose that the dielectric layer comprises a high K dielectric. However, forming dielectric layers between the electrodes of capacitors from high K dielectric materials is well-known in the art (¶ 0114 of Timler et al.). It would have been obvious to one having ordinary skill in the art at the time the application was filed to use a high K dielectric material for the dielectric of the capacitor of the combination of Chaparala, Topaloglu, and Tong as a high K dielectric (as opposed to a low K dielectric) will allow for the same insulative properties to be achieved with less material, resulting in a smaller device profile, a recognized advantage in the art. Regarding claim 6, the combination of Chaparala, Topaloglu, Tong, and Timler disclose the structure of claim 5, as discussed above. Timler further discloses that the high K dielectric can comprises lithium niobate (¶ 0114). Regarding claim 7, the combination of Chaparala, Topaloglu, Tong, and Timler disclose the structure of claim 5, as discussed above. Timler further discloses using noble metals for the electrodes of capacitors (“gold” in ¶ 0123). It would have been obvious to one having ordinary skill in the art at the time the application was filed to use a noble metal as taught by Timler for the first electrode as noble metals have a lower probability of corroding, which can negatively impact the functionality of the device.
Claim 43 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chaparala et al., Topaloglu, and Tong et al. as applied to claim 30, and further in view of Azais (US 2013/0286544 A1).
Regarding claim 43, the combination of Chaparala, Topaloglu, and Tong disclose the structure of claim 30, as discussed above. Topaloglu further discloses that the passive electronic component comprises a sheet covering a majority of the active surface of the element (see Fig. 1). Topaloglu discloses that the sheet is an electrode of a capacitor but Chaparala, Topaloglu, and Tong do not disclose the dimensions of the electrode in order to determine if the sheet has a lateral width at least three times its thickness. However, forming electrode sheets in capacitors to have a lateral width at least three times its thickness is common in the art (¶¶ 0148-0150 of Azais). It would have been obvious to one having ordinary skill in the art to use a high ratio of width to thickness in the capacitor sheet as taught by Azais in the device of the combination of Chaparala, Topaloglu, and Tong in order to increase the capacitance of the capacitor (which increases with the surface area of the capacitor) while maintaining a low overall thickness of the capacitor (which decreases with decreasing electrode thickness), a recognized advantage in the art. Therefore, as the technical knowledge necessary to form the sheet with a lateral width at least three times its thickness in known in the art (as evidenced by Azais) and there is motivation to do so, it would have been obvious to one having ordinary skill in the art at the time the application was filed to form the sheet of the combination of Chaparala, Topaloglu, and Tong to have a lateral width at least three times its thickness.
Claim 46 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chaparala et al., Topaloglu, and Tong et al. as applied to claim 1, and further in view of Cho et al. (US 2013/0032952 A1).
Regarding claim 46, Chaparala, Topaloglu, and Tong disclose the structure of claim 1, as discussed above. Chaparala, Topaloglu and Tong do not disclose a first conductive electrical interconnect configured to connect to electrical ground or second and third conductive electrical interconnects configured to connect to a power source. However, forming interconnects in bonded structures configured to connect to electrical ground and a power source is well-known in the art (“Traces 54 also provide power and ground connections to each of the semiconductor packages” in ¶ 0035 of Cho). There is a benefit to providing a first conductive electrical interconnect configured to connect to an electrical ground in that the device can have increased safety in the event of an electrical fault. There is further a benefit to providing second and third conductive electrical interconnects configured to connect to a power source in that it allows energy to be transmitted to different portions of the device. It would have been obvious to one having ordinary skill in the art at the time the application was filed to incorporate a first conductive electrical interconnect configured to connect to electrical ground and second and third conductive electrical interconnects configured to connect to a power source as taught by Cho in the structure of the combination of Chaparala, Topaloglu, and Tong for these benefits.
Response to Arguments
Applicant's arguments filed 2/26/2026 have been fully considered but they are not persuasive.
Applicant argues that the prior art references do not disclose the newly added limitations concerning contact pads. This argument is not persuasive as the conductive features are themselves contact pads.
Applicant further argues that there was no motivation to support the combination. This argument is not persuasive as the motivation was provided in the rejections.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A CULBERT whose telephone number is (571)272-4893. The examiner can normally be reached M-F 9-5.
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/CHRISTOPHER A CULBERT/Examiner, Art Unit 2815
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