DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Applicant's arguments filed on 05/13/2026 have been fully considered but they are not persuasive for at least the following reasons:
Regarding claim 1:
Applicant arguments: “Applicants respectfully submit that LIN does not disclose “a second portion with second cavity walls under the hard mask that extend to a second depth, and a third portion with third cavity walls under the hard mask and the one opening, the third cavity walls extending to a third depth, wherein the third depth is greater than the second depth and the second depth is greater than the first depth and wherein the first portion is wider than the second portion and the second portion is wider than the third portion”. The Examiner disagrees.
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In response: LIN discloses:
a second portion (annotated second arrow middle) with second cavity walls (Fig. [6], t annotated second arrow middle) under the hard mask (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]) that extend to a second depth (Fig. [6], annotated second arrow middle), and a third portion ( annotated third arrow bottom) with third cavity walls ( annotated third arrow bottom) under the hard mask (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]) and the one opening (Fig. [6], gate trench region 16, Para [ 0014]), the third cavity walls ( annotated third arrow bottom) extending to a third depth ( annotated third arrow bottom), wherein the third depth ( annotated third arrow bottom) is greater than the second depth ( annotated second arrow middle) and the second depth ( annotated second arrow middle) is greater than the first depth ( annotated first arrow top) and wherein the first portion ( annotated first arrow top) is wider than the second portion ( annotated second arrow middle) and the second portion ( annotated second arrow middle) is wider than the third portion ( annotated third arrow bottom).
Examiner like to note that, claim recites a second portion (annotated second arrow middle) and a third portion (annotated third arrow bottom) with third cavity walls (annotated third arrow bottom). Second portion or third portion can be any portion or any region of the cavity walls, as interpreted by the examiner. Therefore, the separated region as annotated, examiner interpreted as first portion, second portion and third portion.
Regarding claim 15:
Applicant arguments: Applicants respectfully submit that LIN does not disclose “wherein walls of the cavity extend from a surface of the substrate to a first lateral surface at a first depth and from the first lateral surface to a second depth under the one opening, the second depth being greater than the first depth, wherein the entire first depth of the first lateral surface extends under the layer”. The Examiner disagrees.
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In response: LIN discloses: wherein walls of the cavity (Fig. [6], trench region 24, Para [ 0016, 0020]) extend from a surface of the substrate to a first lateral surface at a first depth ( annotated first arrow top) and from the first lateral surface to a second depth (annotated second arrow middle) under the one opening (Fig. [6], gate trench 16, Para [ 0012- 0020]), the second depth (annotated second arrow middle) being greater than the first depth ( annotated first arrow top), wherein the entire first depth of the first lateral surface (Fig. [6], trench region 24, Para [ 0016, 0020]) extends under the layer (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]).
Examiner like to note that, wherein walls of the cavity (Fig. [6], trench region 24, Para [ 0016, 0020]) extend from a surface of the substrate (annotated a surface of the substrate) to a first lateral surface at a first depth (annotated first arrow top). It appears based on the argument, a surface of the substrate, meant by top surface or topmost surface, which is not claimed.
Regarding claim 19:
Applicant arguments: Applicants respectfully submit that LIN does not disclose “the cavity extends to a surface of the substrate" and "the cavity extends to the hard mask”.
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In response: LIN discloses: a cavity (Fig. [6], trench region 24, Para [ 0016, 0020]) in a substrate (Fig. [6], substrate 10, Para [ 0012]) and a hard mask (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]) over the substrate (Fig. [6], substrate 10, Para [ 0012]), wherein:
the cavity (Fig. [6], trench region 24, Para [ 0016, 0020]) extends to a surface of the substrate (Fig. [6], annotated surface of the substrate 10, Para [ 0012]);
the cavity (Fig. [6], trench region 24, Para [ 0016, 0020]) extends to the hard mask (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]).
Regarding claim 26:
Applicant arguments: Applicants respectfully submit that LIN does not disclose “wherein a width of the cavity at the third cavity walls is greater than a width of the opening, a width of the cavity at the second cavity walls is greater than the width of the cavity at the third cavity walls, and a width of the cavity at the first cavity walls is greater than the width of the cavity at the second cavity walls”. The Examiner disagrees.
Terasawa discloses wherein a width of the cavity at the third cavity (Fig 3H, 11c,col 8, lines 10-25) walls is greater than a width of the opening (Fig 3H, opening 12a,col7, lines 30-45), a width of the cavity at the second cavity walls ( Fig 3H, 11b, col 8, lines 10-25) is greater than the width of the cavity at the third cavity walls (Fig 3H, 11c, col 8, lines 10-25), and a width of the cavity at the first cavity walls ( Fig 3H, 11a, col 8, lines 10-25) is greater than the width of the cavity at the second cavity walls ( Fig 3H, 11b, col 8, lines 10-25).
Thus, the well-made rejection included in the 12/16/2025 Non-Final Office Action is proper and hereby made FINAL.
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Takubu et al (US 2007/0073448 A1; hereafter Takubu) in view of Gonzalez (US 2003/0042512 A1; hereafter Gonzalez).
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Regarding claim 15, Takubu disclose a semiconductor device (Fig 7) comprising: a substrate (Fig [7], substrate 1, Para [ 0050, 0057]);
a layer (Fig [7], photoresist [40], Para [ 0057]) over the substrate (Fig [7], substrate 1);
a cavity (Fig [7], hole 3, Para [ 0058]) in the substrate (Fig 7, substrate 10) under no more than one opening in the layer (Fig [7], photoresist [40], Para [ 0057]), wherein the cavity is at least twice as wide as it is deep (Fig [7], hole 3, Para [ 0058]), and wherein walls of the cavity (Fig [7], hole 3, Para [ 0058]) extend from a surface of the substrate (Fig 7, substrate 10) to a first lateral surface at a first depth (Fig 7, annotated first arrow left) and from the first lateral surface to a second depth ( Fig 7, annotated first arrow middle) under the one opening, the second depth (Fig 7, annotated arrow middle) being greater than the first depth (Fig 7, annotated arrow left), wherein the entire first depth of the first lateral surface extends under the layer (Fig [7], photoresist [40], Para [ 0057]).
But Takubu does not disclose explicitly a substrate of single crystal silicon and wherein a depth of the cavity is non-uniform across a width of the cavity.
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In a similar field of endeavor, Gonzalez discloses a substrate of single crystal silicon (Fig 4, Para [0044]) and wherein a depth of the cavity is non-uniform across a width of the cavity (Fig 4, monolithic crystallographic surfaces 42, 44, 46, 48, 50, and 52, Para [ 0044-0049]).
Therefore it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to modify Takubu in light of Gonzalez teaching “a substrate of single crystal silicon (Fig 4, Para [0044]) and wherein a depth of the cavity is non-uniform across a width of the cavity (Fig 4, monolithic crystallographic surfaces 42, 44, 46, 48, 50, and 52, Para [ 0044-0049])” for further advantages such as to manufacture high reliable semiconductor device by using well know substrate material and desire depth to provide various semiconductor device application.
Additionally, the Applicant has presented no discussion in the specification which convinces the Examiner that the particular shape of the support means is anything more than one of numerous shapes a person of ordinary skill in the art would find obvious for the purpose of providing support. In re Dailey, 149 USPQ 47 (CCPA 1976). It appears that these changes produce no functional differences and therefore would have been obvious.
Regarding claim 19, Takubu discloses a semiconductor device (Fig 7) comprising a cavity (Fig [7], hole 3, Para [ 0058]) in a substrate (Fig [7], substrate 1, Para [ 0050, 0057]) and
a hard mask (Fig [7], photoresist [40], Para [ 0057]) over the substrate (Fig 7, substrate 100), wherein:
the cavity extends (Fig [7], hole 3, Para [ 0058]) to a surface of the substrate (Fig [7], substrate 1, Para [ 0050, 0057]);
the cavity extends (Fig [7], hole 3, Para [ 0058]) to the hard mask (Fig [7], photoresist [40], Para [ 0057]);
the cavity (Fig [7], hole 3, Para [ 0058]) underlies no more than one opening (Fig [7]) in the hard mask (Fig [7], photoresist [40], Para [ 0057]);
the cavity (Fig [7], hole 3, Para [ 0058]) is wider than it is deep (Fig 7) and the depth being greatest directly below the opening (Fig 7); and
the surface of the substrate (Fig 7, substrate 100) in the cavity extends from the hard mask (Fig [7], photoresist [40], Para [ 0057]) at a first lateral distance from the one opening to a first lateral portion at a first depth (Fig 7, annotated arrow left) and from the first lateral portion (Fig 7, annotated arrow left) at a second lateral distance from the one opening to a second depth (Fig 7, annotated arrow middle), the second depth being deeper (Fig 7, annotated arrow middle) than the first depth (Fig 6b, annotated arrow left) and the first lateral distance being greater than the second lateral distance (Fig 7), wherein the hard mask (Fig [7], photoresist [40], Para [ 0057]) extends entirely over the first lateral portion (Fig 7).
But Takubu does not disclose explicitly wherein a depth of the cavity is non-uniform across a width of the cavity.
In a similar field of endeavor, Gonzalez discloses wherein a depth of the cavity is non-uniform across a width of the cavity (Fig 4, monolithic crystallographic surfaces 42, 44, 46, 48, 50, and 52, Para [ 0044-0049]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to modify Takubu in light of Gonzalez teaching “wherein a depth of the cavity is non-uniform across a width of the cavity (Fig 4, monolithic crystallographic surfaces 42, 44, 46, 48, 50, and 52, Para [ 0044-0049])” for further advantages such as to manufacture high reliable semiconductor device and desire depth to provide various semiconductor device application.
Additionally, the Applicant has presented no discussion in the specification which convinces the Examiner that the particular shape of the support means is anything more than one of numerous shapes a person of ordinary skill in the art would find obvious for the purpose of providing support. In re Dailey, 149 USPQ 47 (CCPA 1976). It appears that these changes produce no functional differences and therefore would have been obvious.
ALTERNATE REJECTION:
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5, 19, 22, 24-25, 27 and 35 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin (US 2007/0161172 A1; hereafter Lin).
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Regarding claim 1. Lin discloses a semiconductor device (Fig. [6]) comprising a cavity (Fig. [6], trench region 24, Para [ 0016, 0020]) in a substrate ( Fig. [6], substrate 10,Para [ 0012]) and a hard mask (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]) over the substrate ( Fig. [6], substrate 10, Para [ 0012]), the cavity (Fig. [6], trench region 24, Para [ 0016, 0020]) exposing a surface of the substrate ( Fig. [6], substrate 10,Para [ 0012]) and underlying no more than one opening ( gate trench 16, Para [ 0014]) in the hard mask (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]), wherein the cavity (Fig. [6], trench region 24, Para [ 0016, 0020]) is wider than it is deep and is non-uniform across a width of the cavity (Fig. [6], trench region 24, Para [ 0016, 0020]) and comprises a first portion ( annotated first arrow top) with first cavity walls (Fig. [6], trench region 24, Para [ 0016, 0020]) under the hard mask (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]) that extend to a first depth ( annotated first arrow top), a second portion (annotated second arrow middle) with second cavity walls (Fig. [6], t annotated second arrow middle) under the hard mask (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]) that extend to a second depth (Fig. [6], annotated second arrow middle), and a third portion ( annotated third arrow bottom) with third cavity walls ( annotated third arrow bottom) under the hard mask (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]) and the one opening (Fig. [6], gate trench region 16, Para [ 0014]), the third cavity walls ( annotated third arrow bottom) extending to a third depth ( annotated third arrow bottom), wherein the third depth ( annotated third arrow bottom) is greater than the second depth ( annotated second arrow middle) and the second depth ( annotated second arrow middle) is greater than the first depth ( annotated first arrow top) and wherein the first portion ( annotated first arrow top) is wider than the second portion ( annotated second arrow middle) and the second portion ( annotated second arrow middle) is wider than the third portion ( annotated third arrow bottom).
Regarding claim 5. Lin discloses the semiconductor device of claim 1, Lin further discloses wherein the hard mask (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]) comprises a layer of silicon nitride overlying a layer of silicon dioxide (Fig. [6], element [12,14], construed as hard mask, Para [ 0012-0013]). It is evidence by Knaipp et al US 2008/0290445 discloses oxide layer is silicon oxide, Para [ 0034] and silicon nitride layer is referred to as nitride layer, Para [ 0010]).
Regarding claim 19. Lin discloses a semiconductor device (Fig. [6]) comprising a cavity (Fig. [6], trench region 24, Para [ 0016, 0020]) in a substrate (Fig. [6], substrate 10, Para [ 0012]) and a hard mask (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]) over the substrate (Fig. [6], substrate 10, Para [ 0012]), wherein:
the cavity (Fig. [6], trench region 24, Para [ 0016, 0020]) extends to a surface of the substrate (Fig. [6], substrate 10, Para [ 0012]);
the cavity (Fig. [6], trench region 24, Para [ 0016, 0020]) extends to the hard mask (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]);
the cavity underlies no more than one opening (Fig. [6], gate trench 16, Para [ 0012- 0020]) in the hard mask (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]);
the cavity (Fig. [6], trench region 24, Para [ 0016, 0020]) is wider than it is deep and a depth of the cavity is non-uniform across a width of the cavity (annotated Fig. [6]), the depth being greatest directly below the opening (Fig. [6], gate trench 16, Para [ 0012- 0020]); and
the surface of the substrate (Fig. [6], substrate 10, Para [ 0012]) in the cavity (Fig. [6], trench region 24, Para [ 0016, 0020]) extends from the hard mask (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]) at a first lateral distance from the one opening to a first lateral portion at a first depth ( annotated first arrow top) and from the first lateral portion ( annotated first arrow top) at a second lateral distance from the one opening to a second depth (annotated second arrow middle), the second depth (annotated second arrow middle) being deeper than the first depth ( annotated first arrow top) and the first lateral distance ( annotated first arrow top) being greater than the second lateral distance (annotated second arrow middle), wherein the hard mask (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]) extends entirely over the first lateral portion ( annotated first arrow top).
Regarding claim 22. Lin discloses the semiconductor device of claim 19, Lin further discloses wherein a width of the cavity (Fig. [6], trench region 24, Para [ 0016, 0020]) is greater than a width of the opening (Fig. [6], gate trench 16, Para [ 0012- 0020]).
Regarding claim 24, Lin discloses the semiconductor device of claim 1, Lin further discloses wherein a width of the cavity (Fig. [6], trench region 24, Para [ 0016, 0020]) is greater than a width of the opening (Fig. [6], gate trench 16, Para [ 0012- 0020]).
Regarding claim 25, Lin discloses the semiconductor device of claim 1, Lin further discloses wherein a width of the cavity at the second cavity walls (annotated second arrow middle) is greater than a width of the opening (Fig. [6], gate trench 16, Para [ 0012- 0020]) and a width of the cavity at the first cavity walls (annotated first arrow top) is greater than the width of the cavity at the second cavity walls (Fig 6).
Regarding claim 27, Lin discloses the semiconductor device of claim 1, Lin further discloses wherein the first cavity walls (Fig. [6], annotated first arrow top) extend under the hard mask layer (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]) further from the opening (Fig. [6], gate trench 16, Para [ 0012- 0020]) than the second cavity walls ( annotated second arrow middle), and the second cavity walls (Fig. [6], annotated second arrow middle) extend further under the hard mask layer (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]) from the opening (Fig. [6], gate trench 16, Para [ 0012- 0020]) than the third cavity walls (Fig. [6], annotated third arrow bottom).
Regarding claim 35. Lin discloses the semiconductor device of claim 19, Lin further discloses wherein the hard mask comprises a layer of silicon nitride overlying a layer of silicon dioxide (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]). It is evidence by Knaipp et al US 2008/0290445 discloses oxide layer is silicon oxide, Para [ 0034] and silicon nitride layer is referred to as nitride layer, Para [ 0010]).
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3, 15 and 30-34 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2007/0161172 A1; hereafter Lin) in view of Shichi et al (US 2010/0087044 A1; hereafter Shichi)
Regarding claim 2. Lin discloses the semiconductor device of claim 1, but Lin does not disclose explicitly wherein the substrate is single crystal silicon.
In a similar field of endeavor, Shichi discloses wherein the substrate is single crystal silicon germanium (Para [0036]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to modify Lin in light of Shichi teaching “wherein the substrate is single crystal silicon germanium (Para [0036])” for further advantages such as using well-known materials to manufacture high reliability semiconductor device.
Regarding claim 3. Lin discloses the semiconductor device of claim 1, but Lin does not disclose explicitly wherein the substrate is single crystal silicon germanium.
In a similar field of endeavor, Shichi discloses wherein the substrate is single crystal silicon germanium (Para [0036]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to modify Holzwarth in light of Shichi teaching “wherein the substrate is single crystal silicon germanium (Para [0036])” for further advantages such as using well-known materials to manufacture high reliability semiconductor device.
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Regarding claim 15. Lin discloses a semiconductor device comprising: a substrate (Fig 6b, substrate 10, Para [ 0012]);
a layer (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]) over the substrate (Fig 6b, substrate 10, Para [ 0012]);
a cavity (Fig. [6], trench region 24, Para [ 0016, 0020]) in the substrate (Fig 6b, substrate 10, Para [ 0012]) under no more than one opening (Fig. [6], gate trench 16, Para [ 0012- 0020]) in the layer (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]), wherein the cavity is at least twice as wide as it is deep (Fig. [6], trench region 24, Para [ 0016, 0020]), wherein a depth of the cavity is non-uniform across a width of the cavity (Fig. [6], trench region 24, Para [ 0016, 0020]), and wherein walls of the cavity (Fig. [6], trench region 24, Para [ 0016, 0020]) extend from a surface of the substrate to a first lateral surface at a first depth ( annotated first arrow top) and from the first lateral surface to a second depth (annotated second arrow middle) under the one opening (Fig. [6], gate trench 16, Para [ 0012- 0020]), the second depth (annotated second arrow middle) being greater than the first depth ( annotated first arrow top), wherein the entire first depth of the first lateral surface (Fig. [6], trench region 24, Para [ 0016, 0020]) extends under the layer (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]).
But Lin does not disclose explicitly wherein the substrate is single crystal silicon.
In a similar field of endeavor, Shichi discloses wherein the substrate is single crystal silicon germanium (Para [0036]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to modify Lin in light of Shichi teaching “wherein the substrate is single crystal silicon germanium (Para [0036])” for further advantages such as using well-known materials to manufacture high reliability semiconductor device.
Regarding claim 31. Lin in light of Shichi discloses the semiconductor device of claim 15, but Lin does not disclose explicitly wherein the substrate is single crystal silicon germanium.
In a similar field of endeavor, Shichi discloses wherein the substrate is single crystal silicon germanium (Para [0036]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to modify Lin in light of Shichi teaching “wherein the substrate is single crystal silicon germanium (Para [0036])” for further advantages such as using well-known materials to manufacture high reliability semiconductor device.
Regarding claim 32. Lin in light of Shichi discloses the semiconductor device of claim 15, Lin further discloses wherein the hard mask comprises a layer of silicon nitride overlying a layer of silicon dioxide (Fig. [6], element [12,14], construed as hard mask, Para [ 0012-0013]). It is evidence by Knaipp et al US 2008/0290445 discloses oxide layer is silicon oxide, Para [ 0034] and silicon nitride layer is referred to as nitride layer, Para [ 0010]).
Regarding claim 33. Lin discloses the semiconductor device of claim 19, but Lin does not disclose explicitly wherein the substrate is single crystal silicon.
In a similar field of endeavor, Shichi discloses wherein the substrate is single crystal silicon germanium (Para [0036]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to modify Lin in light of Shichi teaching “wherein the substrate is single crystal silicon germanium (Para [0036])” for further advantages such as using well-known materials to manufacture high reliability semiconductor device.
Regarding claim 34. Lin discloses the semiconductor device of claim 19, but Lin does not disclose explicitly wherein the substrate is single crystal silicon germanium.
In a similar field of endeavor, Shichi discloses wherein the substrate is single crystal silicon germanium (Para [0036]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to modify Holzwarth in light of Shichi teaching “wherein the substrate is single crystal silicon germanium (Para [0036])” for further advantages such as using well-known materials to manufacture high reliability semiconductor device.
Claims 26 is rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2007/0161172 A1; hereafter Lin) in view of Terasawa et al (US 6075,269; hereafter Terasawa).
Regarding claim 26, Lin discloses the semiconductor device of claim 1, but Lin does not disclose explicitly wherein a width of the cavity at the third cavity walls is greater than a width of the opening, a width of the cavity at the second cavity walls is greater than the width of the cavity at the third cavity walls, and a width of the cavity at the first cavity walls is greater than the width of the cavity at the second cavity walls.
In a similar field of endeavor, Terasawa discloses wherein a width of the cavity at the third cavity (Fig 3H, 11c,col 8, lines 10-25) walls is greater than a width of the opening (Fig 3H, opening 12a,col7, lines 30-45), a width of the cavity at the second cavity walls ( Fig 3H, 11b, col 8, lines 10-25) is greater than the width of the cavity at the third cavity walls (Fig 3H, 11c, col 8, lines 10-25), and a width of the cavity at the first cavity walls ( Fig 3H, 11a, col 8, lines 10-25) is greater than the width of the cavity at the second cavity walls ( Fig 3H, 11b, col 8, lines 10-25).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to modify Lin in light of Terasawa teaching “wherein a width of the cavity at the third cavity (Fig 3H, 11c,col 8, lines 10-25) walls is greater than a width of the opening (Fig 3H, opening 12a,col7, lines 30-45), a width of the cavity at the second cavity walls ( Fig 3H, 11b, col 8, lines 10-25) is greater than the width of the cavity at the third cavity walls (Fig 3H, 11c, col 8, lines 10-25), and a width of the cavity at the first cavity walls ( Fig 3H, 11a, col 8, lines 10-25) is greater than the width of the cavity at the second cavity walls ( Fig 3H, 11b, col 8, lines 10-25)” for further advantages such as provide high aspect ratio to improve device performance.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
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