DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
In view of the Appeal Brief filed on 07/28/2025, PROSECUTION IS HEREBY REOPENED. A new ground(s) of rejection is set forth below. Claims 1-3, 5, 15,19, 22, 24-27 and 29-35 are pending.
To avoid abandonment of the application, appellant must exercise one of the following two options:
(1) file a reply under 37 CFR 1.111 (if this Office action is non-final) or a reply under 37 CFR 1.113 (if this Office action is final); or,
(2) initiate a new appeal by filing a notice of appeal under 37 CFR 41.31 followed by an appeal brief under 37 CFR 41.37. The previously paid notice of appeal fee and appeal brief fee can be applied to the new appeal. If, however, the appeal fees set forth in 37 CFR 41.20 have been increased since they were previously paid, then appellant must pay the difference between the increased fees and the amount previously paid.
A Supervisory Patent Examiner (SPE) has approved of reopening prosecution by signing below:
/JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d) that forms the basis for the rejection set forth in this Office action:
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed.
Claim 30 rejected under 35 U.S.C. 112(d), as failing to comply with the written description requirement. Limitations of claim 30 “wherein the substrate is single crystal silicon” are in independent claim 15 from which dependent claim 30 depends. The limitation of Claim 30 “wherein the substrate is single crystal silicon” does not specify a further limitation of the subject matter.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5, 19, 22, 24-25, 27 and 35 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin (US 2007/0161172 A1; hereafter Lin).
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Regarding claim 1. Lin discloses a semiconductor device (Fig. [6]) comprising a cavity (Fig. [6], trench region 24, Para [ 0016, 0020]) in a substrate ( Fig. [6], substrate 10,Para [ 0012]) and a hard mask (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]) over the substrate ( Fig. [6], substrate 10, Para [ 0012]), the cavity (Fig. [6], trench region 24, Para [ 0016, 0020]) exposing a surface of the substrate ( Fig. [6], substrate 10,Para [ 0012]) and underlying no more than one opening ( gate trench 16, Para [ 0014]) in the hard mask (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]), wherein the cavity (Fig. [6], trench region 24, Para [ 0016, 0020]) is wider than it is deep and is non-uniform across a width of the cavity (Fig. [6], trench region 24, Para [ 0016, 0020]) and comprises a first portion ( annotated first arrow top) with first cavity walls (Fig. [6], trench region 24, Para [ 0016, 0020]) under the hard mask (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]) that extend to a first depth ( annotated first arrow top), a second portion (annotated second arrow middle) with second cavity walls (Fig. [6], t annotated second arrow middle) under the hard mask (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]) that extend to a second depth (Fig. [6], annotated second arrow middle), and a third portion ( annotated third arrow bottom) with third cavity walls ( annotated third arrow bottom) under the hard mask (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]) and the one opening (Fig. [6], gate trench region 16, Para [ 0014]), the third cavity walls ( annotated third arrow bottom) extending to a third depth ( annotated third arrow bottom), wherein the third depth ( annotated third arrow bottom) is greater than the second depth ( annotated second arrow middle) and the second depth ( annotated second arrow middle) is greater than the first depth ( annotated first arrow top) and wherein the first portion ( annotated first arrow top) is wider than the second portion ( annotated second arrow middle) and the second portion ( annotated second arrow middle) is wider than the third portion ( annotated third arrow bottom).
Regarding claim 5. Lin discloses the semiconductor device of claim 1, Lin further discloses wherein the hard mask (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]) comprises a layer of silicon nitride overlying a layer of silicon dioxide (Fig. [6], element [12,14], construed as hard mask, Para [ 0012-0013]). It is evidence by Knaipp et al US 2008/0290445 discloses oxide layer is silicon oxide, Para [ 0034] and silicon nitride layer is referred to as nitride layer, Para [ 0010]).
Regarding claim 19. Lin discloses a semiconductor device (Fig. [6]) comprising a cavity (Fig. [6], trench region 24, Para [ 0016, 0020]) in a substrate (Fig. [6], substrate 10, Para [ 0012]) and a hard mask (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]) over the substrate (Fig. [6], substrate 10, Para [ 0012]), wherein:
the cavity (Fig. [6], trench region 24, Para [ 0016, 0020]) extends to a surface of the substrate (Fig. [6], substrate 10, Para [ 0012]) underlying the cavity (Fig. [6], trench region 24, Para [ 0016, 0020]); the cavity extends to the hard mask;
the cavity underlies no more than one opening (Fig. [6], gate trench 16, Para [ 0012- 0020]) in the hard mask (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]);
the cavity (Fig. [6], trench region 24, Para [ 0016, 0020]) is wider than it is deep and a depth of the cavity is non-uniform across a width of the cavity (annotated Fig. [6]), the depth being greatest directly below the opening (Fig. [6], gate trench 16, Para [ 0012- 0020]); and
the surface of the substrate (Fig. [6], substrate 10, Para [ 0012]) in the cavity (Fig. [6], trench region 24, Para [ 0016, 0020]) extends from the hard mask (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]) at a first lateral distance from the one opening to a first lateral portion at a first depth ( annotated first arrow top) and from the first lateral portion ( annotated first arrow top) at a second lateral distance from the one opening to a second depth (annotated second arrow middle), the second depth (annotated second arrow middle) being deeper than the first depth ( annotated first arrow top) and the first lateral distance ( annotated first arrow top) being greater than the second lateral distance (annotated second arrow middle), wherein the hard mask (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]) extends entirely over the first lateral portion ( annotated first arrow top).
Regarding claim 22. Lin discloses the semiconductor device of claim 19, Lin further discloses wherein a width of the cavity (Fig. [6], trench region 24, Para [ 0016, 0020]) is greater than a width of the opening (Fig. [6], gate trench 16, Para [ 0012- 0020]).
Regarding claim 24, Lin discloses the semiconductor device of claim 1, Lin further discloses wherein a width of the cavity (Fig. [6], trench region 24, Para [ 0016, 0020]) is greater than a width of the opening (Fig. [6], gate trench 16, Para [ 0012- 0020]).
Regarding claim 25, Lin discloses the semiconductor device of claim 1, Lin further discloses wherein a width of the cavity at the second cavity walls (annotated second arrow middle) is greater than a width of the opening (Fig. [6], gate trench 16, Para [ 0012- 0020]) and a width of the cavity at the first cavity walls (annotated first arrow top) is greater than the width of the cavity at the second cavity walls (Fig 6).
Regarding claim 27, Lin discloses the semiconductor device of claim 1, Lin further discloses wherein the first cavity walls (Fig. [6], annotated first arrow top) extend under the hard mask layer (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]) further from the opening (Fig. [6], gate trench 16, Para [ 0012- 0020]) than the second cavity walls ( annotated second arrow middle), and the second cavity walls (Fig. [6], annotated second arrow middle) extend further under the hard mask layer (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]) from the opening (Fig. [6], gate trench 16, Para [ 0012- 0020]) than the third cavity walls (Fig. [6], annotated third arrow bottom).
Regarding claim 35. Lin discloses the semiconductor device of claim 19, Lin further discloses wherein the hard mask comprises a layer of silicon nitride overlying a layer of silicon dioxide (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]). It is evidence by Knaipp et al US 2008/0290445 discloses oxide layer is silicon oxide, Para [ 0034] and silicon nitride layer is referred to as nitride layer, Para [ 0010]).
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3, 15 and 30-34 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2007/0161172 A1; hereafter Lin) in view of Shichi et al (US 2010/0087044 A1; hereafter Shichi)
Regarding claim 2. Lin discloses the semiconductor device of claim 1, but Lin does not disclose explicitly wherein the substrate is single crystal silicon.
In a similar field of endeavor, Shichi discloses wherein the substrate is single crystal silicon germanium (Para [0036]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to modify Lin in light of Shichi teaching “wherein the substrate is single crystal silicon germanium (Para [0036])” for further advantages such as using well-known materials to manufacture high reliability semiconductor device.
Regarding claim 3. Lin discloses the semiconductor device of claim 1, but Lin does not disclose explicitly wherein the substrate is single crystal silicon germanium.
In a similar field of endeavor, Shichi discloses wherein the substrate is single crystal silicon germanium (Para [0036]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to modify Holzwarth in light of Shichi teaching “wherein the substrate is single crystal silicon germanium (Para [0036])” for further advantages such as using well-known materials to manufacture high reliability semiconductor device.
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Regarding claim 15. Lin discloses a semiconductor device comprising: a substrate (Fig 6b, substrate 10, Para [ 0012]);
a layer (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]) over the substrate (Fig 6b, substrate 10, Para [ 0012]);
a cavity (Fig. [6], trench region 24, Para [ 0016, 0020]) in the substrate (Fig 6b, substrate 10, Para [ 0012]) under no more than one opening (Fig. [6], gate trench 16, Para [ 0012- 0020]) in the layer (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]), wherein the cavity is at least twice as wide as it is deep (Fig. [6], trench region 24, Para [ 0016, 0020]), wherein a depth of the cavity is non-uniform across a width of the cavity (Fig. [6], trench region 24, Para [ 0016, 0020]), and wherein walls of the cavity (Fig. [6], trench region 24, Para [ 0016, 0020]) extend from a surface of the substrate to a first lateral surface at a first depth ( annotated first arrow top) and from the first lateral surface to a second depth (annotated second arrow middle) under the one opening (Fig. [6], gate trench 16, Para [ 0012- 0020]), the second depth (annotated second arrow middle) being greater than the first depth ( annotated first arrow top), wherein the entire first lateral surface extends under the layer (Fig. [6], element [12,14], construed as hard mask, Para [ 0012]).
But Lin does not disclose explicitly wherein the substrate is single crystal silicon.
In a similar field of endeavor, Shichi discloses wherein the substrate is single crystal silicon germanium (Para [0036]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to modify Lin in light of Shichi teaching “wherein the substrate is single crystal silicon germanium (Para [0036])” for further advantages such as using well-known materials to manufacture high reliability semiconductor device.
Regarding claim 30. Lin in light of Shichi discloses the semiconductor device of claim 15, Shichi further discloses wherein the substrate is single crystal silicon (Para [0036]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to modify Lin in light of Shichi teaching “wherein the substrate is single crystal silicon germanium (Para [0036])” for further advantages such as using well-known materials to manufacture high reliability semiconductor device.
Regarding claim 31. Lin in light of Shichi discloses the semiconductor device of claim 15, but Lin does not disclose explicitly wherein the substrate is single crystal silicon germanium.
In a similar field of endeavor, Shichi discloses wherein the substrate is single crystal silicon germanium (Para [0036]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to modify Lin in light of Shichi teaching “wherein the substrate is single crystal silicon germanium (Para [0036])” for further advantages such as using well-known materials to manufacture high reliability semiconductor device.
Regarding claim 32. Lin in light of Shichi discloses the semiconductor device of claim 15, Lin further discloses wherein the hard mask comprises a layer of silicon nitride overlying a layer of silicon dioxide (Fig. [6], element [12,14], construed as hard mask, Para [ 0012-0013]). It is evidence by Knaipp et al US 2008/0290445 discloses oxide layer is silicon oxide, Para [ 0034] and silicon nitride layer is referred to as nitride layer, Para [ 0010]).
Regarding claim 33. Lin discloses the semiconductor device of claim 19, but Lin does not disclose explicitly wherein the substrate is single crystal silicon.
In a similar field of endeavor, Shichi discloses wherein the substrate is single crystal silicon germanium (Para [0036]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to modify Lin in light of Shichi teaching “wherein the substrate is single crystal silicon germanium (Para [0036])” for further advantages such as using well-known materials to manufacture high reliability semiconductor device.
Regarding claim 34. Lin discloses the semiconductor device of claim 19, but Lin does not disclose explicitly wherein the substrate is single crystal silicon germanium.
In a similar field of endeavor, Shichi discloses wherein the substrate is single crystal silicon germanium (Para [0036]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to modify Holzwarth in light of Shichi teaching “wherein the substrate is single crystal silicon germanium (Para [0036])” for further advantages such as using well-known materials to manufacture high reliability semiconductor device.
Claims 26 is rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2007/0161172 A1; hereafter Lin) in view of Terasawa et al (US 6075,269; hereafter Terasawa).
Regarding claim 26, Lin discloses the semiconductor device of claim 1, but Lin does not disclose explicitly wherein a width of the cavity at the third cavity walls is greater than a width of the opening, a width of the cavity at the second cavity walls is greater than the width of the cavity at the third cavity walls, and a width of the cavity at the first cavity walls is greater than the width of the cavity at the second cavity walls.
In a similar field of endeavor, discloses wherein a width of the cavity at the third cavity (Fig 3H, 11c,col 8, lines 10-25) walls is greater than a width of the opening (Fig 3H, opening 12a,col7, lines 30-45), a width of the cavity at the second cavity walls ( Fig 3H, 11b, col 8, lines 10-25) is greater than the width of the cavity at the third cavity walls (Fig 3H, 11c, col 8, lines 10-25), and a width of the cavity at the first cavity walls ( Fig 3H, 11a, col 8, lines 10-25) is greater than the width of the cavity at the second cavity walls ( Fig 3H, 11b, col 8, lines 10-25).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to modify Lin in light of Terasawa teaching “wherein a width of the cavity at the third cavity (Fig 3H, 11c,col 8, lines 10-25) walls is greater than a width of the opening (Fig 3H, opening 12a,col7, lines 30-45), a width of the cavity at the second cavity walls ( Fig 3H, 11b, col 8, lines 10-25) is greater than the width of the cavity at the third cavity walls (Fig 3H, 11c, col 8, lines 10-25), and a width of the cavity at the first cavity walls ( Fig 3H, 11a, col 8, lines 10-25) is greater than the width of the cavity at the second cavity walls ( Fig 3H, 11b, col 8, lines 10-25)” for further advantages such as provide high aspect ratio to improve device performance.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
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