DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 9/4/2025 has been entered.
Response to Arguments
Applicant’s arguments filed 10/10/2025 with respect to the pending claims have been fully considered but are moot in view of the new grounds of rejection.
The rejection has updated to include the newly added limitations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Licausi et al. US 9,812,351 (hereinafter “Licausi”) in view of Kornachuk et al. (US PGPub 2017/0365548; hereinafter “Kornachuk”), Chang et al. (US 2017/0194252; hereinafter “Chang”), and Himeno et al. (CN103168359; hereinafter “Himeno”; found in IDS filed 3/20/2023), and Raaijmakers et al. (US PGPub 2004/0130029; hereinafter “Raaijmakers”).
Re claim 1: Licausi teaches (e.g. figs. 1, 2, 34 and labeled fig. 34 below) an integrated circuit structure, comprising: an inter-layer dielectric (ILD) layer (104) above a substrate (108); a first plurality of conductive interconnect lines (A, B, C, D; e.g. column 7, line 26) in and spaced apart by the ILD layer (104), the first plurality of conductive interconnect lines (A, B, C, D) comprising: a first interconnect line (1CL) having a width (1CL has width 112; e.g. column 7, line 43); a second interconnect line (2CL) immediately adjacent the first interconnect line (1CL), the second interconnect line (2CL) having a width (2CL has width 114; e.g. column 7, line 43); a third interconnect line (3CL) immediately adjacent the second interconnect line (2CL), the third interconnect line (3CL) having a width (3CL has width 116; e.g. column 7, line 50), wherein the width of the third interconnect line (116) is different than the width of the second interconnect line (114), and wherein the width of the third interconnect line (116) is different than the width of the first interconnect line (112); a fourth interconnect line (4CL) immediately adjacent the third interconnect line (3CL), the fourth interconnect line (4CL) having a width (4CL has width 110; e.g. column 7, line 43) the same as the width of the second interconnect line (114), wherein a first pitch (pitch labeled P1) between the first interconnect line (1CL) and the third interconnect line (3CL) is different than a second pitch (pitch labeled P2) between the second interconnect line (2CL) and the fourth interconnect line (4CL); a fifth interconnect line (5CL) immediately adjacent the fourth interconnect line (4CL), the fifth interconnect line (5CL) having a width (5CL has width 112; e.g. column 7, line 43) the same as the width of the first interconnect line (112); and a sixth interconnect line (6CL) immediately adjacent the fifth interconnect line (5CL), the sixth interconnect line (6CL) having a width (6CL has width 114; e.g. column 7, line 43) the same as the width of the second interconnect line (114).
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Although fig. 34 illustrates the width of interconnect line B (which has been cited as reading on 1CL and 5CL) as being wider than interconnect lines A and C (which has been cited as reading on 2CL, 4CL, and 6CL) the specification is silent as to explicitly teaching the claimed “second interconnect line having a width different than the width of the first interconnect line” however does state that the widths 110, 112, 114 are set substantially equal at column 7, line 44. The specification also states at column 8, lines 58-60 there is a great deal of flexibility in the widths of 110, 112, 114 which appears to allude to the fact that these widths can be selected with great flexibility according to the design specification of the device being designed and is a matter of design choice since there lacks unexpected results from the selection of these widths.
Therefore Licausi may be considered as being silent as to explicitly teaching the second interconnect line having a width different than the width of the first interconnect line, and the fourth interconnect line having a width the same as the width of the second interconnect line; and a second ILD layer above the ILD layer; and a second plurality of conductive interconnect lines in and spaced apart by the second ILD layer, each of the second plurality of conductive interconnect lines having a width greater than a greatest width of the first, second, third, fourth, fifth and sixth interconnect lines of the plurality of conductive interconnect lines.
Kornachuk teaches (labeled fig. 10C below) a set of wires with a width pattern which follows an ABCBABCB pattern where A, B, and C are different widths and further teaches (e.g. fig. 10C and labeled fig. 10C below which is labeled to correspond to the labels of fig. 34 of Licausi) the second interconnect line (line labeled “C2”) having a width (SRW) different than the width (w1) of the first interconnect line (line labeled “B1”), and the fourth interconnect line (line labeled “A4”) having a width (SRW) the same as the width (SRW) of the second interconnect line (C2).
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Therefore, it would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to create the widths of interconnect line A, B, and C into an ABCBABCB pattern in an application which requires such a signal line pattern. Since these widths are known dimensions to be modified in the art of semiconductor fabrication, there would be a high expectation of success when such a width is modified.
Licausi in view of Kornachuk is silent as to explicitly teaching a second plurality of conductive interconnect lines in and spaced apart by the second ILD layer, each of the second plurality of conductive interconnect lines having a width greater than a greatest width of the first, second, third, fourth, fifth and sixth interconnect lines of the plurality of conductive interconnect lines.
Chang teaches (e.g. figs. 1A, 1B, and 2) a second plurality of conductive interconnect lines (M4, however ICs may include more of less conductive layers than shown in fig. 1B depending on particular IC design; e.g. paragraph 18) in and spaced apart by the second ILD layer (M4 and other metallization levels are known to be built up on and embedded in dielectrics on lower ILD layers; hereinafter “ILD2”), each of the second plurality of conductive interconnect lines (M4) having a width greater than (M4 would have widths greater than any metallization pattern below it) a greatest width of the first, second, third, fourth, fifth and sixth interconnect lines (1CL, 2CL, 3CL, 4CL, 5CL, 6CL of Licausi) of the plurality of conductive interconnect lines.
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the addition of upper metallization layers as taught by Chang in the device of Licausi in view of Kornachuk in order to have the predictable result of using an interconnect structure required for the connection of IC elements.
Licausi in view of Kornachuk and Chang is silent as to explicitly teaching each of the first plurality of conductive interconnect lines including a first conductive barrier layer having a first barrier composition, and each of the first plurality of conductive interconnect lines including a first conductive fill having a first fill composition, and each of the second plurality of conductive interconnect lines including a second conductive barrier layer having a second barrier composition, the second barrier composition of the second conductive barrier layer different than the first barrier composition of the first conductive barrier layer, wherein one of the first barrier composition or the second barrier composition includes an outer layer and an inner layer, one of the outer layer or inner layer having a first metal species not included in the other one of the outer layer or inner layer, and the other one of the outer layer or inner layer having a second metal species not included in the one of the outer layer or inner layer , and each of the second plurality of conductive interconnect lines having a second conductive fill having a second fill composition, the second fill composition of the second conductive fill different than the first fill composition of the first conductive fill.
Himeno teaches (e.g. fig. 1) each of the first plurality of conductive interconnect lines (103) including a first conductive barrier layer (102) having a first barrier composition (first barrier metal layer 102 having a stacked structure of tantalum nitride and tantalum; e.g. paragraph 146), and each of the first plurality of conductive interconnect lines (103) including a first conductive fill having a first fill composition (metal wiring 103 made from a metal other than copper, for example aluminum; e.g. paragraph 105), and each of the second plurality of conductive interconnect lines (119) including a second conductive barrier layer (117) having a second barrier composition (third barrier metal layer 117 made of tantalum nitride; e.g. paragraph 175), the second barrier composition of the second conductive barrier layer (tantalum nitride 117) different than the first barrier composition of the first conductive barrier layer (stacked tantalum nitride and tantalum layers 102), and each of the second plurality of conductive interconnect lines (119) having a second conductive fill having a second composition (wiring trench 119 is filled with copper; e.g. paragraph 175), the second composition of the second conductive fill (copper) different than the first composition of the first conductive fill (aluminum).
Raaijmakers teaches (fig. 13) wherein one of the first barrier composition (WN/TiN bilayer barrier layer 150; e.g. paragraph 101) or the second barrier composition includes an outer layer (WN) and an inner layer (TiN), one of the outer layer or inner layer (TiN) having a first metal species (Ti is not contained in WN) not included in the other one of the outer layer (WN) or inner layer, and the other one of the outer layer (WN) or inner layer having a second metal species (W is not contained in TiN) not included in the one of the outer layer or inner layer (TiN).
It would have been obvious to one of ordinary skill in the art at the time of effective filling, absent unexpected results, to use the barrier metal layers as taught by Himeno and the bilayer barrier layer as taught by Raaijmakers in the device of Kornachuk in view of Smayling and Chang in order to have the predictable result of using the barrier metal layers such that the device lifetime can be improved by preventing diffusion of impurities into the interconnect lines as well as preventing metallic atoms from diffusion into the surrounding ILD layers, and in order to have the predictable result of using a bilayer barrier layer more capable of preventing ion diffusion, respectively.
Re claim 8: Licausi teaches (e.g. figs. 1, 2, 34 and labeled fig. 34 above) an integrated circuit structure, comprising: an inter-layer dielectric (ILD) layer (dielectric layer 104; e.g. column 7, line 13) above a substrate (108); and a first plurality of conductive interconnect lines (A, B, C, D; e.g. column 7, line 26) in and spaced apart by the ILD layer (104), the first plurality of conductive interconnect lines (A, B, C, D) comprising: a first interconnect line (1CL) having a width (1CL has width 112; e.g. column 7, line 43); a second interconnect line (2CL) immediately adjacent the first interconnect line (1CL), the second interconnect line (2CL) having a width (2CL has width 114; e.g. column 7, line 43); a third interconnect line (3CL) immediately adjacent the second interconnect line (2CL), the third interconnect line (3CL) having a width (3CL has width 116; e.g. column 7, line 50) different than the width of the first interconnect line (112), wherein the width of the third interconnect line (116) is different than the width of the second interconnect line (114); a fourth interconnect line (4CL) immediately adjacent the third interconnect line (3CL), the fourth interconnect line (4CL) having a width (4CL has width 110; e.g. column 7, line 43) the same as the width of the second interconnect line (114), wherein a first pitch (P1) between the first interconnect line (1CL) and the third interconnect line (3CL) is different than a second pitch (P2) between the second interconnect line (2CL) and the fourth interconnect line (4CL); a fifth interconnect line (5CL) immediately adjacent the fourth interconnect line (4CL), the fifth interconnect line (5CL) having a width (5CL has width 112; e.g. column 7, line 43) the same (5CL and 1CL are both labeled B signal lines with the same width 112) as the width of the first interconnect line (112); a sixth interconnect line (6CL) immediately adjacent the fifth interconnect line (5CL), the sixth interconnect line (6CL) having a width (6CL has width 114; e.g. column 7, line 43) the same (6CL and 1CL are labeled C and B, respectively, and are signal lines with the same width 112, 114) as the width of the second interconnect line (112); and a seventh interconnect line (7CL) immediately adjacent the sixth interconnect line (6CL), the seventh interconnect line (7CL) having a width (7CL has width 116; e.g. column 7, line 50) the same (3CL and 7CL are both labeled D and are power lines with the same width 116) as the width of the third interconnect line (116).
Although fig. 34 illustrates the width of interconnect line B (which has been cited as reading on 1CL and 5CL) as being wider than interconnect lines A and C (which has been cited as reading on 2CL, 4CL, and 6CL) the specification is silent as to explicitly teaching the claimed “second interconnect line having a width different than the width of the first interconnect line” however does state that the widths 110, 112, 114 are set substantially equal at column 7, line 44. The specification also states at column 8, lines 58-60 there is a great deal of flexibility in the widths of 110, 112, 114 which appears to allude to the fact that these widths can be selected with great flexibility according to the design specification of the device being designed and is a matter of design choice since there lacks unexpected results from the selection of these widths.
Therefore Licausi may be considered as being silent as to explicitly teaching the second interconnect line having a width different than the width of the first interconnect line, and the fourth interconnect line having a width the same as the width of the second interconnect line; and a second plurality of conductive interconnect lines in and spaced apart by the second ILD layer, each of the second plurality of conductive interconnect lines having a width greater than a greatest width of the first, second, third, fourth, fifth, sixth, and seventh interconnect lines of the plurality of conductive interconnect lines..
Kornachuk teaches (labeled fig. 10C above) a set of wires with a width pattern which follows an ABCBABCB pattern where A, B, and C are different widths and further teaches (e.g. fig. 10C and labeled fig. 10C below which is labeled to correspond to the labels of fig. 34 of Licausi) the second interconnect line (line labeled “C2”) having a width (SRW) different than the width (w1) of the first interconnect line (line labeled “B1”), and the fourth interconnect line (line labeled “A4”) having a width (SRW) the same as the width (SRW) of the second interconnect line (C2).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to create the widths of interconnect line A, B, and C into an ABCBABCB pattern in an application which requires such a signal line pattern. Since these widths are known dimensions to be modified in the art of semiconductor fabrication, there would be a high expectation of success when such a width is modified.
Licausi in view of Kornachuk is silent as to explicitly teaching a second plurality of conductive interconnect lines in and spaced apart by the second ILD layer, each of the second plurality of conductive interconnect lines having a width greater than a greatest width of the first, second, third, fourth, fifth, sixth, and seventh interconnect lines of the plurality of conductive interconnect lines.
Chang teaches (e.g. figs. 1A, 1B, and 2) a second plurality of conductive interconnect lines (M4, however ICs may include more of less conductive layers than shown in fig. 1B depending on particular IC design; e.g. paragraph 18) in and spaced apart by the second ILD layer (M4 and other metallization levels are known to be built up on and embedded in dielectrics on lower ILD layers; hereinafter “ILD2”), each of the second plurality of conductive interconnect lines (M4) having a width greater than (M4 would have widths greater than any metallization pattern below it) a greatest width of the first, second, third, fourth, fifth, sixth, and seventh interconnect lines (1CL, 2CL, 3CL, 4CL, 5CL, 6CL of Licausi) of the plurality of conductive interconnect lines.
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the addition of upper metallization layers as taught by Chang in the device of Licausi in view of Kornachuk in order to have the predictable result of using an interconnect structure required for the connection of IC elements.
Licausi in view of Kornachuk and Chang is silent as to explicitly teaching each of the first plurality of conductive interconnect lines including a first conductive barrier layer having a first barrier composition, and each of the first plurality of conductive interconnect lines including a first conductive fill having a first fill composition, and each of the second plurality of conductive interconnect lines including a second conductive barrier layer having a second barrier composition, the second barrier composition of the second conductive barrier layer different than the first barrier composition of the first conductive barrier layer, wherein one of the first barrier composition or the second barrier composition includes an outer layer and an inner layer, one of the outer layer or inner layer having a first metal species not included in the other one of the outer layer or inner layer, and the other one of the outer layer or inner layer having a second metal species not included in the one of the outer layer or inner layer , and each of the second plurality of conductive interconnect lines having a second conductive fill having a second fill composition, the second fill composition of the second conductive fill different than the first fill composition of the first conductive fill.
Himeno teaches (e.g. fig. 1) each of the first plurality of conductive interconnect lines (103) including a first conductive barrier layer (102) having a first barrier composition (first barrier metal layer 102 having a stacked structure of tantalum nitride and tantalum; e.g. paragraph 146), and each of the first plurality of conductive interconnect lines (103) including a first conductive fill having a first fill composition (metal wiring 103 made from a metal other than copper, for example aluminum; e.g. paragraph 105), and each of the second plurality of conductive interconnect lines (119) including a second conductive barrier layer (117) having a second barrier composition (third barrier metal layer 117 made of tantalum nitride; e.g. paragraph 175), the second barrier composition of the second conductive barrier layer (tantalum nitride 117) different than the first barrier composition of the first conductive barrier layer (stacked tantalum nitride and tantalum layers 102), and each of the second plurality of conductive interconnect lines (119) having a second conductive fill having a second composition (wiring trench 119 is filled with copper; e.g. paragraph 175), the second composition of the second conductive fill (copper) different than the first composition of the first conductive fill (aluminum).
Raaijmakers teaches (fig. 13) wherein one of the first barrier composition (WN/TiN bilayer barrier layer 150; e.g. paragraph 101) or the second barrier composition includes an outer layer (WN) and an inner layer (TiN), one of the outer layer or inner layer (TiN) having a first metal species (Ti is not contained in WN) not included in the other one of the outer layer (WN) or inner layer, and the other one of the outer layer (WN) or inner layer having a second metal species (W is not contained in TiN) not included in the one of the outer layer or inner layer (TiN).
It would have been obvious to one of ordinary skill in the art at the time of effective filling, absent unexpected results, to use the barrier metal layers as taught by Himeno and the bilayer barrier layer as taught by Raaijmakers in the device of Kornachuk in view of Smayling and Chang in order to have the predictable result of using the barrier metal layers such that the device lifetime can be improved by preventing diffusion of impurities into the interconnect lines as well as preventing metallic atoms from diffusion into the surrounding ILD layers, and in order to have the predictable result of using a bilayer barrier layer more capable of preventing ion diffusion, respectively.
Claims 15, 17, 19, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kornachuk in view of Chang et al. (US 2017/0194252; hereinafter “Chang”), Doyle (US PGPub 2005/02015040), Himeno, and Raaijmakers et al. (US PGPub 2004/0130029; hereinafter “Raaijmakers”).
Re claim 15: Kornachuk teaches (e.g. labeled fig. 10c above) a method of fabricating an integrated circuit structure, the method comprising: forming a first plurality of conductive interconnect lines (wire lines 1020, 1060, 1030, 1061, 1024; hereinafter “1CIL”) in and spaced apart by a first inter-layer dielectric (ILD) layer (patterned conductive layers are insulated from other conductive layers by dielectric materials; hereinafter “1ILD”; e.g. paragraph 131) above a substrate (substrate upon which wires are formed; hereinafter “S”; e.g. paragraph 131), and wherein the first plurality of conductive interconnect lines (1CIL) comprises a first interconnect line (wire 1020 labeled “B1”) having a width (w1), and a second interconnect line (wire 1060 labeled “C2”) immediately adjacent the first interconnect line (B1), the second interconnect line (C2) having a width (SRW) different than the width (w1) of the first interconnect line (B1), and a third interconnect line (wire 1030 labeled “D3”) immediately adjacent the second interconnect line (C2), the third interconnect line (D3) having a width (w2), wherein the width (w2) of the third interconnect line (D3) is different than the width (SRW) of the second interconnect line (C2), and wherein the width (w2) of the third interconnect line (D3) is different than the width (w1) of the first interconnect line (B1), and a fourth interconnect line (wire 1061 labeled “A4”) immediately adjacent the third interconnect line (D3), the fourth interconnect line (A4) having a width (SRW) the same as the width (SRW) of the second interconnect line (C2), wherein a first pitch (pitch between B1 and D3) between the first interconnect line (B1) and the third interconnect line (D3) is different (pitches are between different lines) than a second pitch (pitch between C2 and A4) between the second interconnect line (C2) and the fourth interconnect line (A4), and a fifth interconnect line (wire 1024 labeled “B5”) immediately adjacent the fourth interconnect line (A4), the fifth interconnect line (B5) having a width (w1) the same as the width (w1) of the first interconnect line (B1), and a sixth interconnect line (wire 1060 labeled “C6”) immediately adjacent the fifth interconnect line (B5), the sixth interconnect line (C6) having a width (SRW) the same as the width (SRW) of the second interconnect line (C2).
Kornachuk is silent as to explicitly teaching forming a second plurality of conductive interconnect lines in and spaced apart by a second ILD layer above the first ILD layer; wherein the first plurality of conductive interconnect lines is formed using a spacer-based pitch quartering process where a first set of spacers is used as a mask during etching in a first etching process; wherein the second plurality of conductive interconnect lines is formed using a spacer-based pitch halving process where a second set of spacers is used as a mask during etching in a second etching process; and each of the second plurality of conductive interconnect lines having a width greater than a greatest width of the first, second, third, fourth, fifth and six interconnect lines of the plurality of conductive interconnect lines.
Chang teaches (e.g. figs. 1A, 1B, and 2) forming a second plurality of conductive interconnect lines (M4, however ICs may include more of less conductive layers than shown in fig. 1B depending on particular IC design; e.g. paragraph 18) in and spaced apart by a second ILD layer (M4 are known to be embedded in dielectric built-up on lower ILD layers; hereinafter “ILD2”) above the first ILD layer (1ILD of Kornachuk); and each of the second plurality of conductive interconnect lines (M4) having a width greater than a greatest width of the first, second, third, fourth, fifth and six interconnect lines (B1, C2, D3, A4, B5, C6, D7 of Kornachuk) of the plurality of conductive interconnect lines
Doyle teaches (e.g. figs. 2A-F) wherein the first plurality of conductive interconnect lines (1CIL of Kornachuk) is formed using a spacer-based pitch quartering process (masking sequence from fig.2A-F of Doyle; hereinafter “PQP”) where a first set of spacers (26 of fig. 2F of Doyle is at a quarter pitch mask state as well as discussed at paragraph 67-69) is used as a mask during etching in a first etching process (etching performed for the creation of 1CIL of Kornachuk, etching being a standard process); wherein the second plurality of conductive interconnect lines (M4 of Chang) is formed using a spacer-based pitch halving process (masking sequence from fig.2A-D of Doyle; hereinafter “PHP”) where a second set of spacers (18 of fig. 2C is at a half pitch mask state) is used as a mask during etching in a second etching process (etching performed for the creation of M4, etching being discussed at paragraph 4 as being a standard process).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the addition of upper metallization layers as taught by Chang and to use the masking method as taught by Doyle in the method of Kornachuk in order to have the predictable result of using an interconnect structure required for the connection of IC elements and in order to have the predictable result of using a masking sequence capable of smaller critical dimension features, respectively.
Further, there is a high expectation of success that the use of spacer-based quarter and half pitch masks since it is merely a masking process well-known to photolithographic processes, as evidenced by Lowrey et al. (US 5,328,810) which discloses in the abstract the use of half-pitch masks and repeating the creation of half-pitch masks to create quarter-pitch masks to pattern underlying layers. Lowrey’s disclosure was patented over 25 years ago.
Licausi in view of Chang and Doyle is silent as to explicitly teaching each of the first plurality of conductive interconnect lines including a first conductive barrier layer having a first barrier composition, and each of the first plurality of conductive interconnect lines including a first conductive fill having a first fill composition, and each of the second plurality of conductive interconnect lines including a second conductive barrier layer having a second barrier composition, the second barrier composition of the second conductive barrier layer different than the first barrier composition of the first conductive barrier layer, wherein one of the first barrier composition or the second barrier composition includes an outer layer and an inner layer, one of the outer layer or inner layer having a first metal species not included in the other one of the outer layer or inner layer, and the other one of the outer layer or inner layer having a second metal species not included in the one of the outer layer or inner layer , and each of the second plurality of conductive interconnect lines having a second conductive fill having a second fill composition, the second fill composition of the second conductive fill different than the first fill composition of the first conductive fill.
Himeno teaches (e.g. fig. 1) each of the first plurality of conductive interconnect lines (103) including a first conductive barrier layer (102) having a first barrier composition (first barrier metal layer 102 having a stacked structure of tantalum nitride and tantalum; e.g. paragraph 146), and each of the first plurality of conductive interconnect lines (103) including a first conductive fill having a first fill composition (metal wiring 103 made from a metal other than copper, for example aluminum; e.g. paragraph 105), and each of the second plurality of conductive interconnect lines (119) including a second conductive barrier layer (117) having a second barrier composition (third barrier metal layer 117 made of tantalum nitride; e.g. paragraph 175), the second barrier composition of the second conductive barrier layer (tantalum nitride 117) different than the first barrier composition of the first conductive barrier layer (stacked tantalum nitride and tantalum layers 102), and each of the second plurality of conductive interconnect lines (119) having a second conductive fill having a second composition (wiring trench 119 is filled with copper; e.g. paragraph 175), the second composition of the second conductive fill (copper) different than the first composition of the first conductive fill (aluminum).
Raaijmakers teaches (fig. 13) wherein one of the first barrier composition (WN/TiN bilayer barrier layer 150; e.g. paragraph 101) or the second barrier composition includes an outer layer (WN) and an inner layer (TiN), one of the outer layer or inner layer (TiN) having a first metal species (Ti is not contained in WN) not included in the other one of the outer layer (WN) or inner layer, and the other one of the outer layer (WN) or inner layer having a second metal species (W is not contained in TiN) not included in the one of the outer layer or inner layer (TiN).
It would have been obvious to one of ordinary skill in the art at the time of effective filling, absent unexpected results, to use the barrier metal layers as taught by Himeno and the bilayer barrier layer as taught by Raaijmakers in the device of Kornachuk in view of Smayling and Chang in order to have the predictable result of using the barrier metal layers such that the device lifetime can be improved by preventing diffusion of impurities into the interconnect lines as well as preventing metallic atoms from diffusion into the surrounding ILD layers, and in order to have the predictable result of using a bilayer barrier layer more capable of preventing ion diffusion, respectively.
Re claim 17: Kornachuk in view of Chang and Doyle teaches the method wherein the spacer-based pitch quartering process and the spacer-based pitch halving process are based on an immersion 193nm lithography process (many masking and exposure processes can be adapted to immersion 193-nm lithography schemes, as evidenced by US PGPub 2011/0039061).
Re claim 19: Kornachuk in view of Chang and Doyle teaches the method further comprising: forming a third plurality of conductive interconnect lines (M5 metallization as shown in fig. 1B of Chang) in and spaced apart by a third ILD layer (the metallization lines M5 are known to be embedded in a third dielectric; hereinafter “ILD3”) above the second ILD layer (ILD2 of Chang), wherein the third plurality of conductive interconnect lines (M5 of Chang) is formed without using pitch division (M5 of Chang is a coarse layer and would not require pitch division since the dimensions are not small, as would have been recognized by one of ordinary skill in the art).
Re claim 20: Kornachuk in view of Chang and Doyle teaches the method further comprising: prior to forming the second plurality of conductive interconnect lines (M4), forming a third plurality of conductive interconnect lines (M2 as shown in fig. 1B of Chang”) in and spaced apart by a third ILD layer (the metallization lines M2 are known to be embedded in a third dielectric; hereinafter “ILD3”) above the first ILD layer (ILD1 of Chang), wherein the third plurality of conductive interconnect lines (M2) is formed using a spacer-based pitch quartering process (PQP of Doyle); subsequent to forming the second plurality of conductive interconnect lines (M2), forming a fourth plurality of conductive interconnect lines (M3 as shown in fig. 1B of Chang) in and spaced apart by a fourth ILD layer (the metallization lines M3 are known to be embedded in a fourth dielectric; hereinafter “ILD4”) above the second ILD layer (ILD2), wherein the fourth plurality of conductive interconnect lines (M3) is formed using a spacer-based pitch halving process (PHP of Doyle); forming a fifth plurality of conductive interconnect lines (M5 as shown in fig. 1B of Chang) in and spaced apart by a fifth ILD layer (M5 are known to be embedded in a fifth dielectric; hereinafter “ILD5”) above the fourth ILD layer (ILD4), wherein the fifth plurality of conductive interconnect lines (M5) is formed using a spacer-based pitch halving process (PHP of Doyle); forming a sixth plurality of conductive interconnect lines (M6 as shown in fig. 1B of Chang) in and spaced apart by a sixth ILD layer (M6 are known to be embedded in a sixth dielectric; hereinafter “ILD6”) above the fifth ILD layer (ILD5), wherein the sixth plurality of conductive interconnect lines (M6) is formed using a spacer-based pitch halving process (PHP of Doyle); and forming a seventh plurality of conductive interconnect lines (M7 as shown in fig. 1B of Chang) in and spaced apart by a seventh ILD layer (M7 are known to be embedded in a seventh dielectric; hereinafter “ILD7”) above the sixth ILD layer (ILD6), wherein the seventh plurality of conductive interconnect lines (M7) is formed without using pitch division (M7 is a coarse layer and would not require pitch division since the dimensions are not small, as would have been recognized by one of ordinary skill in the art).
Claim 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kornachuk in view of Chang, Doyle, Himeno, and Raaijmakers, as applied to claim 15 above, and further in view of Stephens et al. (US 9,852,986; hereinafter “Stephens”).
Re claim 16: Kornachuk in view of Doyle teaches substantially the method as recited in claim 15 except explicitly teaching the method wherein first plurality of conductive interconnect lines has a pitch between immediately adjacent lines of less than 40 nanometers, and wherein the second plurality of conductive interconnect lines has a pitch between immediately adjacent lines of 44 nanometers or greater.
Stephens teaches the method wherein first plurality of conductive interconnect lines (1CIL of Kornachuk) has a pitch between immediately adjacent lines of less than 40 nanometers (spacer pitch is set to 40 nm to be half the original mandrel pitch 136; e.g. column 7, lines 53-57 of Stephens), and wherein the second plurality of conductive interconnect lines (M4 of Chang) has a pitch between immediately adjacent lines of 44 nanometers or greater (original mandrel pitch is 80 nm; e.g. column 7, lines 53-57).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the half and quarter pitch mask dimensions as taught by Stephens in the method of Endo in view of Chang, Doyle, Himeno and Lee in order to have the predictable result of creating the device of Endo in an application which requires the use of mask pitch dimensions of 40nm and 80nm.
Conclusion
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2822
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