UNITED STATES PATENT AND TRADEMARKS OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO.
16/542,960
FILING DATE
08/16/2019
FIRST NAMED INVENTOR
Andrew W. YEOH
ATTORNEY DOCKET NO.
AA6131-US-
C1 111548249691
CONFIRMATION NO.
1019
31817
7590
02/12/2026
SCHWABE, WILLIAMSON & WYATT, P.C.
1211 SW 5th Avenue, Suite 1800
Portland, OR 97204
ART UNIT
2898
EXAMINER
MIYOSHI, JESSE Y
PAPER NUMBER
NOTIFICATION DATE
DELIVERY MODE
02/12/2026
ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
IPDocketing@SCHWABE.com
intelparalegal@schwabe.com
patent@schwabe.com
PTOL-90A (Rev. 04/07)
Office Action Summary
Application No.
16/542,960
Applicant(s)
YEOH et al.
Examiner
JESSE Y MIYOSHI
Art Unit
2898
AIA (First Inventor to
File) Status Yes
-- The MAILING DATE of this communication appears on the cover sheet with the correspondence address --
Period for Reply
A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE 3 MONTHS FROM THE MAILING
DATE OF THIS COMMUNICATION.
Status
Extensions of time may be available under the provisions of 37 CFR 1.136(a). In no event, however, may a reply be timely filed after SIX (6) MONTHS from the mailing
date of this communication.
If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
Any reply received by the Office later than three months after the mailing date of this communication, even if timely filed, may reduce any earned patent term
adjustment. See 37 CFR 1.704(b).
1) Responsive to communication(s) filed on 07 October 2025.
2a) ☐ A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/were filed on
2b) ☐ This action is non-final.
This action is FINAL.
3) ☐ An election was made by the applicant in response to a restriction requirement set forth during the interview
on; the restriction requirement and election have been incorporated into this action.
4) ☐ Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
closed in accordance with the practice under Ex parte Quayle, 1935 C.D. 11, 453 O.G. 213.
Disposition of Claims*
5) Claim(s) 2,5,8,11-19 and 21 is/are pending in the application.
5a) Of the above claim(s) 8 is/are withdrawn from consideration.
☐ Claim(s)
is/are allowed.
6)
7) ☐ Claim(s) 2,5,11-19 and 21 is/are rejected.
8) ☐ Claim(s)
is/are objected to.
9) ☐ Claim(s) are subject to restriction and/or election requirement
* If any claims have been determined allowable, you may be eligible to benefit from the Patent Prosecution Highway program at a
participating intellectual property office for the corresponding application. For more information, please see
http://www.uspto.gov/patents/init_events/pph/index.jsp or send an inquiry to PPHfeedback@uspto.gov.
Application Papers
10) ☐ The specification is objected to by the Examiner.
11) The drawing(s) filed on
is/are: a) accepted or b)☐ objected to by the Examiner.
Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121(d).
Priority under 35 U.S.C. § 119
12) ☐ Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).
Certified copies:
a) All b) Some** c) None of the:
☐ Certified copies of the priority documents have been received.
1.
2. ☐ Certified copies of the priority documents have been received in Application No.
3. ☐ Copies of the certified copies of the priority documents have been received in this National Stage
application from the International Bureau (PCT Rule 17.2(a)).
** See the attached detailed Office action for a list of the certified copies not received.
Attachment(s)
1) ☐ Notice of References Cited (PTO-892)
2) ☐ Information Disclosure Statement(s) (PTO/SB/08a and/or PTO/SB/08b)
Paper No(s)/Mail Date
U.S. Patent and Trademark Office
PTOL-326 (Rev. 11-13)
Office Action Summary
3) ☐ Interview Summary (PTO-413)
Paper No(s)/Mail Date
☐ Other:
Part of Paper No./Mail Date 20260209
Application/Control Number: 16/542,960
Art Unit: 2898
DETAILED ACTION
Notice of Pre-AIA or AIA Status
Page 2
1. The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA.
2. Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set
forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this
application is eligible for continued examination under 37 CFR 1.114, and the fee set
forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action
has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on
10/7/2025 has been entered.
3. Response to Arguments
Applicant's arguments filed 9/9/2025 with respect to the pending claims have
been fully considered but are moot in view of the new grounds of rejection.
4. Applicant argues that the prior art does not disclose the newly added limitation.
This argument is not persuasive since the reference to Raaijmakers et al. (US
PGPub 2004/0130029) teaches these limitation. The drawing objection was not
addressed, therefore are being maintained.
5. The rejection has updated to include the newly added limitations.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show
every feature of the invention specified in the claims. Therefore, the widths of each
Application/Control Number: 16/542,960
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Page 3
interconnect line and the respective pitches as claimed must be shown or the feature(s)
canceled from the claim (s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in
reply to the Office action to avoid abandonment of the application. Any amended
replacement drawing sheet should include all of the figures appearing on the immediate
prior version of the sheet, even if only one figure is being amended. The figure or figure
number of an amended drawing should not be labeled as "amended." If a drawing figure
is to be canceled, the appropriate figure must be removed from the replacement sheet,
and where necessary, the remaining figures must be renumbered and appropriate
changes made to the brief description of the several views of the drawings for
consistency. Additional replacement sheets may be necessary to show the renumbering
of the remaining figures. Each drawing sheet submitted after the filing date of an
application must be labeled in the top margin as either "Replacement Sheet" or "New
Sheet" pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner,
the applicant will be notified and informed of any required corrective action in the next
Office action. The objection to the drawings will not be held in abeyance.
Applicant argues that fig. 55A shows claimed features. Examiner respectfully
disagrees. As can be seen from the figures, each wiring is drawn to be the same width,
where clearly the claims explicitly claim certain metal lines as being the same widths
and certain metal lines being different widths. The claims further require the pitches P1
and P3 to be equal to each other. The instant invention claiming these features with
specificity should illustrate the invention with equal specificity if this is the focal point of
the instant application's novelty.
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Art Unit: 2898
Page 4
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all
obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed
invention is not identically disclosed as set forth in section 102, if the differences between the
claimed invention and the prior artare such that the claimed invention as a whole would have
been obvious before the effective filing date of the claimed invention to a person having
ordinary skill in the art to which the claimed invention pertains. Patentability shall not be
negated by the manner in which the invention was made.
7. Claims 2, 5, 11-19, and 21 is/are rejected under 35 U.S.C. 103 as being
unpatentable over Kornachuk et al. (US PGPub 2009/0300575; hereinafter
"Kornachuk") in view of Smayling et al. (US PGPub 2008/0222587; hereinafter
"Smayling") and Chang et al. (US PGPub 2017/0194252; hereinafter “Chang”), Himeno
et al. (US PGPub 20130112935; hereinafter “Himeno”), and Raaijmakers et al. (US
PGPub 2004/0130029; hereinafter “Raaijmakers”).
Re claim 2: Kornachuk teaches (e.g. fig. 10C and labeled fig. 10C below) an
integrated circuit structure, comprising: an inter-layer dielectric (ILD) layer (dielectric
materials insulate patterned conductive layers from each other; e.g. paragraph 132;
hereinafter "IL") above a substrate (multi-level structures defined on a silicon substrate;
e.g. paragraph 132); and a first plurality of conductive interconnect lines (1061, 1030,
1060, 1020 as shown in fig. 10C and labeled fig. 10C; hereinafter “CIL") in and spaced
apart by the ILD layer (IL), the first plurality of conductive interconnect lines (CIL)
comprising: a first interconnect line (top-most 1060 as shown in labeled fig. 10C and
labeled as "A1") having a width (SRW); a second interconnect line (top-most 1030 as
shown in labeled fig. 10C and labeled as "B2") immediately adjacent the first
interconnect line (A1), the second interconnect line (B2) having a width (W2) different
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Page 5
than the width (SRW) of the first interconnect line (A1); a third interconnect line (1061
as shown in fig. 10C and labeled as "A3") immediately adjacent the second interconnect
line (B2), the third interconnect line (A3) having a width (SRW) the same as the width
(SRW) of the first interconnect line (A1); and a fourth interconnect line (1024 as shown
in labeled fig. 10C and labeled as "C4") immediately adjacent the third interconnect line
(A3), the fourth interconnect line (C4) having a width (W1) different than the width of the
first interconnect line (A1), and the width (W1) of the fourth interconnect line (C4)
different than the width (W2) of the second interconnect line (B2).
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Page 6
Fig. 10c Labeled by
Examiner
1020
100
A1
101
B2
201
A3
103
C4
1060
A5
1030
B6
104
Kornachuk is silent as to explicitly teaching a fifth interconnect line immediately
adjacent the fourth interconnect line, the fifth interconnect line having a width the same
as the width of the first interconnect line; and a sixth interconnect line immediately
adjacent the fifth interconnect line, the sixth interconnect line having a width the same
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Art Unit: 2898
as the width of the second interconnect line; a second ILD layer above the ILD layer;
and a second plurality of conductive interconnect lines in and spaced apart by the
second ILD layer, each of the second plurality of conductive interconnect lines having a
width greater than a greatest width of the first, second, third, fourth, fifth and sixth
interconnect lines of the plurality of conductive interconnect lines.
Smayling teaches, as shown in figs. 5A-5F, that sub-layouts can be formed such
that they are combined to generate a desired sequence of M2 level layouts 505A, 505B,
for example, combining cell variant 501A and cell variant 501B, as chosen in figs. 5D,
5E, to have alternating M2 layers 505A, 505B (which maintains an ABAB-ABAB
pattern) and alternating lines 503A, 503B (which maintains an ABAB pattern by
combining ABA-BAB cells). This concept can be applied to the structure of fig. 10C of
Kornachuk by repeating 1061, 1030, 1060, and 1020, which when repeating would have
a structure similar to 1060, 1061 be immediately adjacent to 1020 as shown in labeled
fig. 10C above, these additional repeating element will be referred to as labeled
elements "A5" and "B6".
Therefore Kornachuk in view of Smayling teaches a fifth interconnect line (A5 of
Kornachuk) immediately adjacent the fourth interconnect line (C4 of Kornachuk), the
fifth interconnect line (A5) having a width (SRW) the same as the width (SRW) of the
first interconnect line (A1); and a sixth interconnect line (B6 of Kornachuk) immediately
adjacent the fifth interconnect line (A5 of Kornachuk), the sixth interconnect line (B6 of
Kornachuk) having a width (W2) the same as the width (W2) of the second interconnect
line (B2 of Kornachuk).
Application/Control Number: 16/542,960
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Page 8
It would have been obvious to one of ordinary skill in the art at the time of
effective filing, absent unexpected results, to use the known method of repeating
metallization lines in predetermined layout patterns to achieve a desired layout as
taught by Smayling in the device of Kornachuk in order to have the predictable result of
using a known method of repeating metallization structures since in semiconductor
device fabrication, these structures are not made in a one at a time sequence but rather
plural identical structures are formed across an entire wafer and these plurality of these
elements are made.
Kornachuk in view of Smayling is silent as to explicitly teaching a second ILD
layer above the ILD layer; and a second plurality of conductive interconnect lines in and
spaced apart by the second ILD layer, each of the second plurality of conductive
interconnect lines having a width greater than a greatest width of the first, second, third,
fourth, fifth and sixth interconnect lines of the plurality of conductive interconnect lines.
Chang teaches (e.g. figs. 1A and 1B) the general concept of metallization lines
and their use to gradually increase in size as metallization layers get further from the
semiconductor device so that the signal lines can be large enough to interface with
external connections. Chang further teaches a second ILD layer (ILD layer provided
between each metallization layers M2, M3, M4, M5, M6, M7; hereinafter “2ILD”) above
the ILD layer (IL of Kornachuk); and a second plurality of conductive interconnect lines
(110 of metallization level M5) in and spaced apart by the second ILD layer (2ILD), each
of the second plurality of conductive interconnect lines (110) having a width greater than
a greatest width of the first, second, third, fourth, fifth and sixth interconnect lines (A1,
Application/Control Number: 16/542,960
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Page 9
B2, A3, C4 of Kornachuk and A5, B6 of Kornachuk in view of Smayling) of the plurality
of conductive interconnect lines (CIL of Kornachuk).
It would have been obvious to one of ordinary skill in the art at the time of
effective filing, absent unexpected results, to use the higher metallization lines as taught
by Chang in the device of Kornachuk in view of Smayling in order to have the
predictable results of using known fan-out interconnection structures to increase
metallization line widths and pitches so that the semiconductor device can make
external connections and be able to be packaged into a device.
Kornachuk in view of Smayling and Chang is silent as to explicitly teaching each
of the first plurality of conductive interconnect lines including a first conductive barrier
layer having a first barrier composition, and each of the first plurality of conductive
interconnect lines including a first conductive fill having a first fill composition, and each
of the second plurality of conductive interconnect lines including a second conductive
barrier layer having a second barrier composition, the second barrier composition of the
second conductive barrier layer different than the first barrier composition of the first
conductive barrier layer, wherein one of the first barrier composition or the second
barrier composition includes an outer layer and an inner layer, one of the outer layer or
inner layer having a first metal species not included in the other one of the outer layer or
inner layer, and the other one of the outer layer or inner layer having a second metal
species not included in the one of the outer layer or inner layer, and each of the second
plurality of conductive interconnect lines having a second conductive fill having a
second fill composition, the second fill composition of the second conductive fill different
than the first fill composition of the first conductive fill.
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Page 10
Himeno teaches (e.g. fig. 1) each of the first plurality of conductive interconnect
lines (103) including a first conductive barrier layer (102) having a first barrier
composition (first barrier metal layer 102 having a stacked structure of tantalum nitride
and tantalum; e.g. paragraph 146), and each of the first plurality of conductive
interconnect lines (103) including a first conductive fill having a first fill composition
(metal wiring 103 made from a metal other than copper, for example aluminum; e.g.
paragraph 105), and each of the second plurality of conductive interconnect lines (119)
including a second conductive barrier layer (117) having a second barrier composition
(third barrier metal layer 117 made of tantalum nitride; e.g. paragraph 175), the second
barrier composition of the second conductive barrier layer (tantalum nitride 117)
different than the first barrier composition of the first conductive barrier layer (stacked
tantalum nitride and tantalum layers 102), and each of the second plurality of conductive
interconnect lines (119) having a second conductive fill having a second fill composition
(wiring trench 119 is filled with copper; e.g. paragraph 175), the second fill composition
of the second conductive fill (copper) different than the first fill composition of the first
conductive fill (aluminum).
Raaijmakers teaches (fig. 13) wherein one of the first barrier composition
(WN/TiN bilayer barrier layer 150; e.g. paragraph 101) or the second barrier
composition includes an outer layer (WN) and an inner layer (TiN), one of the outer
layer or inner layer (TiN) having a first metal species (Ti is not contained in WN) not
included in the other one of the outer layer (WN) or inner layer, and the other one of the
outer layer (WN) or inner layer having a second metal species (W is not contained in
TiN) not included in the one of the outer layer or inner layer (TIN).
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Page 11
It would have been obvious to one of ordinary skill in the art at the time of
effective filling, absent unexpected results, to use the barrier metal layers as taught by
Himeno and the bilayer barrier layer as taught by Raaijmakers in the device of
Kornachuk in view of Smayling and Chang in order to have the predictable result of
using the barrier metal layers such that the device lifetime can be improved by
preventing diffusion of impurities into the interconnect lines as well as preventing
metallic atoms from diffusion into the surrounding ILD layers, and in order to have the
predictable result of using a bilayer barrier layer more capable of preventing ion
diffusion, respectively.
Re claim 5: Kornachuk teaches the integrated circuit structure wherein a pitch
(twice the distance labeled P1 in fig. 10C) between the first interconnect line (A1) and
the third interconnect line (A3) is the same as a pitch (twice the distance labeled P1 in
fig. 10C) between the second interconnect line (B2) and the fourth interconnect line
(C4).
Re claim 11: Kornachuk teaches (e.g. fig. 10C and labeled fig. 10C above) a
computing device, comprising: integrated circuit structure, comprising: an inter-layer
dielectric (ILD) layer (dielectric materials insulate patterned conductive layers from each
other; e.g. paragraph 132; hereinafter “IL”) above a substrate (multi-level structures
defined on a silicon substrate; e.g. paragraph 132); and a first plurality of conductive
interconnect lines (1061, 1030, 1060, 1020 as shown in fig. 10C; hereinafter “CIL") in
and spaced apart by the ILD layer (IL), the first plurality of conductive interconnect lines
(CIL) comprising: a first interconnect line (top-most 1060 as shown in labeled fig. 10C
and labeled as "A1") having a width (SRW); a second interconnect line (top-most 1030
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Page 12
as shown in labeled fig. 10C and labeled as "B2") immediately adjacent the first
interconnect line (A1), the second interconnect line (B2) having a width (W2) different
than the width (SRW) of the first interconnect line (A1); a third interconnect line (1061
as shown in fig. 10C and labeled as "A3") immediately adjacent the second interconnect
line (B2), the third interconnect line (A3) having a width (SRW) the same as the width
(SRW) of the first interconnect line (A1); and a fourth interconnect line (1024 as shown
in labeled fig. 10C and labeled as "C4") immediately adjacent the third interconnect line
(A3), the fourth interconnect line (C4) having a width (W1) different than the width of the
first interconnect line (A1), and the width (W1) of the fourth interconnect line (C4)
different than the width (W2) of the second interconnect line (B2).
Kornachuk is silent as to explicitly teaching a fifth interconnect line immediately
adjacent the fourth interconnect line, the fifth interconnect line having a width the same
as the width of the first interconnect line; and a sixth interconnect line immediately
adjacent the fifth interconnect line, the sixth interconnect line having a width the same
as the width of the second interconnect line; a second ILD layer above the ILD layer;
and a second plurality of conductive interconnect lines in and spaced apart by the
second ILD layer, each of the second plurality of conductive interconnect lines having a
width greater than a greatest width of the first, second, third, fourth, fifth and sixth
interconnect lines of the plurality of conductive interconnect lines.
Smayling teaches, as shown in figs. 5A-5F, that sub-layouts can be formed such
that they are combined to generate a desired sequence of M2 level layouts 505A, 505B,
for example, combining cell variant 501A and cell variant 501B, as chosen in figs. 5D,
5E, to have alternating M2 layers 505A, 505B (which maintains an ABAB-ABAB
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Page 13
pattern) and alternating lines 503A, 503B (which maintains an ABAB pattern by
combining ABA-BAB cells). This concept can be applied to the structure of fig. 10C of
Kornachuk by repeating 1061, 1030, 1060, and 1020, which when repeating would have
a structure similar to 1060, 1061 be immediately adjacent to 1020 as shown in labeled
fig. 10C above, these additional repeating element will be referred to as labeled
elements "A5" and "B6".
Therefore Kornachuk in view of Smayling teaches a fifth interconnect line (A5 of
Kornachuk) immediately adjacent the fourth interconnect line (C4 of Kornachuk), the
fifth interconnect line (A5) having a width (SRW) the same as the width (SRW) of the
first interconnect line (A1); and a sixth interconnect line (B6 of Kornachuk) immediately
adjacent the fifth interconnect line (A5 of Kornachuk), the sixth interconnect line (B6 of
Kornachuk) having a width (W2) the same as the width (W2) of the second interconnect
line (B2 of Kornachuk).
It would have been obvious to one of ordinary skill in the art at the time of
effective filing, absent unexpected results, to use the known method of repeating
metallization lines in predetermined layout patterns to achieve a desired layout as
taught by Smayling in the device of Kornachuk in order to have the predictable result of
using a known method of repeating metallization structures since in semiconductor
device fabrication, these structures are not made in a one at a time sequence but rather
plural identical structures are formed across an entire wafer and these plurality of these
elements are made.
Kornachuk in view of Smayling is silent as to explicitly teaching a second ILD
layer above the ILD layer; and a second plurality of conductive interconnect lines in and
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Page 14
spaced apart by the second ILD layer, each of the second plurality of conductive
interconnect lines having a width greater than a greatest width of the first, second, third,
fourth, fifth and sixth interconnect lines of the plurality of conductive interconnect lines.
Chang teaches (e.g. figs. 1A and 1B) the general concept of metallization lines
and their use to gradually increase in size as metallization layers get further from the
semiconductor device so that the signal lines can be large enough to interface with
external connections. Chang further teaches a second ILD layer (ILD layer provided
between each metallization layers M2, M3, M4, M5, M6, M7; hereinafter "2ILD") above
the ILD layer (IL of Kornachuk); and a second plurality of conductive interconnect lines
(110 of metallization level M5) in and spaced apart by the second ILD layer (2ILD), each
of the second plurality of conductive interconnect lines (110) having a width greater than
a greatest width of the first, second, third, fourth, fifth and sixth interconnect lines (A1,
B2, A3, C4 of Kornachuk and A5, B6 of Kornachuk in view of Smayling) of the plurality
of conductive interconnect lines (CIL of Kornachuk).
It would have been obvious to one of ordinary skill in the art at the time of
effective filing, absent unexpected results, to use the higher metallization lines as taught
by Chang in the device of Kornachuk in view of Smayling in order to have the
predictable results of using known fan-out interconnection structures to increase
metallization line widths and pitches so that the semiconductor device can make
external connections and be able to be packaged into a device.
Kornachuk in view of Smayling and Chang is silent as to explicitly teaching each
of the first plurality of conductive interconnect lines including a first conductive barrier
layer having a first composition, and each of the first plurality of conductive interconnect
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Page 15
lines including a first conductive fill having a first composition, and each of the second
plurality of conductive interconnect lines including a second conductive barrier layer
having a second composition, the second composition of the second conductive barrier
layer different than the first barrier composition of the first conductive barrier layer,
wherein one of the first barrier composition or the second barrier composition includes
an outer layer and an inner layer, one of the outer layer or inner layer having a first
metal species not included in the other one of the outer layer or inner layer, and the
other one of the outer layer or inner layer having a second metal species not included in
the one of the outer layer or inner layer, and each of the second plurality of conductive
interconnect lines having a second conductive fill having a second composition, the
second composition of the second conductive fill different than the first composition of
the first conductive fill.
Himeno teaches (e.g. fig. 1) each of the first plurality of conductive interconnect
lines (103) including a first conductive barrier layer (102) having a first barrier
composition (first barrier metal layer 102 having a stacked structure of tantalum nitride
and tantalum; e.g. paragraph 146), and each of the first plurality of conductive
interconnect lines (103) including a first conductive fill having a first fill composition
(metal wiring 103 made from a metal other than copper, for example aluminum; e.g.
paragraph 105), and each of the second plurality of conductive interconnect lines (119)
including a second conductive barrier layer (117) having a second barrier composition
(third barrier metal layer 117 made of tantalum nitride; e.g. paragraph 175), the second
barrier composition of the second conductive barrier layer (tantalum nitride 117)
different than the first barrier composition of the first conductive barrier layer (stacked
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Art Unit: 2898
tantalum nitride and tantalum layers 102), and each of the second plurality of conductive
interconnect lines (119) having a second conductive fill having a second fill composition
(wiring trench 119 is filled with copper; e.g. paragraph 175), the second fill composition
of the second conductive fill (copper) different than the first fill composition of the first
conductive fill (aluminum).
Raaijmakers teaches (fig. 13) wherein one of the first barrier composition
(WN/TiN bilayer barrier layer 150; e.g. paragraph 101) or the second barrier
composition includes an outer layer (WN) and an inner layer (TiN), one of the outer
layer or inner layer (TiN) having a first metal species (Ti is not contained in WN) not
included in the other one of the outer layer (WN) or inner layer, and the other one of the
outer layer (WN) or inner layer having a second metal species (W is not contained in
TiN) not included in the one of the outer layer or inner layer (TIN).
It would have been obvious to one of ordinary skill in the art at the time of
effective filling, absent unexpected results, to use the barrier metal layers as taught by
Himeno and the bilayer barrier layer as taught by Raaijmakers in the device of
Kornachuk in view of Smayling and Chang in order to have the predictable result of
using the barrier metal layers such that the device lifetime can be improved by
preventing diffusion of impurities into the interconnect lines as well as preventing
metallic atoms from diffusion into the surrounding ILD layers, and in order to have the
predictable result of using a bilayer barrier layer more capable of preventing ion
diffusion, respectively.
Re claims 12-19: It is readily apparent to one of ordinary skill in the art that
electrical computing devices such as smart phones are widely used devices which
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Page 17
require memory structures on a board to operate, these devices further include
communication chips, camera/imager chips, a battery, antennas, and processors
attached to the board.
Further, Kornachuk in view of Smayling and Chang teaches a computing device,
comprising: a board; and a component coupled to the board, the component including
an integrated circuit structure, a memory structure, a communication chip, a camera, a
battery, an antenna, a packaged integrated circuit die, a processor, communication
chip, and DSP, or a computer (paragraphs 45-47 and fig. 8 of Chang discusses memory
integrated with processors, i/o devices (keyboard/mouse), displays to create a
computing system).
Re claim 21: Kornachuk teaches the computing device, wherein a pitch (twice
the distance labeled P1 in fig. 10C) between the first interconnect line (A1) and the third
interconnect line (A3) is the same as a pitch (twice the distance labeled P1 in fig. 10C)
between the second interconnect line (B2) and the fourth interconnect line (C4).
Conclusion
8. Any inquiry concerning this communication or earlier communications from the
examiner should be directed to JESSE Y MIYOSHI whose telephone number is
(571)270-1629. The examiner can normally be reached on M-F, 8:30AM-5:00PM.
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Application/Control Number: 16/542,960
Art Unit: 2898
Page 18
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
Notice of References Cited
Application/Control No.
16/542,960
Examiner
JESSE Y MIYOSHI
Applicant(s)/Patent Under
Reexamination
YEOH et al.
Art Unit
2898
Page 1 of 1
U.S. PATENT DOCUMENTS
Document Number
Country Code-Number-Kind Code
Date
YYYY-MM-DD
Name
CPC Classification
US Classification
*
A
US-20090300575-A1
2009-12-03
Kornachuk; Stephen
G06F30/39
716/50
*
B
US-20080222587-A1
2008-09-11
Smayling; Michael C.
G06F30/392
716/125
*
C
US-20170194252-A1
2017-07-06
CHANG; Kuang-Hung
H10W20/427
1/1
*
D
US-20130112935-A1
2013-05-09
Himeno; Atsushi
H10B63/20
257/4
*
E
US-20040130029-A1
2004-07-08
Raaijmakers, Ivo
C23C16/45525
257/E21.171
F
G
H
J
K
L
M
FOREIGN PATENT DOCUMENTS
Document Number
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Name
CPC Classification
N
Ο
P
Q
R
S
T
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V
W
X
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U.S. Patent and Trademark Office
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