DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 12-14, 20, 25, 26, 33, 34, 44, and 45 are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Selvaraj et al (U.S. 2016/0300907).
Regarding claim 12. Selvaraj et al disclose an electronic circuit (FIG. 2, item 16; FIG. 2,3a/3c, item 20), comprising:
a substrate (FIG. 3a/3c, item 31s) having circuitry including a plurality of transistors ([0050], i.e. for integrated circuits including MOS transistors) connected by metal features ([0040], i.e. metal conductors 40) including vias and/or traces ([0040], i.e. metal conductors 40), the metal features including a first metal feature (FIG. 3a/3c, item 40c; FIG. 3c, item 40c) configured to be biases at a first DC voltage (FIG. 3c, item Vbias+), and a second metal feature (FIG. 3a, item 40t on right; FIG. 3c, item 40t) configured to be biased at a second DC voltage (FIG. 3c, item Vbias-) less than the first DC voltage (FIG. 3c, item Vbias+),
and a third metal (FIG. 3a/3c, item 28b; [0034], i.e. Conversely, lower plate 28b is implemented in a lower metal conductor level, such as the first or second metal level, as shown in FIG. 3a) positioned between the first metal feature (FIG. 3a/3c, item 40c; [0040], i.e. metal conductors 40) and the second metal feature (FIG. 3a/3c, item 40t on the right; [0040], i.e. metal conductors 40),
wherein the third metal (FIG. 3a/3c, item 28b) and the second metal feature (FIG. 3a/3c, item 40t on the right; [0040], i.e. metal conductors 40) are configured to receive ([0006], i.e. capacitor 7 is deployed directly at an external terminal (e.g., an input) of the integrated circuit; [0042], i.e. where voltage Vbias+ is greater than voltage Vbias−, will increase the capacitance values of junction capacitances CD1, CD2, CD3. This increase in those series capacitances CD1, CD2, CD3, in the circuit arrangement of FIG. 3c, will further reduce the effective parasitic capacitance at lower plate 28b) an alternating current (AC) signal (FIG. 2, item 15a; [0004], i.e. As well known in the art, some implementations of modern integrated circuits require the communication of signals between integrated circuits that are not referenced to the same ground voltage, either (or both) in the DC and AC sense; [0031], i.e. integrated circuit 14 serves as a transmitter of signals to integrated circuit 16, which is thus the receiver; [0031] pulse-width modulator 15a).
Regarding claim 13. Selvaraj et al discloses all the limitations of the electronic circuit (FIG. 2, item 16; FIG. 3a/3c, item 20) of claim 12 above.
Selveraj et al further discloses wherein the third metal feature (FIG. 3a/3c, item 28b) is a trace comprising an electrically conductive material (FIG. 3a/3c, item 28b; [0034]) or a via filled with the electrically conductive material.
Regarding claim 14. Selvaraj et al discloses all the limitations of the electronic circuit (FIG. 2, item 16; FIG. 3a/3c, item 20) of claim 12 above.
Selveraj et al further discloses wherein the electronic circuit (FIG. 2, item 16) comprises an integrated circuit (IC) (FIG. 2, item 16; [0034], i.e. integrated circuit 16), including a semiconductor substrate (FIG. 3a/3c, item 31s).
Regarding claim 20. Selvaraj et al discloses all the limitations of the electronic circuit (FIG. 2, item 16; FIG. 3a/3c, item 20) of claim 12 above.
Selvaraj et al further discloses wherein the first (FIG. 3a/3c, item 40c; [0040], i.e. metal conductors 40), second (FIG. 3a/3c, item 40t on the right; [0040], i.e. metal conductors 40), and third metal features (FIG. 3a/3c, item 28b; [0034], i.e. Conversely, lower plate 28b is implemented in a lower metal conductor level) each comprises a same metal ([0040], i.e. metal conductors; [0034], i.e. metal conductor)
Regarding claim 25. Selvaraj et al discloses an integrated circuit (FIG. 2, item 16; FIG. 3a/3c, item 20), comprising:
a first metal feature (FIG. 3a/3c, item 40c; FIG. 3c, item 40c; [0040], i.e. metal conductors 40) configured to operate at a first voltage ([0042], i.e. voltage Vbias+ to n-well region 32w and n-type buried layer 36 (via regions 32c, 34));
a second metal feature (FIG. 3a/3c, item 40t on right side; ; [0040], i.e. metal conductors 40) of a second circuit node (FIG. 3a, item 38w) configured to operate at a second voltage ([0042], i.e. voltage Vbias- to tank region 31t and substrate 31s, where voltage Vbias+ is greater than voltage Vbias-), the first voltage having a DC bias with respect to the second voltage ([0042], i.e. where voltage Vbias+ is greater than voltage Vbias-);
a third metal feature (FIG. 3a/3c, item 28b; [0034]) between the first (FIG. 3a/3c, item 40c) and second metal features (FIG. 3a/3c, item 40t on the right) and,
the third metal feature (FIG. 3a/3c, item 28b) and the second metal feature (FIG. 3a/3c, item 40t) are configured to receive ( [0006], i.e. capacitor 7 is deployed directly at an external terminal (e.g., an input) of the integrated circuit; [0042], i.e. where voltage Vbias+ is greater than voltage Vbias−, will increase the capacitance values of junction capacitances CD1, CD2, CD3. This increase in those series capacitances CD1, CD2, CD3, in the circuit arrangement of FIG. 3c, will further reduce the effective parasitic capacitance at lower plate 28b) an alternating current (AC) signal (FIG. 2, item 15a; [0004], i.e. As well known in the art, some implementations of modern integrated circuits require the communication of signals between integrated circuits that are not referenced to the same ground voltage, either (or both) in the DC and AC sense; [0031], i.e. integrated circuit 14 serves as a transmitter of signals to integrated circuit 16, which is thus the receiver; [0031] pulse-width modulator 15a)
Regarding claim 26. Selvaraj et al discloses all the limitations of the electronic circuit (FIG. 2, item 16; FIG. 3a/3c, item 20) of claim 25 above.
Selveraj et al further discloses wherein the first metal feature (FIG. 3a/3c item 40c) is a first interconnect trace (FIG. 3a/3c item 40c), the second metal feature (FIG. 3a/3c item 40t) is a second interconnect trace (FIG. 3a/3c item 40t), and the third metal feature (FIG. 3a/3c item 28a and 28b) includes a trace (FIG. 3a/3c item 28a and 28b) running parallel ([0033], i.e. several metal conductor levels are used within integrated circuit 16, several interlevel dielectric layers 30b through 30g vertically separate lower plate 28b from upper plate 28a) to the first (FIG. 3a/3c item 40c) or second (FIG. 3a/3c item 40t) interconnect trace.
Regarding claim 33. Selvaraj et al discloses all the limitations of the electronic circuit (FIG. 2, item 16; FIG. 3a/3c, item 20) of claim 25 above.
Selveraj et al further discloses wherein the third metal feature (FIG. 3a/3c, item 28a and 28b) is configured to receive an AC potential ([0004]) with a 10V peak-to-peak voltage ([0004] As well known in the art, some implementations of modern integrated circuits require the communication of signals between integrated circuits that are not referenced to the same ground voltage, either (or both) in the DC and AC sense; [0031] pulse-width modulator 15a).
The use of the language "wherein the metal guard is configured to receive an AC potential with a 10V peak-to-peak voltage" in a device claim shall be interpreted as intended use. As long as the element of the metal guard in the prior art is met, then the intended use is met. Claim requires further positive structure to overcome the intended use.
Regarding claim 34. Selvaraj et al discloses all the limitations of the electronic circuit (FIG. 2, item 16; FIG. 3a/3c, item 20) of claim 25 above.
Selveraj et al further discloses wherein the third metal feature (FIG. 3a/3c, item 28a and 28b) is configured to receive an AC potential ([0004]; [0031]) with a 100 Hz frequency ([0004]; [0031] pulse-width modulator 15a).
The use of the language " wherein the metal guard is configured to receive an AC potential with a 100 Hz frequency" in a device claim shall be interpreted as intended use. As long as the element of the metal guard in the prior art is met, then the intended use is met. Claim requires further positive structure to overcome the intended use.
Regarding claim 44. Selvaraj et al discloses all the limitations of the electronic circuit (FIG. 2, item 16; FIG. 3a/3c, item 20) of claim 12 above.
Selveraj et al further discloses wherein the third metal feature (FIG. 3a/3c, item 28a and 28b) is configured to receive an AC potential ([0004]) with a 10V peak-to-peak voltage ([0004] As well known in the art, some implementations of modern integrated circuits require the communication of signals between integrated circuits that are not referenced to the same ground voltage, either (or both) in the DC and AC sense; [0031] pulse-width modulator 15a).
The use of the language "wherein the metal guard is configured to receive an AC potential with a 10V peak-to-peak voltage" in a device claim shall be interpreted as intended use. As long as the element of the metal guard in the prior art is met, then the intended use is met. Claim requires further positive structure to overcome the intended use.
Regarding claim 45. Selvaraj et al discloses all the limitations of the electronic circuit (FIG. 2, item 16; FIG. 3a/3c, item 20) of claim 12 above.
Selveraj et al further discloses wherein the third metal feature (FIG. 3a/3c, item 28a and 28b) is configured to receive an AC potential ([0004]; [0031]) with a 100 Hz frequency ([0004]; [0031] pulse-width modulator 15a).
The use of the language " wherein the metal guard is configured to receive an AC potential with a 100 Hz frequency" in a device claim shall be interpreted as intended use. As long as the element of the metal guard in the prior art is met, then the intended use is met. Claim requires further positive structure to overcome the intended use.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 16 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Selvaraj et al (U.S. 2016/0300907) as applied to claims 12 and 25 above, and further in view of Hopper (U.S. 2002/0149111).
Regarding claim 16. Selvaraj et al discloses all the limitations of the electronic circuit (FIG. 2, item 16; FIG. 3a/3c, item 20) of claim 12 above.
Selvaraj et al further discloses wherein the metal features ([0040], i.e. metal conductors 40).
Selvaraj et al fails to explicitly disclose the metal features comprise copper or aluminum.
However, Hopper teaches the guard feature is a trace substantially comprising aluminum (claim 14, i.e. the interconnect metallization layer is substantially composed of aluminum)
Hopper further discloses (in claim 13) that the metallization layer is substantially composed of copper).
Since Selvaraj et al and Hopper teach copper interconnects, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the integrated circuit as disclosed in Selvaraj et al with the guard feature is a trace substantially comprising aluminum as disclosed by Hopper. The use of the interconnect metallization layer is substantially composed of aluminum in Hopper provides for exhibiting reduced variation in parasitic capacitance (Hopper, [Abstract]).
Regarding claim 32. Selvaraj et al discloses all the limitations of the electronic circuit (FIG. 2, item 16; FIG. 3a/3c, item 20) of claim 25 above.
Selvaraj et al further discloses wherein the first (FIG. 3a, item 40c), second (FIG. 3a, item 40t), and third (FIG. 3a, items 28b) metal features ([0040], i.e. metal conductors 40).
Selvaraj et al fails disclose wherein the metal features each comprises comprise copper.
However, Hopper teaches the metal feature is a trace substantially comprising aluminum (claim 13, i.e. wherein the interconnect metallization layer is substantially composed of copper)
Since Selvaraj et al and Hopper teach interconnects, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the integrated circuit as disclosed to modify Selvaraj et al with the teachings of the metal feature is a trace substantially comprising aluminum as disclosed by Hopper. The use of the interconnect metallization layer is substantially composed of copper in Hopper provides for exhibiting reduced variation in parasitic capacitance (Hopper, [Abstract]).
Claims 18, 19, 46, and 47 are rejected under 35 U.S.C. 103 as being unpatentable over Selvaraj et al (U.S. 2016/0300907) as applied to claims 12 and 25 above, and further in view of Lu et al (U.S. 2015/0138873).
Regarding claim 18. Selvaraj et al discloses all the limitations of the electronic circuit (FIG. 2, item 16; FIG. 3a/3c, item 20) of claim 12 above.
Selvaraj et al discloses the first (FIG. 3a, item 40c) and second metal (FIG. 3a, item 40t) feature.
Selvaraj et al fails to explicitly disclose wherein the first and second metal features are spaced apart by < 100 mm.
However, Lu et al teaches (FIG. 6a) wherein the first and second metal features are spaced apart by < 100 mm ([0080], i.e. the metallic nanowires can have a width of about 60 nm and pitch of about 150 nm).
Since Both Selvaraj et al and Lu et al teach metal conductors, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the electronic circuit as disclosed in Selvaraj et al with the wherein the first and second metal features are spaced apart by < 100 mm as disclosed by Lu et al. The use of the metallic nanowires can have a width of about 60 nm and pitch of about 150 nm in Lu et al provides for an array of metallic nanowires that include metals capable of supplying filament-forming ions (Lu et al, [0080]).
Regarding claim 19. Selvaraj et al discloses all the limitations of the electronic circuit (FIG. 2, item 16; FIG. 3a/3c, item 20) of claim 12 above.
Selvaraj et al discloses the first (FIG. 3a, item 40c) and second metal (FIG. 3a, item 40t) feature.
Selvaraj et al fails to explicitly disclose features are spaced apart by < 10 mm.
Selvaraj et al fails to explicitly disclose wherein the first and second metal features are spaced apart by < 10 mm.
However, Lu et al teaches (FIG. 6a) wherein the first and second metal features are spaced apart by < 10 mm ([0080], i.e. the metallic nanowires can have a width of about 60 nm and pitch of about 150 nm).
Since Both Selvaraj et al and Lu et al teach metal conductors, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the electronic circuit as disclosed in Selvaraj et al with the wherein the first and second metal features are spaced apart by < 10 mm as disclosed by Lu et al. The use of the metallic nanowires can have a width of about 60 nm and pitch of about 150 nm in Lu et al provides for an array of metallic nanowires that include metals capable of supplying filament-forming ions (Lu et al, [0080]).
Regarding claim 46. Selvaraj et al discloses all the limitations of the electronic circuit (FIG. 2, item 16; FIG. 3a/3c, item 20) of claim 25 above.
Selvaraj et al discloses the first (FIG. 3a, item 40c) and second metal (FIG. 3a, item 40t) feature.
Selvaraj et al fails to explicitly disclose wherein the first and second metal features are spaced apart by < 100 mm.
However, Lu et al teaches (FIG. 6a) wherein the first and second metal features are spaced apart by < 100 mm ([0080], i.e. the metallic nanowires can have a width of about 60 nm and pitch of about 150 nm).
Since Both Selvaraj et al and Lu et al teach metal conductors, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the electronic circuit as disclosed in Selvaraj et al with the wherein the first and second metal features are spaced apart by < 100 mm as disclosed by Lu et al. The use of the metallic nanowires can have a width of about 60 nm and pitch of about 150 nm in Lu et al provides for an array of metallic nanowires that include metals capable of supplying filament-forming ions (Lu et al, [0080]).
Regarding claim 47. Selvaraj et al discloses all the limitations of the electronic circuit (FIG. 2, item 16; FIG. 3a/3c, item 20) of claim 25 above.
Selvaraj et al discloses the first (FIG. 3a, item 40c) and second metal (FIG. 3a, item 40t) feature.
Selvaraj et al fails to explicitly disclose features are spaced apart by < 10 mm.
Selvaraj et al fails to explicitly disclose wherein the first and second metal features are spaced apart by < 10 mm.
However, Lu et al teaches (FIG. 6a) wherein the first and second metal features are spaced apart by < 10 mm ([0080], i.e. the metallic nanowires can have a width of about 60 nm and pitch of about 150 nm).
Since Both Selvaraj et al and Lu et al teach metal conductors, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the electronic circuit as disclosed in Selvaraj et al with the wherein the first and second metal features are spaced apart by < 10 mm as disclosed by Lu et al. The use of the metallic nanowires can have a width of about 60 nm and pitch of about 150 nm in Lu et al provides for an array of metallic nanowires that include metals capable of supplying filament-forming ions (Lu et al, [0080]).
Response to Arguments
Applicant's arguments filed June 26, 2026 have been fully considered but they are not persuasive.
Regarding 102 rejection.
On page 6 of applicant’s remarks, applicant appears to be arguing that Selvaraj et al fails to teach or suggest the third metal feature and the second metal feature are configured to receive and AC signal in claims 12 and 25.
Examiner respectfully disagrees and points out Selvaraj et al discloses the third metal (FIG. 3a/3c, item 28b) feature and the second metal feature (FIG. 3a/3c, item 40t) are configured to receive ([0006]) and AC signal from (FIG. 2, item 15a [0004], [0006], [0031]-[0035]).
On page 6 of applicant’s remarks, applicant appears to be further arguing that [0031] of Selvaraj does not disclose applicant’s claim 12.
Examiner respectfully disagrees and points out that Selvaraj et al teaches claim 12 as explained in the rejection above.
Regarding 103 rejection.
On page 8 of applicant’s remarks, applicant appears to be arguing claims 16, 18, 19, 32, 41, 42 and 43 are allowable for the same reasons as above.
Examiner respectfully disagrees for the same reason as above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Farkas et al (U.S. 2018/0284011) discloses Circuits, Systems, and Methods for Corrosion Detection.
Farque (U.S. 4,894,135) discloses Electrolyte IR Voltage Compensator for Cathodic Protection Systems or the like.
Freeman (U.S. 4,437,957) discloses Cathodic or Anodic Protection System and Method for Independently Protecting Different Regions of A Structure.
Freeman (U.S. 4,255,242) discloses Reference Electrode IP Drop Corrector for Cathodic and Anodic Protection Systems.
Wieloch et al (U.S. 5,670,944) discloses Power Substrate With Improved Thermal Characteristics.
Wieloch et al (U.S. 5,670,749) discloses Multilayer Circuit Board Having A Window Exposing An Enhanced Conductive Layer For Use As An Insulated Mounting Area.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT E BAUMAN whose telephone number is (469)295-9045. The examiner can normally be reached M-F, 9-5 CST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S.E.B./Examiner, Art Unit 2815
/JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
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