DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to Request for Continued Examination filed on February 17, 2026.
Claims 13-16, 18-20, 27, 29-38 and 40-49 are pending.
Claims 13-16, 18-20, 27, 29-38 and 40-47 have been amended.
Claims 17 and 39 have been canceled.
Claims 48-49 have been added.
Response to Amendment
Claim Objections
Claims 13-16, 18-20, 27, 29-38 and 40-49 are objected to because of the following informalities:
Claims 13, 18 and 29 state “in response to determining the two or more pointwise operations can be included in the single software kernel” in lines 5, 7 and 6 respectively. In the interest of consistency, it is recommended that this limitation be amended to “in response to identifying the two or more pointwise operations within the directed acyclic graph that can be included in the single software kernel”.
Claims 14-16, 19-20, 27, 30-38 and 40-49 depend on the objected to claims and do not resolve the deficiencies and thus, are objected to for at least the same reasons.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 48 and 49 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 48 and 49 state “storing the fallback kernel in the library for subsequent retrieval” and “store the fallback kernel in the library for subsequent retrieval upon the library could not find the other software kernel suitable for the multi-dependent operation” respectively. The Examiner has been unable to find the quoted subject matter in the drawings and/or specification filed on December 10, 2018. The specification and drawings make no mention of storing a “fallback kernel” in a “library” for subsequent retrieval . Therefore, the Examiner respectfully requests that the Applicant provide an explanation and/or citation to where possession of the claimed subject matter can be found at the time of filing.
Claims 13-16, 18-20, 27, 29-38 and 40-49 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 13, 18 and 29 recite the limitation "the operation" in lines 11, 13 and 12 respectively. It is unclear if “the operation” is referring to “a multi-dependent operation” or “two or more pointwise operations” or another “operation”.
Claims 14-16, 19-20, 27, 30-38 and 40-49 depend on the rejected claims 13, 18 and 29 as stated above and do not resolve the deficiencies and thus, are rejected for at least the same reasons.
Claim 20 states “a directed acyclic graph” in line 3. It is unclear if this “directed acyclic graph” is the same “directed acyclic graph” introduced in claim 18 or a different “directed acyclic graph”.
Claim 35 states “a multi-dependent operation” in line 4. It is unclear if this “multi-dependent operation” is referring to the same “multi-dependent operation introduced in claim 29 or a different “multi-dependent operation”.
Claims 36 and 37 depend on the rejected claim 35 as stated above and do not resolve the deficiencies and thus, are rejected for at least the same reasons.
Claim 46 states “the operations” in line 10. It is unclear if “the operations” is referring to the “two or more pointwise operations” or “operations” newly introduced in claim 46 in line 5.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 13-15, 18, 20, 29-31, 33-38, 42 and 47-49 are rejected under 35 U.S.C. 101 because the claimed invention recites a judicial exception, is directed to that judicial exception, an abstract idea, as it has not been integrated into practical application and the claims further do not recite significantly more than the judicial exception. Examiner has evaluated the claims under the framework provided in the 2019 Patent Eligibility Guidance published in the Federal Register 01/07/2019 and has provided such analysis below.
Step 1: Claims 13-15, 17 and 48 are directed to methods and fall within the statutory category of processes; Claim 18 is directed to a system and fall within the statutory category of machines; and Claims 29-31, 33-39, 42, 47 and 49 are directed to a processor and fall within the statutory category of articles of manufacture. Therefore, “Are the claims to a process, machine, manufacture or composition of matter?” Yes.
In order to evaluate the Step 2A inquiry “Is the claim directed to a law of nature, a natural phenomenon or an abstract idea?” we must determine, at Step 2A Prong 1, whether the claim recites a law of nature, a natural phenomenon or an abstract idea and further whether the claim recites additional elements that integrate the judicial exception into a practical application.
Step 2A Prong 1:
Claims 13, 18 and 29: The limitation “identify two or more pointwise operations within a directed acyclic graph that can be included in a single software kernel”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think and observe, judge and evaluate a directed acyclic graph and mentally identify, with or without the use of pen and paper, two or more pointwise operations within the directed acyclic graph that can be included in a single software kernel, at least in part, on whether inclusion of the two or more instructions in the software kernel are to cause two or more software kernels to be mutually dependent on one another.
Therefore, Yes, claims 13, 18 and 29 recite judicial exceptions.
The claims have been identified to recite judicial exceptions, Step 2A Prong 2 will evaluate whether the claims are directed to the judicial exception.
Step 2A Prong 2:
Claims 13, 18 and 29: The judicial exception is not integrated into a practical application. In particular, the claim recites the following additional elements – “computer-implemented”, “a memory storing one or more instructions; a processor that executes the one or more instructions…”, “performing a compiler to”, “one or more processors, comprising: circuitry…” and “in response to determining the two or more pointwise operations can be included in the single software kernel, compiling a software kernel for execution using the two or more pointwise operations” which are merely recitations of generic computing components and functions being used as a tool to apply the abstract idea (see MPEP § 2106.05(f)) which does not integrate a judicial exception into practical application. Further, claim 13, 18 and 29 recite the following additional elements – “in response to identifying a multi-dependent operation within the directed acyclic graph, causing the compiler to retrieve from a library another software kernel to execute the operation” which is merely a recitation of insignificant data gathering activity (see MPEP § 2106.05(g)) which does not integrate a judicial exception into practical application and will also be addressed below in Step 2B as also being Well-Understood, Routine and Conventional.
Therefore, “Do the claims recite additional elements that integrate the judicial exception into a practical application? No, these additional elements do not integrate the abstract idea into a practical application and they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
After having evaluating the inquires set forth in Steps 2A Prong 1 and 2, it has been concluded that claims 13, 18 and 29 not only recite a judicial exception but that the claim is directed to the judicial exception as the judicial exception has not been integrated into practical application.
Step 2B:
Claims 13, 18 and 29: The claims do not include additional elements, alone or in combination, that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements amount to no more than generic computing components and mere instructions to apply an exception which do not amount to significantly more than the abstract idea. Moreover, the recitation of insignificant data gathering activity as also Well-Understood, Routine and Conventional. See at least MPEP § 2106.05(d)(II) “The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. i. Receiving or transmitting data over a network, e.g., using the Internet to gather data”. That is, in the instant claims these limitations merely receive or transmit/provide data which is Well-Understood, Routine and Conventional.
Therefore, “Do the claims recite additional elements that amount to significantly more than the judicial exception? No, these additional elements, alone or in combination, do not amount to significantly more than the judicial exception.
Having concluded analysis within the provided framework, Claims 13, 18 and 29 do not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 14, it recites additional abstract idea recitations of “wherein, upon identification of the two or more pointwise operations, the two or more pointwise operations are partitioned into a first partition of a plurality of partitions, and wherein the first partition is to include a first node associated with a first operation to be performed by the two or more pointwise operations, where each output element from the first node corresponds to one input element to the first node, and a second node where each output element from the second node corresponds to one input element to the second node” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think about and observe, judge and evaluate two or more pointwise operations, just as in the independent claims above, mentally partition, with or without the use of pen and paper, the two or more pointwise operations into a first partition of a plurality of partitions, and wherein the first partition is to include a first node associated with a first operation to be performed by the two or more pointwise operations, where each output element from the first node corresponds to one input element to the first node, and a second node where each output element from the second node corresponds to one input element to the second node. Further, claim 14 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 14 also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, Claim 14 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 15, it recites additional abstract idea recitations of “wherein, upon identification of the two or more pointwise operations, the two or more pointwise operations are partitioned into a first partition of a plurality of partitions, and wherein the first partition is to include a first node associated with a first operation to be performed by the two or more pointwise operations, where each output element from the first node corresponds to multiple input elements to the first node, and a second node where each output element from the second node corresponds to multiple input elements to the second node” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think about and observe, judge and evaluate two or more pointwise operations, just as in the independent claims above, mentally partition, with or without the use of pen and paper, the two or more pointwise operations into a first partition of a plurality of partitions, and wherein the first partition is to include a first node associated with a first operation to be performed by the two or more pointwise operations, where each output element from the first node corresponds to multiple input elements to the first node, and a second node where each output element from the second node corresponds to multiple input elements to the second node. Further, claim 15 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 15 also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, Claim 15 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 20, it recites additional abstract idea recitations of “wherein the two or more pointwise operations correspond to a sequence of connected graph nodes comprising a directed acyclic graph” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think about and observe, judge and evaluate two or more pointwise operations, just as in the independent claims above, mentally correspond, with or without the use of pen and paper, the two or more instructions to a sequence of connected graph nodes comprising a directed acyclic graph. Further, claim 20 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 20 also fails both Step 2A prong 2, thus the claims are directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, Claim 20 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 30, it recite additional abstract idea recitations of “generate a first partition included in a plurality of partitions, the first partition including at least two nodes that correspond to at least two pointwise operations of the two or more pointwise operations” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think about and observe, judge and evaluate nodes, just as in the independent claims above, mentally generate, with or without the use of pen and paper, a first partition included in a plurality of partitions, the first partition including at least two nodes that correspond to at least two pointwise operations of the two or more pointwise operations. Further, claim 30 recite additional abstract idea recitations of “determining that a first node of the at least two nodes corresponds to a first operation included in the at least two pointwise operations” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think about and observe, judge and evaluate nodes, just as in the independent claims above, mentally determine, with or without the use of pen and paper, that a first node of the at least two nodes corresponds to a first operation included in the at least two pointwise operations.
Further still, claim 30 recites additional abstract idea recitations of “adding the first node to the first partition” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think about and observe, judge and evaluate a first node, just as in the independent claims above, mentally add, with or without the use of pen and paper, the first node to the first partition. Further still, claim 30 recite additional abstract idea recitations of “determining that a second node of the at least two nodes is a predecessor of the first node” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think about and observe, judge and evaluate nodes, just as in the independent claims above, mentally determine, with or without the use of pen and paper, that a second node of the at least two nodes is a predecessor of the first node.
Further still, claim 30 recite additional abstract idea recitations of “determining that the second node corresponds to a second pointwise operation included in the at least two pointwise operations” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think about and observe, judge and evaluate nodes, just as in the independent claims above, mentally determine, with or without the use of pen and paper, that the second node corresponds to a second pointwise operation included in the at least two pointwise operations. Further still, claim 30 recites additional abstract idea recitations of “adding the second node to the first partition” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think about and observe, judge and evaluate a second node, just as in the independent claims above, mentally add, with or without the use of pen and paper, the second node to the first partition. Further still, claim 30 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 30 also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, Claim 30 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 31, it recites additional abstract idea recitations of “wherein the software kernel is to be assigned to the first partition to combine operations to be performed by the first and second pointwise operations” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think about and observe, judge and evaluate a first partition, just as in the independent claims above, mentally assign, with or without the use of pen and paper, a software kernel to the first partition to combine operations to be performed by a first and second pointwise operations. Further, claim 31 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 31 also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, Claim 31 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 33, it recites additional abstract idea recitations of “generate a first partition included in a plurality of partitions, the first partition to include a first node that corresponds to an additional instruction” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think about and observe, judge and evaluate a first node, just as in the independent claims above, mentally generate, with or without the use of pen and paper, a first partition included in a plurality of partitions, the first partition to include the first node that corresponds to an additional instruction. Further, claim 33 recites additional element of “wherein the one or more circuits are further to…” which is merely a recitation of generic computing components and functions being used as a tool to apply the abstract idea (see MPEP § 2106.05(f)) which does not integrate a judicial exception into practical application and does not amount to significantly more. Further still, claim 33 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 33 also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, Claim 33 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 34, it recites additional abstract idea recitations of “generate the first partition at least by: determining that a second software kernel of the two or more software kernels is to be assigned to the first partition, the second software kernel included in the library that includes an implementation of the additional instruction” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think about and observe, judge and evaluate software kernels, just as in the independent claims above, mentally determine, with or without the use of pen and paper, that a second software kernel of the two or more software kernels is to be assigned to the first partition, the second software kernel included in the library that includes an implementation of the additional instruction and generating the first partition. Further, claim 34 recite additional abstract idea recitations of “adding the first node to the first partition, wherein additional nodes are not added to the first partition” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think about and observe, judge and evaluate nodes, just as in the independent claims above, mentally add, with or without the use of pen and paper, a first node to a first partition, wherein additional nodes are not added to the first partition. Further still, claim 34 recites additional element of “wherein circuitry…” which is merely a recitation of generic computing components and functions being used as a tool to apply the abstract idea (see MPEP § 2106.05(f)) which does not integrate a judicial exception into practical application and does not amount to significantly more. Further still, claim 34 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 34 also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, Claim 34 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 35, it recites additional abstract idea recitations of “generate the first partition at least by adding the first node to the first partition, wherein additional nodes are not added to the first partition, and wherein the additional instruction is to perform a multi-dependent operation that cannot be combined with any operation to be performed by the two or more pointwise operations” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think about and observe, judge and evaluate nodes, just as in the independent claims above, mentally generate, with or without the use of pen and paper, the first partition at least by adding the first node to the first partition, wherein additional nodes are not added to the first partition, and wherein the additional instruction is to perform a multi-dependent operation that cannot be combined with any operation to be performed by the two or more pointwise operations. Further still, claim 35 recites additional element of “wherein circuitry…” which is merely a recitation of generic computing components and functions being used as a tool to apply the abstract idea (see MPEP § 2106.05(f)) which does not integrate a judicial exception into practical application and does not amount to significantly more. Further still, claim 35 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 35 also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, Claim 35 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 36, it recites additional abstract idea recitations of “determining that no software kernels are available to assign to the first partition, generate an additional software kernel to assign to the first partition to perform the additional instruction in parallel” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think about and observe, judge and evaluate software kernels, just as in the independent claims above, mentally determine, with or without the use of pen and paper, that no software kernels are available to assign to the first partition and generate an additional software kernel to assign to the first partition to perform the additional instruction in parallel. Further still, claim 36 recites additional element of “wherein circuitry…” which is merely a recitation of generic computing components and functions being used as a tool to apply the abstract idea (see MPEP § 2106.05(f)) which does not integrate a judicial exception into practical application and does not amount to significantly more. Further still, claim 36 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 36 also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, Claim 36 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 37, it recites additional abstract idea recitations of “determine that the first node corresponds to the multi-dependent operation based, at least in part, on a graph representation of a serial computer program including the additional instruction and the two or more pointwise operations” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think about and observe, judge and evaluate a graph representation of a serial computer program, just as in the independent claims above, mentally determine, with or without the use of pen and paper, that the first node corresponds to the multi-dependent operation based, at least in part, on the graph representation of a serial computer program including the additional instruction and the two or more pointwise operations. Further still, claim 37 recites additional element of “wherein circuitry…” which is merely a recitation of generic computing components and functions being used as a tool to apply the abstract idea (see MPEP § 2106.05(f)) which does not integrate a judicial exception into practical application and does not amount to significantly more. Further still, claim 37 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 37 also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, Claim 37 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 38, it recites additional abstract idea recitations of “generate the plurality of partitions such that none of the partitions included in the plurality of partitions has cyclic dependencies on other partitions included in the plurality of partitions” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think about and observe, judge and evaluate cyclic dependencies, just as in the independent claims above, mentally generate, with or without the use of pen and paper, a plurality of partitions such that none of the partitions included in the plurality of partitions has cyclic dependencies on other partitions included in the plurality of partitions. Further still, claim 38 recites additional element of “wherein circuitry…” which is merely a recitation of generic computing components and functions being used as a tool to apply the abstract idea (see MPEP § 2106.05(f)) which does not integrate a judicial exception into practical application and does not amount to significantly more. Further still, claim 38 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 38 also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, Claim 38 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 42, it recites additional abstract idea recitations of “wherein two or more operations to be performed by the two or more pointwise operations are to be combined in the software kernel” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think about and observe, judge and evaluate two or more operations, just as in the independent claims above, mentally combine, with or without the use of pen and paper, the two or more operations to be performed by the two or more instructions into a software kernel. Further, claim 42 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 42 also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, Claim 42 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 47, it recites additional element of “wherein the two or more pointwise operations are to perform two or more pointwise operations of a serial computer program” which is merely a recitation of field of use/technological environment (see MPEP § 2106.05(h)) which does not integrate a judicial exception into a practical application and does not amount to significantly more. Further, claim 47 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 47 also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, Claim 47 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 48, it recites additional abstract idea recitations of “wherein, upon the library not finding the other software kernel suitable for the multi-dependent operation, configuring a fallback kernel” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think about and observe, judge and evaluate finding another software kernel suitable for a multi-dependent operation, just as in the independent claims above, mentally configure, with or without the use of pen and paper, a fallback kernel when a library cannot find the other software kernel suitable for the multi-dependent operation. Further, claim 48 recites additional element of “storing the fallback kernel in the library for subsequent retrieval” which is merely an insignificant data storing activity (see MPEP § 2106.05(g)) which does not integrate a judicial exception into practical application and is also Well-Understood, Routine and Conventional. See at least MPEP § 2106.05(d)(II) “The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. iv. Storing and retrieving information in memory”. That is, in the instant claims these limitations merely store or retrieve data which is Well-Understood, Routine and Conventional. Further, claim 48 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 48 also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, Claim 48 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 49, it recites additional abstract idea recitations of “configuring a fallback kernel” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think about and observe, judge and evaluate an other software kernel, just as in the independent claims above, mentally configure, with or without the use of pen and paper, a fallback kernel. Further, claim 49 recites additional element of “storing the fallback kernel in the library for subsequent retrieval upon the library could not find the other software kernel suitable for the multi-dependent operation” which is merely an insignificant data storing activity (see MPEP § 2106.05(g)) which does not integrate a judicial exception into practical application and is also Well-Understood, Routine and Conventional. See at least MPEP § 2106.05(d)(II) “The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. iv. Storing and retrieving information in memory”. That is, in the instant claims these limitations merely store or retrieve data which is Well-Understood, Routine and Conventional. Further, claim 49 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 49 also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, Claim 49 does not recite patent eligible subject matter under 35 U.S.C. §101.
Therefore, Claims 13-15, 18, 20, 29-31, 33-38, 42 and 47-49 do not recite patent eligible subject matter under 35 U.S.C. §101.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13-16, 18-20, 27, 29-38 and 40-46 are rejected under 35 U.S.C. 103 as being unpatentable over Haicheng Wu et al. (“Kernel Weaver: Automatically Fusing Database Primitives for Efficient GPU Computation”, 2012) in view of Jeremy Appleyard et al. (“Optimizing Performance of Recurrent Neural Networks on GPUs”, Apr 2016).
With respect to Claim 13, Haicheng Wu et al. disclose:
performing a compiler (compiler framework, Kernel Weaver, that can automatically fuse relational algebra operators, Abstract, Paragraph 2, lines 10-12) to identify two or more [operations] within a directed acyclic graph that can be included in a single software kernel; (see Figures 9, 10(a) and 10(b); constructing a dependency graph (directed acyclic graph) and searching for the longest contiguous sequence of operators (two or more operations) that can be fused (single software kernel), 4.2. Choosing Operators to Fuse, Paragraph 2, lines 3-9)
in response to determining the two or more [operations] can be included in the single software kernel; ((ii) selecting candidates (two or more operations) to fuse, 4. Automating Fusion, Paragraph 1, lines 5-8)
compiling a software kernel for execution using the two or more [operations]; ((iii) performing fusion and generating code for the fused operators. (compiling a software kernel), 4. Automating Fusion, Paragraph 1, lines 5-8)
and in response to identifying a multi-dependent operation within the directed acyclic graph, (identifying a consumer kernel from data dependency graph that has to wait until the completion of all threads in the kernel (SORT operator/multi-dependent operation), kernel fusion is not feasible, 4.1. Criteria for Kernel Fusion, Paragraph 6) causing the compiler to retrieve from a library another software kernel to execute the operation. (retrieving the consumer kernel/SORT operator (another software kernel) to execute the sort operation while the other operators have been fused (single software kernel), 5.2. Real Queries, Paragraphs 1-4)
Haicheng Wu et al. do not disclose:
[operations] are pointwise operations
However, Jeremy Appleyard et al. disclose:
[operations] are pointwise operations (fuse all of the point-wise kernels (two or more pointwise operations) into one larger kernel, 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-6)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Jeremy Appleyard et al. into the teaching of Haicheng Wu et al. to include [operations] are pointwise operations in order to execute point-wise operations more efficiently. (Jeremy Appleyard et al., 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-2)
With respect to Claim 14, all the limitations of Claim 13 have been addressed above; and Haicheng Wu et al. further disclose:
wherein, upon identification of the two or more [operations], the two or more [operations] are partitioned into a first partition of a plurality of partitions, (see Figure 11; grouping the partition, compute and gather stages (instructions) together to generate a grouped partition stage, grouped compute stage (first partition) and grouped gather stage (plurality of partition), 4.3. Kernel Weaving and Fusion, Paragraph 1) and wherein the first partition is to include a first node associated with a first operation to be performed by the two or more [operations], (see Figure 11; fused compute group consists of compute1 (first node) and compute2 (two or more instructions)) where each output element from the first node corresponds to one input element to the first node, (see Figure 11; compute1 has one input element (data0) and one output element (data1)) and a second node where each output element from the second node corresponds to one input element to the second node. (see Figure 11; compute2 has one input element (data1) and one output element (data2))
Haicheng Wu et al. do not disclose:
[operations] are pointwise operations
However, Jeremy Appleyard et al. disclose:
[operations] are pointwise operations (fuse all of the point-wise kernels (two or more pointwise operations) into one larger kernel, 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-6)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Jeremy Appleyard et al. into the teaching of Haicheng Wu et al. to include [operations] are pointwise operations in order to execute point-wise operations more efficiently. (Jeremy Appleyard et al., 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-2)
With respect to Claim 15, all the limitations of Claim 13 have been addressed above; and Haicheng Wu et al. further disclose:
wherein, upon identification of the two or more [operations], the two or more [operations]are partitioned into a first partition of a plurality of partitions, (see Figure 11; grouping the partition, compute and gather stages (instructions) together to generate a grouped partition stage, grouped compute stage (first partition) and grouped gather stage (plurality of partition), 4.3. Kernel Weaving and Fusion, Paragraph 1) and wherein the first partition is to include a first node associated with a first operation to be performed by the two or more [operations], (see Figure 11; fused compute group consists of compute1 (first node) and compute2 (two or more instructions)) where each output element from the first node corresponds to multiple input elements to the first node, (the fused operator may have multiple inputs and outputs, 4.3. Kernel Weaving and Fusion, Paragraph 1, lines 19-21; see Figure 9; Join operator has multiple inputs (data3 and data4) and one output (data5)) and a second node where each output element from the second node corresponds to multiple input elements to the second node. (the fused operator may have multiple inputs and outputs, 4.3. Kernel Weaving and Fusion, Paragraph 1, lines 19-21; see Figure 9; Join operator has multiple inputs (data5 and data2) and one output (data6))
Haicheng Wu et al. do not disclose:
[operations] are pointwise operations
However, Jeremy Appleyard et al. disclose:
[operations] are pointwise operations (fuse all of the point-wise kernels (two or more pointwise operations) into one larger kernel, 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-6)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Jeremy Appleyard et al. into the teaching of Haicheng Wu et al. to include [operations] are pointwise operations in order to execute point-wise operations more efficiently. (Jeremy Appleyard et al., 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-2)
With respect to Claim 16, all the limitations of Claim 13 have been addressed above; and Haicheng Wu et al. further disclose:
wherein the software kernel is to be executed by a parallel processor to perform the two or more [operations], (Kernel Weaver operates on CUDA source implementations of RA operators stored in a primitive library to produce fused CUDA implementations from which nvcc is used to generate kernel code in NVIDIA’s parallel thread execution (PTX) instruction set. (parallel processor) The lightweight host runtime layer picks up the fused PTX kernels and drives the Ocelot dynamic compilation and runtime infrastructure which is responsible for the execution on the NVIDIA GPUs, 3. System Overview, Paragraph 1) and wherein the parallel processor is to perform a read operation and a write operation when executing the software kernel. (the fused kernel only needs to read and write memory once rather than twice, 4.3.1. Fusing Thread Dependent Only Operators, Paragraph 3)
Haicheng Wu et al. do not disclose:
[operations] are pointwise operations
However, Jeremy Appleyard et al. disclose:
[operations] are pointwise operations (fuse all of the point-wise kernels (two or more pointwise operations) into one larger kernel, 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-6)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Jeremy Appleyard et al. into the teaching of Haicheng Wu et al. to include [operations] are pointwise operations in order to execute point-wise operations more efficiently. (Jeremy Appleyard et al., 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-2)
With respect to Claim 18, Haicheng Wu et al. disclose:
a memory storing one or more instructions; (see Figure 2; NVIDIA’s GPU architecture and execution model which includes memory and a streaming multiprocessor, 2.1. Programmable GPU, Paragraph 1, lines 1-17)
and a processor that executes the one or more instructions to at least: (see Figure 2; NVIDIA’s GPU architecture and execution model which includes memory and a streaming multiprocessor, 2.1. Programmable GPU, Paragraph 1, lines 1-17)
performing a compiler (compiler framework, Kernel Weaver, that can automatically fuse relational algebra operators, Abstract, Paragraph 2, lines 10-12) to identify two or more [operations] within a directed acyclic graph that can be included in a single software kernel; (see Figures 9, 10(a) and 10(b); constructing a dependency graph (directed acyclic graph) and searching for the longest contiguous sequence of operators (two or more operations) that can be fused (single software kernel), 4.2. Choosing Operators to Fuse, Paragraph 2, lines 3-9)
in response to determining the two or more [operations] can be included in the single software kernel; ((ii) selecting candidates (two or more operations) to fuse, 4. Automating Fusion, Paragraph 1, lines 5-8)
compiling a software kernel for execution the two or more [operations]; ((iii) performing fusion and generating code for the fused operators. (compiling a software kernel), 4. Automating Fusion, Paragraph 1, lines 5-8)
and in response to identifying a multi-dependent operation within the directed acyclic graph, (identifying a consumer kernel from data dependency graph that has to wait until the completion of all threads in the kernel (SORT operator/multi-dependent operation), kernel fusion is not feasible, 4.1. Criteria for Kernel Fusion, Paragraph 6) cause the compiler to retrieve from a library another software kernel to execute the operation. (retrieving the consumer kernel/SORT operator (another software kernel) to execute the sort operation while the other operators have been fused (single software kernel), 5.2. Real Queries, Paragraphs 1-4)
Haicheng Wu et al. do not disclose:
[operations] are pointwise operations
However, Jeremy Appleyard et al. disclose:
[operations] are pointwise operations (fuse all of the point-wise kernels (two or more pointwise operations) into one larger kernel, 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-6)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Jeremy Appleyard et al. into the teaching of Haicheng Wu et al. to include [operations] are pointwise operations in order to execute point-wise operations more efficiently. (Jeremy Appleyard et al., 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-2)
With respect to Claim 19, all the limitations of Claim 18 have been addressed above; and Haicheng Wu et al. further disclose:
further comprising a parallel processor that is to execute each software kernel of the two or more software kernels to perform the two or more [operations]. (Kernel Weaver operates on CUDA source implementations of RA operators stored in a primitive library to produce fused CUDA implementations (two or more second instructions) from which nvcc is used to generate kernel code in NVIDIA’s parallel thread execution (PTX) instruction set. (parallel processor) The lightweight host runtime layer picks up the fused PTX kernels (two or more software kernels) and drives the Ocelot dynamic compilation and runtime infrastructure which is responsible for the execution on the NVIDIA GPUs, 3. System Overview, Paragraph 1)
Haicheng Wu et al. do not disclose:
[operations] are pointwise operations
However, Jeremy Appleyard et al. disclose:
[operations] are pointwise operations (fuse all of the point-wise kernels (two or more pointwise operations) into one larger kernel, 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-6)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Jeremy Appleyard et al. into the teaching of Haicheng Wu et al. to include [operations] are pointwise operations in order to execute point-wise operations more efficiently. (Jeremy Appleyard et al., 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-2)
With respect to Claim 20, all the limitations of Claim 19 have been addressed above; and Haicheng Wu et al. further disclose:
wherein the two or more [operations] correspond to a sequence of connected graph nodes comprising a directed acyclic graph. (see Figure 10(b); constructing a dependency graph (directed acyclic graph) and searching for the longest contiguous sequence of operators (two or more instructions) that can be fused (sequence of connected graph nodes), 4.2. Choosing Operators to Fuse, Paragraph 2, lines 3-9)
Haicheng Wu et al. do not disclose:
[operations] are pointwise operations
However, Jeremy Appleyard et al. disclose:
[operations] are pointwise operations (fuse all of the point-wise kernels (two or more pointwise operations) into one larger kernel, 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-6)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Jeremy Appleyard et al. into the teaching of Haicheng Wu et al. to include [operations] are pointwise operations in order to execute point-wise operations more efficiently. (Jeremy Appleyard et al., 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-2)
With respect to Claim 27, all the limitations of Claim 13 have been addressed above; and Haicheng Wu et al. further disclose:
wherein, upon identification of the two or more [operations], the two or more [operations] are partitioned into a first partition of a plurality of partitions (see Figure 11; grouping the partition, compute and gather stages (instructions) together to generate a grouped partition stage, grouped compute stage (first partition) and grouped gather stage (plurality of partition), 4.3. Kernel Weaving and Fusion, Paragraph 1) to be performed in parallel, (finding feasible combinations of data parallel kernels to fuse, 4.1. Criteria for Kernel Fusion, Paragraph 1, lines 1-11) wherein the software kernel is assigned to the first partition, (the compute stage is fused into a single fused compute stage, 4.3. Kernel Weaving and Fusion, Paragraph 1, lines 5-13) and wherein, prior to causing the software kernel to perform the two or more [operations] in parallel, each other partition of the plurality of partitions is assigned other instructions to be performed in parallel. (fusing each of the partition and gather stages (other partitions) of the operators together to generate a single newly fused partition and gather stage which is done before code generation and execution, 4.3. Kernel Weaving and Fusion, Paragraph 1, line 5-13)
Haicheng Wu et al. do not disclose:
[operations] are pointwise operations
However, Jeremy Appleyard et al. disclose:
[operations] are pointwise operations (fuse all of the point-wise kernels (two or more pointwise operations) into one larger kernel, 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-6)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Jeremy Appleyard et al. into the teaching of Haicheng Wu et al. to include [operations] are pointwise operations in order to execute point-wise operations more efficiently. (Jeremy Appleyard et al., 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-2)
With respect to Claim 29, Haicheng Wu et al. disclose:
circuitry to: (see Figure 2; NVIDIA’s GPU architecture and execution model which includes memory and a streaming multiprocessor, 2.1. Programmable GPU, Paragraph 1, lines 1-17)
identify two or more [operations] within a directed acyclic graph that can be included in a single software kernel; (see Figures 9, 10(a) and 10(b); constructing a dependency graph (directed acyclic graph) and searching for the longest contiguous sequence of operators (two or more operations) that can be fused (single software kernel), 4.2. Choosing Operators to Fuse, Paragraph 2, lines 3-9)
in response to determining the two or more [operations] can be included in the single software kernel; ((ii) selecting candidates (two or more operations) to fuse, 4. Automating Fusion, Paragraph 1, lines 5-8)
compiling a software kernel for execution the two or more [operations]; ((iii) performing fusion and generating code for the fused operators. (compiling a software kernel), 4. Automating Fusion, Paragraph 1, lines 5-8)
and in response to identifying a multi-dependent operation within the directed acyclic graph, (identifying a consumer kernel from data dependency graph that has to wait until the completion of all threads in the kernel (SORT operator/multi-dependent operation), kernel fusion is not feasible, 4.1. Criteria for Kernel Fusion, Paragraph 6) cause the compiler to retrieve from a library another software kernel to execute the operation. (retrieving the consumer kernel/SORT operator (another software kernel) to execute the sort operation while the other operators have been fused (single software kernel), 5.2. Real Queries, Paragraphs 1-4)
Haicheng Wu et al. do not disclose:
[operations] are pointwise operations
However, Jeremy Appleyard et al. disclose:
[operations] are pointwise operations (fuse all of the point-wise kernels (two or more pointwise operations) into one larger kernel, 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-6)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Jeremy Appleyard et al. into the teaching of Haicheng Wu et al. to include [operations] are pointwise operations in order to execute point-wise operations more efficiently. (Jeremy Appleyard et al., 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-2)
With respect to Claim 30, all the limitations of Claim 29 have been addressed above; and Haicheng Wu et al. further disclose:
wherein the circuitry are further to generate a first partition included in a plurality of partitions, (grouping/fusing individual stages (partition, compute and gather stages) (plurality of partitions), 4.3. Kernel Weaving and Fusion, Paragraph 1; finding all groups of operators that can be fused (first partition/plurality of partitions), 4. Automating Fusion, Paragraph 1) the first partition including at least two nodes that correspond to at least two [operations] of the two or more [operations], (see Figure 11; two compute stages (two instructions) from two candidate operators (two nodes)are fused/grouped into one data parallel kernel (first partition), 4.3. Kernel Weaving and Fusion, Paragraph 1, lines 13-17; selecting candidate operators (nodes/instructions) to fuse (first partition), 4. Automating Fusion, Paragraph 1, lines 7-8) by:
determining that a first node of the at least two nodes corresponds to a first operation included in the at least two [operations]; (determining producer-consumer dependence between two data parallel kernels and fusing the corresponding producer and consumer threads (first node) from each kernel, 4.1. Criteria for Kernel Fusion, Paragraphs 3 and 4; each operator (node) has three stages, partition, compute and gather stages (at least two instructions), 4.3. Kernel Weaving and Fusion, Paragraph 1, lines 1-5)
adding the first node to the first partition; (adding operators (nodes/first node) that can be fused, within resource constraints into a fused operator (first partition, 4.2. Choosing Operators to Fuse, Paragraph 2, lines 6-7)
determining that a second node of the at least two nodes is a predecessor of the first node; (determining producer-consumer dependence between two data parallel kernels and fusing the corresponding producer (second node) and consumer threads (first node) from each kernel, 4.1. Criteria for Kernel Fusion, Paragraphs 3 and 4)
determining that the second node corresponds to a second [operation] included in the at least two [operations]; (determining producer-consumer dependence between two data parallel kernels and fusing the corresponding producer (second node) and consumer threads (first node) from each kernel, 4.1. Criteria for Kernel Fusion, Paragraphs 3 and 4)
and adding the second node to the first partition. (adding operators (nodes/second node) that can be fused, within resource constraints into a fused operator (first partition, 4.2. Choosing Operators to Fuse, Paragraph 2, lines 6-7)
Haicheng Wu et al. do not disclose:
[operation] and [operations] are pointwise operations
However, Jeremy Appleyard et al. disclose:
[operation] and [operations] are pointwise operations (fuse all of the point-wise kernels (two or more pointwise operations) into one larger kernel, 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-6)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Jeremy Appleyard et al. into the teaching of Haicheng Wu et al. to include [operation] and [operations] are pointwise operations in order to execute point-wise operations more efficiently. (Jeremy Appleyard et al., 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-2)
With respect to Claim 31, all the limitations of Claim 30 have been addressed above; and Haicheng Wu et al. further disclose:
wherein the software kernel is to be assigned to the first partition to combine operations to be performed by the first and second [operations]. (fusing the two compute stages (first and second instructions) of two operators (operations) into one data parallel kernel (software kernel/first partition), 4.3. Kernel Weaving and Fusion, Paragraph 1, lines 13-17)
Haicheng Wu et al. do not disclose:
[operations] are pointwise operations
However, Jeremy Appleyard et al. disclose:
[operations] are pointwise operations (fuse all of the point-wise kernels (two or more pointwise operations) into one larger kernel, 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-6)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Jeremy Appleyard et al. into the teaching of Haicheng Wu et al. to include [operations] are pointwise operations in order to execute point-wise operations more efficiently. (Jeremy Appleyard et al., 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-2)
With respect to Claim 32, all the limitations of Claim 31 have been addressed above; and Haicheng Wu et al. further disclose:
wherein the software kernel is to be executed by the processor to perform the first and second [operations], (Kernel Weaver operates on CUDA source implementations of RA operators stored in a primitive library to produce fused CUDA implementations from which nvcc is used to generate kernel code in NVIDIA’s parallel thread execution (PTX) instruction set. The lightweight host runtime layer picks
up the fused PTX kernels and drives the Ocelot dynamic compilation and runtime infrastructure which is responsible for the execution on the NVIDIA GPUs, 3. System Overview, Paragraph 1) and wherein the circuitry are further to perform a read operation and a write operation when executing the software kernel. (the fused kernel only needs to read and write memory once rather than twice, 4.3.1. Fusing Thread Dependent Only Operators, Paragraph 3)
Haicheng Wu et al. do not disclose:
[operations] are pointwise operations
However, Jeremy Appleyard et al. disclose:
[operations] are pointwise operations (fuse all of the point-wise kernels (two or more pointwise operations) into one larger kernel, 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-6)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Jeremy Appleyard et al. into the teaching of Haicheng Wu et al. to include [operations] are pointwise operations in order to execute point-wise operations more efficiently. (Jeremy Appleyard et al., 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-2)
With respect to Claim 33, all the limitations of Claim 29 have been addressed above; and Haicheng Wu et al. further disclose:
wherein the circuitry are further to generate a first partition included in a plurality of partitions, (grouping/fusing individual stages (partition, compute and gather stages) (plurality of partitions), 4.3. Kernel Weaving and Fusion, Paragraph 1; finding all groups of operators that can be fused (first partition/plurality of partitions), 4. Automating Fusion, Paragraph 1) the first partition to include a first node that corresponds to an additional instruction. (see Figures 9 and 10; searching and identifying the longest contiguous sequence of operators that can be fused/grouped together. For example, 2 SELECT operators and 1 JOIN operator while a second JOIN operator (first node/additional instruction) is not added and the algorithm repeats for the next not fused operator (first partition), 4.2. Choosing Operators to Fuse, Paragraph 2)
With respect to Claim 34, all the limitations of Claim 33 have been addressed above; and Haicheng Wu et al. further disclose:
wherein the circuitry are to generate the first partition at least by:
determining that a second software kernel of the two or more software kernels is to be assigned to the first partition, (generating a fused operator (second software kernel) that contains the second JOIN operator and any other operators that can be fused, 4.2. Choosing Operators to Fuse, Paragraph 2) the second software kernel included in the library that includes an implementation of the additional instruction; (see Figures 9 and 10; multiple fused operators (software kernels) wherein one software kernel includes the 2 SELECT operators and 1 JOIN operator and the second software kernel includes the second JOIN operator and any other operators that can be fused with it, 4.2. Choosing Operators to Fuse, Paragraph 2)
and adding the first node to the first partition, wherein additional nodes are not added to the first partition. (adding the second JOIN operator and any other operators that can be fused, 4.2. Choosing Operators to Fuse, Paragraph 2; see Figure 9; SORT operators (additional nodes) were not added/identified to the candidate operators to fuse and/or 2 SELECT operators and first JOIN operator were not added to the second JOIN operator)
With respect to Claim 35, all the limitations of Claim 33 have been addressed above; and Haicheng Wu et al. further disclose:
wherein the circuitry are to generate the first partition at least by adding the first node to the first partition, (see Figures 9 and 10; grouping/identifying another fusable operator (first partition) that includes the second JOIN operation (first node), 4.2. Choosing Operators to Fuse, Paragraph 2) wherein additional nodes are not added to the first partition, (see Figure 9; SORT operators were not added/identified to the candidate operators to fuse and/or 2 SELECT operators and first JOIN operator were not added to the second JOIN operator) and wherein the additional instruction is to perform a multi-dependent operation that cannot be combined with any operation to be performed by the two or more [operations]. (second JOIN operation (additional instruction) could not be added (a multi-dependent operation) to the previous fused operator (two or more operations), 4.2. Choosing Operators to Fuse, Paragraph 2; see Figure 9; SORT operator (multi-dependent operation) is not fusable, 4.1 Criteria for Kernel Fusion, Paragraph 6)
Haicheng Wu et al. do not disclose:
[operations] are pointwise operations
However, Jeremy Appleyard et al. disclose:
[operations] are pointwise operations (fuse all of the point-wise kernels (two or more pointwise operations) into one larger kernel, 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-6)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Jeremy Appleyard et al. into the teaching of Haicheng Wu et al. to include [operations] are pointwise operations in order to execute point-wise operations more efficiently. (Jeremy Appleyard et al., 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-2)
With respect to Claim 36, all the limitations of Claim 35 have been addressed above; and Haicheng Wu et al. further disclose:
wherein the circuitry are further to, in response to determining that no software kernels are available to assign to the first partition, generate an additional software kernel to assign to the first partition to perform the additional instruction in parallel. (the algorithm repeats the process of searching for the longest contiguous sequence of operators that have not been fused and generating a fused operator within resource constraints (generate an additional software kernel), 4.2. Choosing Operators to Fuse, Paragraph 2; Kernel Weaver operates on CUDA source implementations of RA operators stored in a primitive library to produce fused CUDA implementations from which nvcc is used to generate kernel code in NVIDIA’s parallel thread execution (PTX) instruction set. (parallel) The lightweight host runtime layer picks up the fused PTX kernels and drives the Ocelot dynamic compilation and runtime infrastructure which is responsible for the execution on the NVIDIA GPUs, 3. System Overview, Paragraph 1, lines 9-16)
With respect to Claim 37, all the limitations of Claim 35 have been addressed above; and Haicheng Wu et al. further disclose:
wherein the circuitry are further to determine that the first node corresponds to the multi-dependent operation based, at least in part, on a graph representation of a serial computer program including the additional instruction and the two or more [operations]. (constructing a dependence graph wherein nodes in the graph represent RA operators (additional instructions and the two or more instructions) and the directional edges identify nodes with producer-consumer dependencies and identifying a consumer kernel that has to wait until the completion of all threads in the kernel (multi-dependent operation), 4.1. Criteria for Kernel Fusion, Paragraphs 6-8; see Figure 9; sample database program (serial computer program))
Haicheng Wu et al. do not disclose:
[operations] are pointwise operations
However, Jeremy Appleyard et al. disclose:
[operations] are pointwise operations (fuse all of the point-wise kernels (two or more pointwise operations) into one larger kernel, 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-6)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Jeremy Appleyard et al. into the teaching of Haicheng Wu et al. to include [operations] are pointwise operations in order to execute point-wise operations more efficiently. (Jeremy Appleyard et al., 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-2)
With respect to Claim 38, all the limitations of Claim 33 have been addressed above; and Haicheng Wu et al. further disclose:
wherein the circuitry are further to generate the plurality of partitions such that none of the partitions included in the plurality of partitions are to have cyclic dependencies on other partitions included in the plurality of partitions. (see Figure9; the kernels in a dependence graph (no cyclic dependencies) that are candidates for kernel fusion only exhibit thread or CTA dependences with other kernels, and are bounded by operators with kernel dependences (no cyclic dependencies), 4.1. Criteria for Kernel Fusion, Paragraph 7, lines 8-11)
With respect to Claim 40, all the limitations of Claim 29 have been addressed above; and Haicheng Wu et al. further disclose:
wherein the circuitry are further to execute the software kernel according to a sequence that is associated with a plurality of partitions including a first partition that is to be associated with the software kernel. (The CUDA code is generated by concatenating the instantiated algorithm skeleton code of each stage, and connecting (sequence) the outputs of one stage (first partition) to the inputs of the next stage (plurality of partitions) and executing the CUDA code, 4.3. Kernel Weaving and Fusion, Paragraph 2, lines 1-7 and 3. System Overview, Paragraph 1)
With respect to Claim 41, all the limitations of Claim 29 have been addressed above; and Haicheng Wu et al. further disclose:
wherein the circuitry are further to execute the software kernel to perform at least one of the two or more [operations] in parallel. (Kernel Weaver operates on CUDA source implementations of RA operators stored in a primitive library to produce fused CUDA implementations from which nvcc is used to generate kernel code in NVIDIA’s parallel thread execution (PTX) instruction set. (parallel)The lightweight host runtime layer picks up the fused PTX kernels (two or more instructions/software kernel) and drives the Ocelot dynamic compilation and runtime infrastructure which is responsible for the execution on the NVIDIA GPUs, 3. System Overview, Paragraph 1, lines 9-16)
Haicheng Wu et al. do not disclose:
[operations] are pointwise operations
However, Jeremy Appleyard et al. disclose:
[operations] are pointwise operations (fuse all of the point-wise kernels (two or more pointwise operations) into one larger kernel, 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-6)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Jeremy Appleyard et al. into the teaching of Haicheng Wu et al. to include [operations] are pointwise operations in order to execute point-wise operations more efficiently. (Jeremy Appleyard et al., 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-2)
With respect to Claim 42, all the limitations of Claim 29 have been addressed above; and Haicheng Wu et al. further disclose:
wherein two or more operations to be performed by the two or more [operations] are to be combined in the software kernel. (fusing the two compute stages (two or more operations/instructions) into one data parallel kernel, 4.3. Kernel Weaving and Fusion, Paragraph 1, lines 13-17; fuse the code bodies of two GPU kernels (two or more instructions) in to kernel, Abstract, Paragraph 2, lines 1-6)
Haicheng Wu et al. do not disclose:
[operations] are pointwise operations
However, Jeremy Appleyard et al. disclose:
[operations] are pointwise operations (fuse all of the point-wise kernels (two or more pointwise operations) into one larger kernel, 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-6)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Jeremy Appleyard et al. into the teaching of Haicheng Wu et al. to include [operations] are pointwise operations in order to execute point-wise operations more efficiently. (Jeremy Appleyard et al., 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-2)
With respect to Claim 43, all the limitations of Claim 29 have been addressed above; and Haicheng Wu et al. further disclose:
wherein the one or more circuits are further to cause the software kernel to perform the two or more [operations] in parallel with one another on a parallel processing unit. (Kernel Weaver operates on CUDA source implementations of RA operators stored in a primitive library to produce fused CUDA implementations (software kernels) from which nvcc is used to generate kernel code in NVIDIA’s parallel thread execution (PTX) instruction set. (parallel processing unit) The lightweight host runtime layer picks up the fused PTX kernels and drives the Ocelot dynamic compilation and runtime infrastructure which is responsible for the execution on the NVIDIA GPUs, 3. System Overview, Paragraph 1, lines 9-16)
Haicheng Wu et al. do not disclose:
[operations] are pointwise operations
However, Jeremy Appleyard et al. disclose:
[operations] are pointwise operations (fuse all of the point-wise kernels (two or more pointwise operations) into one larger kernel, 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-6)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Jeremy Appleyard et al. into the teaching of Haicheng Wu et al. to include [operations] are pointwise operations in order to execute point-wise operations more efficiently. (Jeremy Appleyard et al., 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-2)
With respect to Claim 44, all the limitations of Claim 29 have been addressed above; and Haicheng Wu et al. further disclose:
wherein the two or more instructions are to be performed in parallel after partitioning a set of [operations], including the two or more instructions, among a plurality of partitions. (Kernel Weaver operates on CUDA source implementations of RA operators stored in a primitive library to produce fused CUDA implementations from which nvcc is used to generate kernel code in NVIDIA’s parallel thread execution (PTX) instruction set. The lightweight host runtime layer picks up the fused PTX kernels (partitioning a set of instructions/plurality of partitions) and drives the Ocelot dynamic compilation and runtime infrastructure which is responsible for the execution on the NVIDIA GPUs, 3. System Overview, Paragraph 1, lines 9-16)
Haicheng Wu et al. do not disclose:
[operations] are pointwise operations
However, Jeremy Appleyard et al. disclose:
[operations] are pointwise operations (fuse all of the point-wise kernels (two or more pointwise operations) into one larger kernel, 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-6)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Jeremy Appleyard et al. into the teaching of Haicheng Wu et al. to include [operations] are pointwise operations in order to execute point-wise operations more efficiently. (Jeremy Appleyard et al., 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-2)
With respect to Claim 45, all the limitations of Claim 44 have been addressed above; and Haicheng Wu et al. further disclose:
wherein the circuitry are further to process two or more partitions formed as a result of the partitioning to generate the two or more software kernels to perform the set of instructions in parallel, the two or more software kernels being respectively assigned the two or more partitions. (see Figure 10; producing a list of operators (set of instructions) and determining the longest contiguous sequence of operators that can be fused (first partition) and repeating the process for the next not fused operator until no more operators can be fused (second partition/plurality of partitions), 4.2. Choosing Operators to Fuse, Paragraph 2; Kernel Weaver operates on CUDA source implementations of RA operators stored in a primitive library to produce fused CUDA implementations (software kernels) from which nvcc is used to generate kernel code in NVIDIA’s parallel thread execution (PTX) instruction set. (perform the set of instructions in parallel) The lightweight host runtime layer picks up the fused PTX kernels and drives the Ocelot dynamic compilation and runtime infrastructure which is responsible for the execution on the NVIDIA GPUs, 3. System Overview, Paragraph 1, lines 9-16)
With respect to Claim 46, all the limitations of Claim 29 have been addressed above; and Haicheng Wu et al. further disclose:
wherein the circuitry are further to:
traverse each node of a graph representation of a serial computer program, (constructing a dependence graph (graph representation) wherein nodes in the graph represent RA operators and the directional edges identify nodes with producer-consumer dependencies and identifying candidate for fusion that satisfy the dependence requirement, 4.1. Criteria for Kernel Fusion, Paragraph 8; Figure 9; dependence graph of a database program (serial computer program)) including the two or more [operations], (see Figure 9; sample dependence graph constructed that contains SORT, SELECT and JOIN operators (two or more instructions)) to partition nodes of the graph representation associated with operations to be performed by the serial computer program among two or more partitions; (identifying operators (nodes) that satisfy the dependence requirement and are candidates for fusion (two or more partitions) using the dependence graph of the database program, 4.1. Criteria for Kernel Fusion, Paragraph 8; one partition includes the 2 SELECT operators and 1 JOIN operator while another partition includes the second JOIN operator and any operators that can be fused with it, 4.2. Choosing Operators to Fuse, Paragraph 2, lines 1-13)
and upon completing the traversal:
respectively assign the two or more software kernels to the two or more partitions; (given the dependence graph and candidate operators to fuse, performing the fusion by fusing the corresponding partition, compute and gather stages into a respective data parallel kernel (two or more software kernels), 4.3. Kernel Weaving and Fusion, Paragraph 1; a kernel (two or more software kernels) is generated (assigned) for each contiguous sequence of operators identified that can be fused (two or more partitions), 4.2. Choosing Operators to Fuse, Paragraph 2, lines 1-13)
and cause the two or more software kernels to perform the operations in parallel. (Kernel Weaver operates on CUDA source implementations of RA operators stored in a primitive library to produce fused CUDA implementations (software kernels) from which nvcc is used to generate kernel code in NVIDIA’s parallel thread execution (PTX) instruction set. (perform the set of instructions in parallel) The lightweight host runtime layer picks up the fused PTX kernels and drives the Ocelot dynamic compilation and runtime infrastructure which is responsible for the execution on the NVIDIA GPUs (two or more software kernels perform the operations in parallel), 3. System Overview, Paragraph 1, lines 9-16)
Haicheng Wu et al. do not disclose:
[operations] are pointwise operations
However, Jeremy Appleyard et al. disclose:
[operations] are pointwise operations (fuse all of the point-wise kernels (two or more pointwise operations) into one larger kernel, 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-6)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Jeremy Appleyard et al. into the teaching of Haicheng Wu et al. to include [operations] are pointwise operations in order to execute point-wise operations more efficiently. (Jeremy Appleyard et al., 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-2)
With respect to Claim 47, all the limitations of Claim 29 have been addressed above; and Haicheng Wu et al. further disclose:
wherein the two or more instructions are to perform two or more [operations] of a serial computer program. (see Figure 9; sample database program that includes two or more operations/instructions (serial computer program))
Haicheng Wu et al. do not disclose:
[operations] are pointwise operations
However, Jeremy Appleyard et al. disclose:
operations are pointwise operations (a widely used optimization is to combine matrix operations (pointwise operations) sharing the same input into a single larger matrix operation wherein the larger matrix operations are performed in parallel and implemented as a single kernel, 2.1 Naive implementation, Paragraph 2, lines 1-8 and 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 5-6; fuse all of the point-wise kernels (two or more pointwise operations) into one larger kernel, 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-6))
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Jeremy Appleyard et al. into the teaching of Haicheng Wu et al. to include operations are pointwise operations in order to execute point-wise operations more efficiently. (Jeremy Appleyard et al., 2.2.2 Fusion of point-wise operations, Paragraph 1, lines 1-2)
Allowable Subject Matter
Claims 48 and 49 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and the §101 and §112 rejections are overcome.
Response to Arguments
Applicant's arguments filed February 17, 2026 have been fully considered but they are not persuasive.
In the Remarks, Applicant argues:
Applicant respectfully disagrees and submits that the claims are recite eligible subject matter under 35 U.S.C. § 101. For example, amended claim 13 recites at least in part, "compiling a software kernel for execution using the two or more pointwise operations; and in response to identifying a multi-dependent operation within the directed acyclic graph, causing the compiler to retrieve from a library another software kernel to execute the operation" The elements recited in amended claim 13 do not recite "mental process," because such recitations cannot be performed in the human mind. Furthermore, compiling a kernel is not a generic machine or computer component that can reasonably be said to be replaceable with a human using pencil and paper.
Even so, assuming arguendo that claim 13 recites a judicial exception that Applicant does not concede, under Step 2A, Prong One, amended claim 13 integrates any such exception into a practical application under Step 2A, Prong Two, consistent with M.P.E.P. § 2106.04(d)(1), and in view of Ex Parte Desjardins, Appeal No. 2024-000567, Dec. on Req. for Rehearing (Sep. 26, 2025) (precedential) (hereinafter "Desjardins").
For example, amended claim 13 includes recitations that do not recite a mental process that integrate the judicial exception into a practical application. Specifically, current claim 13 recites, "performing a compiler to identify two or more pointwise operations within a directed acyclic graph that can be included in a single software kernel; in response to determining the two or more pointwise operations can be included in the single software kernel; compiling a software kernel for execution using the two or more pointwise operations; and in response to identifying a multi-dependent operation within the directed acyclic graph, causing the compiler to retrieve from a library another software kernel to execute the operation."
As discussed in the specification, these recitations address a specific technical problem in computer systems: repeated global memory transactions associated with kernel generation increase the load on memory bandwidth and create latencies. Rather than having a compiler that receive serial program code and generate corresponding serial kernels according to traditional compiler rules and not taking advantage of a parallel execution architecture. The amended claims comprises a compiler that identifies pointwise operations to be combined into software kernels that can executed in parallel with other software kernels. Accordingly, even if claim 13 were to recite a judicial exception, it is directed to an improvement in computer functionality and is not abstract under Step 2A, Prong Two. Similar reasoning applies to analysis under Step 2B. The recited features in amended claims are not well-understood, routine, or conventional and therefore constitute "significantly more."
Examiner’s Response:
The Examiner respectfully disagrees. As can be seen in the updated §101 rejection above, the Examiner has not analyzed “compiling a software kernel for execution using the two or more pointwise operations; and in response to identifying a multi-dependent operation within the directed acyclic graph, causing the compiler to retrieve from a library another software kernel to execute the operation" under Step 2A, Prong 1 for being a mental process. These limitations were analyzed under Step 2A, Prong 2 and Step 2B for being additional elements.
Specifically, the limitation of “in response to determining the two or more pointwise operations can be included in the single software kernel, compiling a software kernel for execution using the two or more pointwise operations” is merely a recitation of generic computing components and functions being used as a tool to apply the abstract idea (see MPEP § 2106.05(f)) which does not integrate a judicial exception into practical application under Step 2A, Prong 2 and does not amount to significantly more under Step 2B. Further, the limitation of “in response to identifying a multi-dependent operation within the directed acyclic graph, causing the compiler to retrieve from a library another software kernel to execute the operation” is merely a recitation of insignificant data gathering activity (see MPEP § 2106.05(g)) which does not integrate a judicial exception into practical application under Step 2A, Prong 2 and is also Well-Understood, Routine and Conventional. See at least MPEP § 2106.05(d)(II) “The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. i. Receiving or transmitting data over a network, e.g., using the Internet to gather data”. That is, in the instant claims these limitations merely receive or transmit/provide data which is Well-Understood, Routine and Conventional.
Since the above limitations have been identified as being additional elements under Step 2A, Prong 2 and Step 2B and are merely generic computing components and functions being used as a tool to apply the abstract idea and/or recitations of insignificant data gathering activity, they cannot be directed to an improvement to computer functionality. The current claim language of claim 13 “identifies” and “retrieves” but does not actually “execute” the pointwise operations that have been combined into software kernels in parallel with other software kernels.
Therefore, for at least the reasons set forth above, the rejection made under 35 U.S.C. §101 with respect to claim 13 is proper and thus, maintained.
In the Remarks, Applicant argues:
Independent claim 18 recites "a processor that executes the one or more instructions to at least: perform a compiler to identify two or more pointwise operations within a directed acyclic graph that can be included in a single software kernel" and claim 29 recites "circuitry to: identify two or more pointwise operations within a directed acyclic graph that can be included in a single software kernel", though not necessarily identical, they recite elements similar to those of claim 13, and are therefore directed to allowable subject matter at least for reasons including some of those discussed above in connection with claim 13. Claims 14-15, 30-31, 33-38, 42, and 47-19 are allowable at least for depending from an allowable independent claim.
Examiner’s Response:
Please see response to arguments above with respect to claim 13.
In the Remarks, Applicant argues:
Claims 13-20, 27, and 29-47 stand rejected under 35 U.S.C. § 112(a) as allegedly "failing to comply with the written description requirement." In response, without conceding the property of the rejection, Applicant has amended the claims which renders the rejection moot. Withdrawal of the rejection with respect to claims 13-20, 27, and 29-47 is respectfully requested.
Examiner’s Response:
Applicant’s arguments, see Page 11, filed February 17, 2026, with respect to §112(a) rejection of claims 13-20, 27 and 29-47 have been fully considered and are persuasive. The §112(a) rejection of claims 13-20, 27 and 29-47 has been withdrawn. However, in light of the amendments, a new ground of rejection under §112(a) and §112(b) rejection has been made.
In the Remarks, Applicant argues:
Applicant respectfully submits that the teachings of Wu are limited to describing techniques for integrating previously compiled kernels. Specifically, the teaching of Wu disclose a kernel fusion that fuse two kernels into a single kernel based on a condition that requires a first kernel that relies on the output produced by a second kernel to not be generated or executed until the second kernel has completed execution. For example, Wu describes that "[k]ernel fusion also requires compatibility between kernel parameters. The fused kernel will have the same kernel configuration as the candidates." Wu et al., at § 4.1, 2. Wu also teaches that "fusion can be performed correctly if the kernel configurations are the same." Id. Accordingly, Wu further describes that "the consumer kernel has to wait until the completion of all threads in the kernel...A typical example is were the producer kernel is a SORT operator... because it behaves like a global barrier." Wu et al., at § 4.1, 6.
Applicant respectfully submits that the teachings of Wu are silent with regard to the combination of instructions into a single software kernel. Accordingly, the teachings of Wu cannot be relied upon to teach generating a software kernel by "performing a compiler to identify two or more pointwise operations within a directed acyclic graph that can be included in a single software kernel," as claimed. The teachings of Wu are limited solely to describing techniques for integrating previously compiled kernels. As such, Wu fails to teach each and every element of claim 13. Thus, Wu fails to anticipate claim 13.
Examiner’s Response:
Applicant’s arguments with respect to claim 13 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Newly amended claim 13 relies on a combination of Wu and Jeremy Appleyard to disclose each and every element.
In the Remarks, Applicant argues:
Applicant respectfully submits that claims 18 and 29 are allowable at least for reasons discussed above in connection with claim 13. For example, claim 29 recites "identify two or more pointwise operations within a directed acyclic graph that can be included in a single software kernel." Amended claim 18 recites similar, though not identical, subject matter of claims 13 and 29. Therefore, at least for reasons including some of those discussed above, Applicant respectfully submits that Wu does not anticipate claims 18 and 29. Accordingly, Applicant respectfully submits that claims 18 and 29 are allowable under 35 U.S.C. § 102 over Wu.
Examiner’s Response:
Please see response to arguments above with respect to claim 13.
In the Remarks, Applicant argues:
Claim 47 depends from claims 29 described above. Accordingly, Applicant respectfully submits that claim 47 is allowable at least for depending from an allowable independent claim. In addition, Applicant respectfully submits that at least some of claim 47 additionally recite patentable subject matter not taught or otherwise rendered obvious by Wu and Appleyard, individually or in combination.
For at least reasons discussed above, Applicant respectfully submits that claim 47 is allowable under 35 U.S.C. § 103 over Wu and Appleyard. Withdrawal of the pending rejections of these claims is, therefore, respectfully requested.
Examiner’s Response:
Please see response to arguments above with respect to claim 29.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LANNY N UNG whose telephone number is (571)270-7708. The examiner can normally be reached Mon-Thurs 6am-4pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bradley Teets can be reached at 571-272-3338. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LANNY N UNG/Examiner, Art Unit 2197
Prosecution Insights