DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/15/2026 has been entered.
Response to Arguments
Applicant's arguments filed 8/28/2023 have been fully considered but they are moot in view of new grounds of rejection.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 2, 7-9, 21-29 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “an intermediate pad having opposite first and second ends and extending away from the first planar surface” at lines 6-7. The claim then states “the first end is at the first planar surface” at lines 7-8. It is unclear how the first end is “at the first planar surface” and is also “extending away from the first planar surface”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 9, 21-23, 28, and 29 is/are rejected under 35 U.S.C. 103, as best understood, as being unpatentable over Yoneda et al. (US PGPub 2002/0027265; hereinafter “Yoneda”) in view of Talledo (US PGPub 2015/0348879).
Re claim 1: Yoneda teaches (e.g. figs. 19, 20, 21, 32, 89A-E) a microelectronic device, comprising: an encapsulation material (112) having a first planar surface (bottom surface of 112 has a planar surface as well as a bottom planar surface on projection 21; hereinafter “1PS”); a die (111) at (111 at the level of PS) the first planar surface (1PS), the die (111) being at least partially surrounded by the encapsulation material (112); an intermediate pad (bonding balls 101 of fig 32 or 245 of fig. 89D, 89E; e.g. paragraph 276) having opposite first (upper side of 101; hereinafter “1E”) and second (lower side of 101; hereinafter “2E”) ends and extending away from the first planar surface (PS), in which the first end (1E) is at the first planar surface (1PS) and includes a wire bondable structure (101 is a wire bondable structure) at least partially surrounded by the encapsulation material (112), and the second end (2E) is away from the first planar surface (1PS) and includes a metal plate (113) having a different material from the wire bondable structure (101); a wire bond (118) coupled between the die (111) and the wire bondable structure (101).
Yoneda is silent as to explicitly teaching a package lead external to the encapsulation material and having a package lead surface coupled to the metal plate.
Talledo teaches (e.g. figs. 1, 2) a package leads (lead 16a-16h; e.g. paragraph 20) external to the encapsulation material (encapsulation material 17; e.g. paragraph 20 of Talledo; which is equivalent to 112 of Yoneda) and having a package lead surface (upper surface of 16a-16h) coupled to the metal plate (18a-18h,15a-15h).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the package lead disposition and attachment method as taught by Talledo in the device of Yoneda in order to have the predictable result of allowing the device of Yoneda to be used in an application which requires leads to extend from a package for electrical connection to a wiring substrate.
Re claim 2: Yoneda teaches the microelectronic device of claim 1, wherein thew wire bondable structure (101) includes a wire bond stud (stud bump; e.g. paragraph 384, 386).
Re claim 9: Yoneda in view of Talledo teaches the microelectronic device wherein the microelectronic device is free of electrically conductive leads (6 of Tsukahara) extending to lateral surfaces (since the lead 6 of Tsukahara is vertically offset from the packaging encapsulant 112 of Yoneda, 6 does not extend to 112) of the encapsulation material (112 of Yoneda), the lateral surfaces being perpendicular (it is known for side surfaces of encapsulant to be vertical depending on design choice since the external shape of the encapsulant has no performance benefits and is well known in the art, for example: Fig 19 of US2002/0105069 and fig. 19A of US 7,446,419 and fig. 9 of US2007/0178626) to the first planar surface (1PS of Yoneda).
Re claim 21: Yoneda in view of Tsukahara teaches the microelectronic device of claim 1, wherein the metal plate (213E as shown in fig. 86 of Yoneda) includes a diffusion barrier layer (213E-1 made of palladium; e.g. paragraph 379), and the microelectronic device includes a base metal layer (213E-3 made of Cu; e.g. paragraph 379 of Yoneda) between the diffusion barrier layer (213E-1) and the wire bondable structure (101 of Yoneda).
Re claim 22: Yoneda in view of Tsukahara teaches the microelectronic device of claim 21, wherein the diffusion barrier layer (213E-1) is a first diffusion barrier layer, and the microelectronic device further comprises at least one of an adhesive layer or a second diffusion barrier layer (213E-5 made of Pd; e.g. paragraph 379) between the wire bondable structure (101 of Yoneda) and the base metal layer (213E-3).
Re claim 23: Yoneda in view of Tsukahara teaches the microelectronic device of claim 22, wherein: the adhesive layer (213E-5) and the first (213E-1) and second diffusion barrier layers include at least one of: nickel, palladium (213E-1 and 213E-5 are both made of Pd), cobalt, titanium, or molybdenum; and the base metal (213E-3) layer includes copper (213E-3 is made of Cu).
Re claim 28: Yoneda in view of Tsukahara teaches the microelectronic device of claim 1, further comprising a layer of die attach material (115) between the die (111) and the planar surface (PS), the die attach material (115) including metal particles each coated with an insulation layer.
Re claim 29: Yoneda in view of Tsukahara teaches the microelectronic device of claim 1, wherein the surface of the package lead (bottom surface of 6 as shown in fig. 4 of Tsukahara) is a first surface, and the microelectronic device further comprises a component (PCB to which component is attached) coupled to a second surface (top surface of 6 as shown in fig. 4 of Tsukahara) of the package lead (6) opposite to the first surface (bottom surface of 6 as shown in fig. 4 of Tsukahara).
Claims 7 and 8 is/are rejected under 35 U.S.C. 103, as best understood, as being unpatentable over Yoneda in view of Talledo, as applied to claim 1 above, and further in view of Shiobara et al. (US 5,358,980; hereinafter “Shiobara”).
Re claim 7: Yoneda in view of Talledo teaches substantially the entire structure as recited in claim 1 except explicitly teaching the microelectronic device wherein the encapsulation material includes particles having a thermal expansion coefficient higher than a thermal expansion coefficient of the first die.
Shiobara teaches fill particles (inorganic fillers consist of fillers such as alumina and silicon nitride; e.g. column 15, line 25) distributed in the encapsulation material (14 of Yoneda), wherein the fill particles (alumina has a CTE of 6-7; silicon nitride has a CTE of 3.2) have a thermal expansion coefficient higher than a thermal expansion coefficient of the first die (silicon has CTE of 2.6 PPM/C°).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use a filler material in the encapsulant as taught by Shiobara in the device of Yoneda in view of Talledo in order to have the predictable result of using filler materials which reduced CTE of the encapsulant for reducing stresses to the semiconductor elements.
Re claim 8: Yoneda in view of Talledo and Shiobara teaches the microelectronic device wherein the encapsulation material includes particles (inorganic fillers consist of fillers such as alumina and silicon nitride; e.g. column 15, line 25 of Shiobara) having a thermal conductivity (alumina has a thermal conductivity of 30 W/mK; silicon nitride has a thermal conductivity of 100 W/mK) higher than a thermal conductivity of the encapsulation material (epoxy has poor thermal conductivities on the order to 0.15-0.25W/mK).
Claims 24-27 is/are rejected under 35 U.S.C. 103, as best understood, as being unpatentable over Yoneda in view of Talledo, as applied to claim 2 above, and further in view of Yabuki et al. (US PGPub 2007/0202683; hereinafter “Yabuki”).
Re claim 24: Yoneda in view of Talledo teaches substantially the entire structure as recited in claim 2 except explicitly teaching the microelectronic device wherein: the wire bond stud (101 of Yoneda) is a first wire bond stud; and the first end of the intermediate pad includes multiple wire bond studs including the first wire bond stud.
Yabuki teaches (e.g. fig. 2A, 3) the wire bond stud (101 of Yoneda) is a first wire bond stud (210, 225, 230; e.g. paragraph 31 of Yabuki); and the first end (top end) of the intermediate pad includes multiple wire bond studs including the first wire bond stud (210, 225, 230; e.g. paragraph 31 of Yabuki).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the stacked two tier buttressed structure as taught by Yabuki in the device of Yoneda in view of Talledo in order to have the predictable result of using a stud bump structure which allows for a taller stud bump structure having better strength in the lateral and vertical direction while increasing surface area provided by the stud bump structure (see paragraph 31 of Yabuki).
Re claim 25: Yoneda in view of Talledo teaches the microelectronic device of claim 24, wherein the multiple wire bond studs (210, 225, 230; e.g. paragraph 31 of Yabuki) being arranged in a rectangular array or a hexagonal array (studs are arranged in a hexagonal closed packed arrangement, as can be seen in fig. 7 of Yabuki).
Re claim 26: Yoneda in view of Talledo teaches the microelectronic device of claim 24, wherein the multiple wire bond studs have a uniform size (studs of the bottom most layer is uniformly formed).
Re claim 27: Yoneda in view of Talledo teaches the microelectronic device of claim 24, wherein the multiple wire bond studs include adjacent wire bond studs of different sizes (as can be seen in fig. 7 of Yabuki, stud bump sizes decrease as the buttressing structure increases in height).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached on M-F, 8:30AM-5:00PM.
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2822
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