Prosecution Insights
Last updated: April 19, 2026
Application No. 16/340,771

METHODS & APPARATUS FOR CONTROLLING AN INDUSTRIAL PROCESS

Non-Final OA §103
Filed
Apr 10, 2019
Examiner
LINDSAY, BERNARD G
Art Unit
2119
Tech Center
2100 — Computer Architecture & Software
Assignee
ASML Netherlands B.V.
OA Round
11 (Non-Final)
69%
Grant Probability
Favorable
11-12
OA Rounds
2y 10m
To Grant
99%
With Interview

Examiner Intelligence

Grants 69% — above average
69%
Career Allow Rate
310 granted / 451 resolved
+13.7% vs TC avg
Strong +47% interview lift
Without
With
+47.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
37 currently pending
Career history
488
Total Applications
across all art units

Statute-Specific Performance

§101
20.4%
-19.6% vs TC avg
§103
42.0%
+2.0% vs TC avg
§102
6.3%
-33.7% vs TC avg
§112
27.1%
-12.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 451 resolved cases

Office Action

§103
DETAILED ACTION Claims 1-7, 10, 14, 16-20, 22-25 and 27-29 are pending. Claims 8-9, 11-13, 15, 21 and 26 are cancelled. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Acknowledgement is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to European Patent Application No. 16195049.8, filed on 10/21/2016. Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/17/2025 has been entered. Response to Arguments Applicant’s arguments, filed 11/17/25, have been fully considered but are not persuasive. Applicant’s arguments regarding the rejection under 35 U.S.C. § 103 and the alleged deficiencies in the combination of Pasadyn, Maeritz and Behm (pages 8-15) are moot in view of the newly cited reference Ho and because Behm is no longer cited. For at least these reasons, the rejection of the claims is maintained. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-4, 10, 14, 16-18 and 22-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pasadyn et al. U.S. Patent No. 6708129 (hereinafter Pasadyn) in view of Maeritz U.S. Patent No. 7348187 (hereinafter Maeritz) and further in view of Ho et al. U.S. Patent Publication No. 20130080372 (hereinafter Ho). Regarding claim 1, Pasadyn teaches a method [col. 3 lines 11-27 — a method is provided for performing a process control using partial measurement data] comprising: selecting one or more product units from the plurality of product units as one or more sample product units and the product units comprising semiconductor substrates [col. 5 line 9 – col. 6 line 10, Figs. 3-7 — instead of analyzing each semiconductor wafer 105 processed by the processing tool 510, the wafer sample calculation unit 340 calculates a selected number of wafers that is less than the total number of wafers being processed for analysis by the integrated metrology tool 310. In one embodiment, the wafer sample calculation unit 340 calculates an optimum number of wafers, which does not interfere with the processing flow of semiconductor wafers 105 from one processing tool 510a to another tool 510b, yet provides a sufficient amount of metrology data for feedback and/or feed-forward purposes. The processing tool 510a routes a certain number of semiconductor wafers 105 dictated by the wafer sample calculation unit 340 to the integrated metrology tool 310, while the non-selected semiconductor wafers 105 are routed to another processing tool 510b]; performing one or more metrology steps, using a physical measurement or inspection apparatus, only on the selected one or more sample product units, wherein the selecting and performing is performed separately [col. 5 line 9 – col. 6 line 10, Figs. 3-7 — instead of analyzing each semiconductor wafer 105 processed by the processing tool 510, the wafer sample calculation unit 340 calculates a selected number of wafers that is less than the total number of wafers being processed for analysis by the integrated metrology tool 310. In one embodiment, the wafer sample calculation unit 340 calculates an optimum number of wafers, which does not interfere with the processing flow of semiconductor wafers 105 from one processing tool 510a to another tool 510b, yet provides a sufficient amount of metrology data for feedback and/or feed-forward purposes. The processing tool 510a routes a certain number of semiconductor wafers 105 dictated by the wafer sample calculation unit 340 to the integrated metrology tool 310, while the non-selected semiconductor wafers 105 are routed to another processing tool 510b]; and based at least partly on the metrology results of the selected one or more sample product units, physically controlling, by a hardware computer system, processing in a physical process performed in semiconductor manufacturing of the subsets of product units and/or other product units [col. 6 lines 39-61, Figs. 3-7 — the processing tool control unit 430 receives the wafer sample data and sends a certain number of sample wafers to the integrated metrology tool 310 while routing the other wafers 105 to the next processing tool, e.g., processing tool B 510b. Communications between processing tool A 510a and processing tool B 510b are coordinated by the system 300 such that the production wafers 105 are routed directly from the process chamber 420 on processing tool A 510a to processing tool B 510b, while a certain amount of wafers 105 are routed via the integrated metrology tool 310 to the processing tool B 510b as indicated in. FIG. 4. Similarly, processing tool B 510b also receives sample data from the wafer sample calculation unit 340 and performs the sampling described above. Furthermore, feed-forward and/or feedback data is calculated by the system 300 using the data acquired by the integrated metrology tool 310. The feed-forward and/or feedback data can be implemented into the processes performed by the processing tool B 510b; col. 6 line 62 – col. 7 line 17, Fig. 5 — semiconductor wafers 105 are processed on processing tools 510a, 510b]. But Pasadyn fails to clearly specify partitioning a set of product units from a plurality of product units into a plurality of subsets of product units, the partitioning into the plurality of subsets dictated at least partly by a statistical analysis of product unit data measured from at least some of the product units; refining the partitioned subsets based on context data representing a physical processing history of one or more product units of the plurality of product units; the selecting of the one or more sample product units based at least partly on statistical analysis of object data representing one or more parameters measured in relation to the plurality of product units, the object data being the same as, or different than, the product unit data, wherein the selecting and performing is performed separately for each refined subset. However, Maeritz teaches the selecting of the one or more sample product units based at least partly on statistical analysis of object data representing one or more parameters measured in relation to the plurality of product units, the object data being the same as, or different than, the product unit data [col. 7 line 38 col. 8 line 30 — Represented in FIG. 4 is a distribution of the values of a process parameter which were recorded in the manufacturing process of a wafer. Chosen as an example was a process parameter which shows the misalignment, i.e. the deviation in the X and/or Y direction… the misalignment values (process parameters) of all the wafers are entered in a diagram in the statistical analysis…In FIG. 4, the values for a lot comprising 50 wafers are entered. By means of the analysis, the wafers which best characterize the lot in this process parameter are then determined] wherein the selecting and performing is performed separately for each subset [col. 7 line 38 col. 8 line 6 — Represented in FIG. 4 is a distribution of the values of a process parameter which were recorded in the manufacturing process of a wafer. Chosen as an example was a process parameter which shows the misalignment, i.e. the deviation in the X and/or Y direction… the misalignment values (process parameters) of all the wafers are entered in a diagram in the statistical analysis…In FIG. 4, the values for a lot (subset) comprising 50 wafers are entered. By means of the analysis, the wafers which best characterize the lot in this process parameter are then determined]. Pasadyn and Maeritz are analogous art. They relate to process control for semiconductor manufacturing. Therefore before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the above process control system and method, as taught by Pasadyn, by incorporating the above limitations, as taught by Maeritz. One of ordinary skill in the art would have been motivated to do this modification in order to utilize product units/wafers that best characterize the group of product units/wafers, as taught by Maeritz [col. 8 lines 2-30]. But the combination of Pasadyn and Maeritz fails to clearly specify partitioning a set of product units from a plurality of product units into a plurality of subsets of product units, the partitioning into the plurality of subsets dictated at least partly by a statistical analysis of product unit data measured from at least some of the product units; refining the partitioned subsets based on context data representing a physical processing history of one or more product units of the plurality of product units. However, Ho teaches partitioning a set of product units from a plurality of product units into a plurality of subsets of product units, the partitioning into the plurality of subsets dictated at least partly by a statistical analysis of product unit data measured from at least some of the product units comprising semiconductor substrates; refining the partitioned subsets based on context data representing a physical processing history of one or more product units of the plurality of product units [0060-0065 — Analysis may, alternatively or additionally, be made more efficient/accurate by first performing automated clustering/classification of wafer (partitioning into the plurality of subsets of semiconductor substrates)… the processed wafers may be grouped according the processed patterns (e.g., over-etching along the top half, over-etching along the bottom half, etc.) or any tool-related parameter (e.g., chamber pressure) (context data) or any material-related parameter (e.g., a particular critical dimension range of values) (measurements from product units) or any combination thereof (measured product unit data and context data)…. . Generically speaking, clustering/classification aims to group subsets of the materials into "single cause" groups or "single dominant cause" groups to improve accuracy in, for example, root-cause analysis. For example, when a subset of the materials (e.g., wafers) are grouped into a group that reflects a similar process result or a set of similar process results, it is likely to be easier to pinpoint the root cause for the similar process result(s) for that subset than if the wafers are arbitrarily grouped into arbitrary subsets/groups without regard for process result similarities or not grouped at all… Classification refers to applying predefined criteria or predefined libraries to the current data set to sort the wafer set into predefined "buckets". Clustering refers to applying statistical analysis to look for common attributes and creating sub-sets of wafers based on these common attributes/parameter; 0055 — analysis may correlate a particular etch pattern on the wafer with a particular pressure setting on a particular tool (context data); 0039 —material-related data from tools 214-220 may be collected using an appropriate I/O module or I/O modules and may include, for example, wafer ID or material ID, wafer history data or material history data, which contains the date/time information, the process step ID, the tool ID, the processing recipe ID, and any material-related quality measurements such as any physical measurements, for example film thickness, film resistivity, critical dimension… data]. Pasadyn, Maeritz and Ho are analogous art. They relate to process control for semiconductor manufacturing. Therefore before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the above process control system and method, as taught by the combination of Pasadyn and Maeritz, by incorporating the above limitations, as taught by Ho. One of ordinary skill in the art would have been motivated to do this modification in order to enable more efficient/accurate analysis, as taught by Ho [0060-0065] and to account for tool-related effects in the process control system. Regarding claim 2, the combination of Pasadyn, Maeritz and Ho teaches all the limitations of the base claims as outlined above. Further, Pasadyn teaches selecting one or more sample product units [col. 5 line 9 – col. 6 line 10, Figs. 3-7 — instead of analyzing each semiconductor wafer 105 processed by the processing tool 510, the wafer sample calculation unit 340 calculates a selected number of wafers that is less than the total number of wafers being processed for analysis by the integrated metrology tool 310. In one embodiment, the wafer sample calculation unit 340 calculates an optimum number of wafers, which does not interfere with the processing flow of semiconductor wafers 105 from one processing tool 510a to another tool 510b, yet provides a sufficient amount of metrology data for feedback and/or feed-forward purposes. The processing tool 510a routes a certain number of semiconductor wafers 105 dictated by the wafer sample calculation unit 340 to the integrated metrology tool 310, while the non-selected semiconductor wafers 105 are routed to another processing tool 510b]. Further, Maeritz teaches selecting the one or more sample product units includes elimination of one or more product units that are identified by the statistical analysis as unrepresentative of the product units of the respective subset [col. 8 lines 2-45 — For the test measurement, a random sample, generally a single wafer, which lies in its alignment value close to the mean value of the distribution is selected. In FIG. 4, this is, for example, the wafer 411 — i.e. unrepresentative outliers, such as wafer 412 are not used/eliminated; col. 7 line 38 col. 8 line 6 — Represented in FIG. 4 is a distribution of the values of a process parameter which were recorded in the manufacturing process of a wafer. Chosen as an example was a process parameter which shows the misalignment, i.e. the deviation in the X and/or Y direction… the misalignment values (process parameters) of all the wafers are entered in a diagram in the statistical analysis…In FIG. 4, the values for a lot (subset) comprising 50 wafers are entered. By means of the analysis, the wafers which best characterize the lot in this process parameter are then determined]. Therefore before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the above process control system and method, as taught by the combination of Pasadyn, Maeritz and Ho, by incorporating the above limitations, as taught by Maeritz. One of ordinary skill in the art would have been motivated to do this modification in order to utilize product units/wafers that best characterize the group of product units/wafers and removing the influence of outliers, as suggested by Maeritz [col. 8 lines 2-30]. Further, Ho teaches respective subsets of product units [0060-0065 — Analysis may, alternatively or additionally, be made more efficient/accurate by first performing automated clustering/classification of wafer (partitioning into the plurality of subsets of semiconductor substrates)… the processed wafers may be grouped according the processed patterns (e.g., over-etching along the top half, over-etching along the bottom half, etc.) or any tool-related parameter (e.g., chamber pressure) (context data) or any material-related parameter (e.g., a particular critical dimension range of values) (measurements from product units) or any combination thereof (measured product unit data and context data)…. . Generically speaking, clustering/classification aims to group subsets of the materials into "single cause" groups or "single dominant cause" groups to improve accuracy in, for example, root-cause analysis. For example, when a subset of the materials (e.g., wafers) are grouped into a group that reflects a similar process result or a set of similar process results, it is likely to be easier to pinpoint the root cause for the similar process result(s) for that subset than if the wafers are arbitrarily grouped into arbitrary subsets/groups without regard for process result similarities or not grouped at all… Classification refers to applying predefined criteria or predefined libraries to the current data set to sort the wafer set into predefined "buckets". Clustering refers to applying statistical analysis to look for common attributes and creating sub-sets of wafers based on these common attributes/parameter; 0055 — analysis may correlate a particular etch pattern on the wafer with a particular pressure setting on a particular tool (context data); 0039 —material-related data from tools 214-220 may be collected using an appropriate I/O module or I/O modules and may include, for example, wafer ID or material ID, wafer history data or material history data, which contains the date/time information, the process step ID, the tool ID, the processing recipe ID, and any material-related quality measurements such as any physical measurements, for example film thickness, film resistivity, critical dimension… data]. Regarding claim 3, the combination of Pasadyn, Maeritz and Ho teaches all the limitations of the base claims as outlined above. Further, Pasadyn teaches selecting one or more sample product units [col. 5 line 9 – col. 6 line 10, Figs. 3-7 — instead of analyzing each semiconductor wafer 105 processed by the processing tool 510, the wafer sample calculation unit 340 calculates a selected number of wafers that is less than the total number of wafers being processed for analysis by the integrated metrology tool 310. In one embodiment, the wafer sample calculation unit 340 calculates an optimum number of wafers, which does not interfere with the processing flow of semiconductor wafers 105 from one processing tool 510a to another tool 510b, yet provides a sufficient amount of metrology data for feedback and/or feed-forward purposes. The processing tool 510a routes a certain number of semiconductor wafers 105 dictated by the wafer sample calculation unit 340 to the integrated metrology tool 310, while the non-selected semiconductor wafers 105 are routed to another processing tool 510b]. Further, Maeritz teaches selecting the one or more sample product units includes preferentially selecting one or more product units that are identified by the statistical analysis as most representative of the product units of the respective subset [col. 7 line 38 col. 8 line 30 — Represented in FIG. 4 is a distribution of the values of a process parameter which were recorded in the manufacturing process of a wafer. Chosen as an example was a process parameter which shows the misalignment, i.e. the deviation in the X and/or Y direction… the misalignment values (process parameters) of all the wafers are entered in a diagram in the statistical analysis…In FIG. 4, the values for a lot comprising 50 wafers are entered. By means of the analysis, the wafers which best characterize the lot (most representative) in this process parameter are then determined; col. 7 line 38 col. 8 line 6 — Represented in FIG. 4 is a distribution of the values of a process parameter which were recorded in the manufacturing process of a wafer. Chosen as an example was a process parameter which shows the misalignment, i.e. the deviation in the X and/or Y direction… the misalignment values (process parameters) of all the wafers are entered in a diagram in the statistical analysis…In FIG. 4, the values for a lot (subset) comprising 50 wafers are entered. By means of the analysis, the wafers which best characterize the lot in this process parameter are then determined]. Therefore before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the above process control system and method, as taught by the combination of Pasadyn, Maeritz and Ho, by incorporating the above limitations, as taught by Maeritz. One of ordinary skill in the art would have been motivated to do this modification in order to utilize product units/wafers that best characterize the group of product units/wafers, as taught by Maeritz [col. 8 lines 2-30]. Further, Ho teaches respective subsets of product units [0060-0065 — Analysis may, alternatively or additionally, be made more efficient/accurate by first performing automated clustering/classification of wafer (partitioning into the plurality of subsets of semiconductor substrates)… the processed wafers may be grouped according the processed patterns (e.g., over-etching along the top half, over-etching along the bottom half, etc.) or any tool-related parameter (e.g., chamber pressure) (context data) or any material-related parameter (e.g., a particular critical dimension range of values) (measurements from product units) or any combination thereof (measured product unit data and context data)…. . Generically speaking, clustering/classification aims to group subsets of the materials into "single cause" groups or "single dominant cause" groups to improve accuracy in, for example, root-cause analysis. For example, when a subset of the materials (e.g., wafers) are grouped into a group that reflects a similar process result or a set of similar process results, it is likely to be easier to pinpoint the root cause for the similar process result(s) for that subset than if the wafers are arbitrarily grouped into arbitrary subsets/groups without regard for process result similarities or not grouped at all… Classification refers to applying predefined criteria or predefined libraries to the current data set to sort the wafer set into predefined "buckets". Clustering refers to applying statistical analysis to look for common attributes and creating sub-sets of wafers based on these common attributes/parameter; 0055 — analysis may correlate a particular etch pattern on the wafer with a particular pressure setting on a particular tool (context data); 0039 —material-related data from tools 214-220 may be collected using an appropriate I/O module or I/O modules and may include, for example, wafer ID or material ID, wafer history data or material history data, which contains the date/time information, the process step ID, the tool ID, the processing recipe ID, and any material-related quality measurements such as any physical measurements, for example film thickness, film resistivity, critical dimension… data]. Regarding claim 4, the combination of Pasadyn, Maeritz and Ho teaches all the limitations of the base claims as outlined above. Further, Maeritz teaches the statistical analysis includes calculating a performance indicator value for a plurality of candidate product units, and identifying the one or more most representative product units by reference to the performance indicator [col. 7 line 38 col. 8 line 30 — Represented in FIG. 4 is a distribution of the values of a process parameter which were recorded in the manufacturing process of a wafer. Chosen as an example was a process parameter which shows the misalignment, i.e. the deviation in the X and/or Y direction… the misalignment values (process parameters/performance indicator) of all the wafers are entered in a diagram in the statistical analysis…In FIG. 4, the values for a lot comprising 50 wafers are entered. By means of the analysis, the wafers which best characterize the lot in this process parameter are then determined]. Therefore before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the above process control system and method, as taught by the combination of Pasadyn, Maeritz and Ho, by incorporating the above limitations, as taught by Maeritz187. One of ordinary skill in the art would have been motivated to do this modification in order to utilize product units/wafers that best characterize the group of product units/wafers, as taught by Maeritz [col. 8 lines 2-30]. Regarding claim 10, the combination of Pasadyn, Maeritz and Ho teaches all the limitations of the base claims as outlined above. Further, Pasadyn teaches one or more metrology steps performed on a selected sample product unit include sending the selected sample product unit ahead through the industrial process and measuring performance of the industrial process on the selected sample product unit, in order to define the corrections for processing of a remainder of the product units [0col. 5 line 9 – col. 6 line 10, Figs. 3-7 — instead of analyzing each semiconductor wafer 105 processed by the processing tool 510, the wafer sample calculation unit 340 calculates a selected number of wafers that is less than the total number of wafers being processed for analysis by the integrated metrology tool 310. In one embodiment, the wafer sample calculation unit 340 calculates an optimum number of wafers, which does not interfere with the processing flow of semiconductor wafers 105 from one processing tool 510a to another tool 510b, yet provides a sufficient amount of metrology data for feedback and/or feed-forward purposes. The processing tool 510a routes a certain number of semiconductor wafers 105 dictated by the wafer sample calculation unit 340 to the integrated metrology tool 310, while the non-selected semiconductor wafers 105 are routed to another processing tool 510b]. Further, Maeritz teaches subsets of product units [col. 8 lines 2-45 — For the test measurement, a random sample, generally a single wafer, which lies in its alignment value close to the mean value of the distribution is selected. In FIG. 4, this is, for example, the wafer 411 — i.e. unrepresentative outliers, such as wafer 412 are not used/eliminated; col. 7 line 38 col. 8 line 6 — Represented in FIG. 4 is a distribution of the values of a process parameter which were recorded in the manufacturing process of a wafer. Chosen as an example was a process parameter which shows the misalignment, i.e. the deviation in the X and/or Y direction… the misalignment values (process parameters) of all the wafers are entered in a diagram in the statistical analysis…In FIG. 4, the values for a lot (subset) comprising 50 wafers are entered. By means of the analysis, the wafers which best characterize the lot in this process parameter are then determined]. Further, Ho teaches subsets of product units [0060-0065 — Analysis may, alternatively or additionally, be made more efficient/accurate by first performing automated clustering/classification of wafer (partitioning into the plurality of subsets of semiconductor substrates)… the processed wafers may be grouped according the processed patterns (e.g., over-etching along the top half, over-etching along the bottom half, etc.) or any tool-related parameter (e.g., chamber pressure) (context data) or any material-related parameter (e.g., a particular critical dimension range of values) (measurements from product units) or any combination thereof (measured product unit data and context data)…. . Generically speaking, clustering/classification aims to group subsets of the materials into "single cause" groups or "single dominant cause" groups to improve accuracy in, for example, root-cause analysis. For example, when a subset of the materials (e.g., wafers) are grouped into a group that reflects a similar process result or a set of similar process results, it is likely to be easier to pinpoint the root cause for the similar process result(s) for that subset than if the wafers are arbitrarily grouped into arbitrary subsets/groups without regard for process result similarities or not grouped at all… Classification refers to applying predefined criteria or predefined libraries to the current data set to sort the wafer set into predefined "buckets". Clustering refers to applying statistical analysis to look for common attributes and creating sub-sets of wafers based on these common attributes/parameter; 0055 — analysis may correlate a particular etch pattern on the wafer with a particular pressure setting on a particular tool (context data); 0039 —material-related data from tools 214-220 may be collected using an appropriate I/O module or I/O modules and may include, for example, wafer ID or material ID, wafer history data or material history data, which contains the date/time information, the process step ID, the tool ID, the processing recipe ID, and any material-related quality measurements such as any physical measurements, for example film thickness, film resistivity, critical dimension… data.]. Regarding claim 14, Pasadyn teaches a non-transitory computer program product comprising machine readable instructions therein, the instructions, when executed by a data processing system [col. 7 lines 18-33, Fig. 5, claim 19 — computer system 530 is coupled to a computer storage unit 532 that may contain a plurality of software programs and data sets. The computer system 530 may contain one or more processors (not shown) that are capable of performing the operations described herein], configured to cause the data processing system apparatus to at least: select one or more product units from the plurality of product units as one or more sample product units, and the product units comprising semiconductor substrates [col. 5 line 9 – col. 6 line 10, Figs. 3-7 — instead of analyzing each semiconductor wafer 105 processed by the processing tool 510, the wafer sample calculation unit 340 calculates a selected number of wafers that is less than the total number of wafers being processed for analysis by the integrated metrology tool 310. In one embodiment, the wafer sample calculation unit 340 calculates an optimum number of wafers, which does not interfere with the processing flow of semiconductor wafers 105 from one processing tool 510a to another tool 510b, yet provides a sufficient amount of metrology data for feedback and/or feed-forward purposes. The processing tool 510a routes a certain number of semiconductor wafers 105 dictated by the wafer sample calculation unit 340 to the integrated metrology tool 310, while the non-selected semiconductor wafers 105 are routed to another processing tool 510b]; obtain metrology results from the performance of one or more metrology steps, using a physical measurement or inspection apparatus, only on the selected one or more sample product units, wherein the selection of one or more of the product units as one or more sample product units and obtaining of metrology results is done separately [col. 5 line 9 – col. 6 line 10, Figs. 3-7 — instead of analyzing each semiconductor wafer 105 processed by the processing tool 510, the wafer sample calculation unit 340 calculates a selected number of wafers that is less than the total number of wafers being processed for analysis by the integrated metrology tool 310. In one embodiment, the wafer sample calculation unit 340 calculates an optimum number of wafers, which does not interfere with the processing flow of semiconductor wafers 105 from one processing tool 510a to another tool 510b, yet provides a sufficient amount of metrology data for feedback and/or feed-forward purposes. The processing tool 510a routes a certain number of semiconductor wafers 105 dictated by the wafer sample calculation unit 340 to the integrated metrology tool 310, while the non-selected semiconductor wafers 105 are routed to another processing tool 510b]; and based at least partly on the metrology results of the selected one or more sample product units, cause physical control of a physical process performed in semiconductor manufacturing performed on the subsets of product units and/or other product units [col. 6 lines 39-61, Figs. 3-7 — the processing tool control unit 430 receives the wafer sample data and sends a certain number of sample wafers to the integrated metrology tool 310 while routing the other wafers 105 to the next processing tool, e.g., processing tool B 510b. Communications between processing tool A 510a and processing tool B 510b are coordinated by the system 300 such that the production wafers 105 are routed directly from the process chamber 420 on processing tool A 510a to processing tool B 510b, while a certain amount of wafers 105 are routed via the integrated metrology tool 310 to the processing tool B 510b as indicated in. FIG. 4. Similarly, processing tool B 510b also receives sample data from the wafer sample calculation unit 340 and performs the sampling described above. Furthermore, feed-forward and/or feedback data is calculated by the system 300 using the data acquired by the integrated metrology tool 310. The feed-forward and/or feedback data can be implemented into the processes performed by the processing tool B 510b; col. 6 line 62 – col. 7 line 17, Fig. 5 — semiconductor wafers 105 are processed on processing tools 510a, 510b]. But Pasadyn fails to clearly specify partition a set of product units from a plurality of product units into a plurality of subsets of product units, the partitioning into the plurality of subsets dictated at least partly by an outcome of a statistical analysis of product unit data measured from at least some of the product units; refine the partitioned subsets based on context data representing a physical processing history of one or more product units of the plurality of product units; the selection of the one or more sample product units based at least partly on statistical analysis of object data representing one or more parameters measured in relation to the plurality of product units, the object data being the same as, or different than, the product unit data wherein the selection of one or more of the product units as one or more sample product units and obtaining of metrology results is done separately for each subset. However, Maeritz teaches the selection of the one or more sample product units based at least partly on statistical analysis of object data representing one or more parameters measured in relation to the plurality of product units, the object data being the same as, or different than, the product unit data [col. 7 line 38 col. 8 line 30 — Represented in FIG. 4 is a distribution of the values of a process parameter which were recorded in the manufacturing process of a wafer. Chosen as an example was a process parameter which shows the misalignment, i.e. the deviation in the X and/or Y direction… the misalignment values (process parameters) of all the wafers are entered in a diagram in the statistical analysis…In FIG. 4, the values for a lot comprising 50 wafers are entered. By means of the analysis, the wafers which best characterize the lot in this process parameter are then determined] wherein the selection of one or more of the product units as one or more sample product units and obtaining of metrology results is done separately for each subset [col. 7 line 38 col. 8 line 6 — Represented in FIG. 4 is a distribution of the values of a process parameter which were recorded in the manufacturing process of a wafer. Chosen as an example was a process parameter which shows the misalignment, i.e. the deviation in the X and/or Y direction… the misalignment values (process parameters) of all the wafers are entered in a diagram in the statistical analysis…In FIG. 4, the values for a lot (subset) comprising 50 wafers are entered. By means of the analysis, the wafers which best characterize the lot in this process parameter are then determined]. Pasadyn and Maeritz are analogous art. They relate to process control for semiconductor manufacturing. Therefore before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the above non-transitory computer program product, as taught by Pasadyn, by incorporating the above limitations, as taught by Maeritz. One of ordinary skill in the art would have been motivated to do this modification in order to utilize product units/wafers that best characterize the group of product units/wafers, as taught by Maeritz [col. 8 lines 2-30]. But the combination of Pasadyn and Maeritz fails to clearly specify partition a set of product units from a plurality of product units into a plurality of subsets of product units, the partitioning into the plurality of subsets dictated at least partly by an outcome of a statistical analysis of product unit data measured from at least some of the product units; refine the partitioned subsets based on context data representing a physical processing history of one or more product units of the plurality of product units. However, Ho teaches partition a set of product units from a plurality of product units into a plurality of subsets of product units, the partitioning into the plurality of subsets dictated at least partly by an outcome of a statistical analysis of product unit data measured from at least some of the product units comprising semiconductor substrates; refine the partitioned subsets based on context data representing a physical processing history of one or more product units of the plurality of product units [0060-0065 — Analysis may, alternatively or additionally, be made more efficient/accurate by first performing automated clustering/classification of wafer (partitioning into the plurality of subsets of semiconductor substrates)… the processed wafers may be grouped according the processed patterns (e.g., over-etching along the top half, over-etching along the bottom half, etc.) or any tool-related parameter (e.g., chamber pressure) (context data) or any material-related parameter (e.g., a particular critical dimension range of values) (measurements from product units) or any combination thereof (measured product unit data and context data)…. . Generically speaking, clustering/classification aims to group subsets of the materials into "single cause" groups or "single dominant cause" groups to improve accuracy in, for example, root-cause analysis. For example, when a subset of the materials (e.g., wafers) are grouped into a group that reflects a similar process result or a set of similar process results, it is likely to be easier to pinpoint the root cause for the similar process result(s) for that subset than if the wafers are arbitrarily grouped into arbitrary subsets/groups without regard for process result similarities or not grouped at all… Classification refers to applying predefined criteria or predefined libraries to the current data set to sort the wafer set into predefined "buckets". Clustering refers to applying statistical analysis to look for common attributes and creating sub-sets of wafers based on these common attributes/parameter; 0055 — analysis may correlate a particular etch pattern on the wafer with a particular pressure setting on a particular tool (context data); 0039 —material-related data from tools 214-220 may be collected using an appropriate I/O module or I/O modules and may include, for example, wafer ID or material ID, wafer history data or material history data, which contains the date/time information, the process step ID, the tool ID, the processing recipe ID, and any material-related quality measurements such as any physical measurements, for example film thickness, film resistivity, critical dimension… data]. Pasadyn, Maeritz and Ho are analogous art. They relate to process control for semiconductor manufacturing. Therefore before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the above non-transitory computer program product, as taught by the combination of Pasadyn and Maeritz, by incorporating the above limitations, as taught by Ho. One of ordinary skill in the art would have been motivated to do this modification in order to enable more efficient/accurate analysis, as taught by Ho [0060-0065] and to account for tool-related effects in the process control system. Regarding claim 16, the combination of Pasadyn, Maeritz and Ho teaches all the limitations of the base claims as outlined above is otherwise rejected under the same rationale as a claim 2. Regarding claim 17, the combination of Pasadyn, Maeritz and Ho teaches all the limitations of the base claims as outlined above is otherwise rejected under the same rationale as a claim 3. Regarding claim 18, the combination of Pasadyn, Maeritz and Ho teaches all the limitations of the base claims as outlined above is otherwise rejected under the same rationale as a claim 4. Regarding claim 22, Pasadyn teaches a non-transitory computer program product comprising machine readable instructions therein, the instructions, when executed by a data processing system [col. 7 lines 18-33, Fig. 5, claim 19 — computer system 530 is coupled to a computer storage unit 532 that may contain a plurality of software programs and data sets. The computer system 530 may contain one or more processors (not shown) that are capable of performing the operations described herein], configured to cause the data processing system to at least: select one or more product units from the plurality of product units as one or more sample product units, and the product units comprising semiconductor substrates the selection of the one or more sample product units based at least partly on statistical analysis of object data representing one or more parameters measured in relation to the plurality of product units, the object data being the same as, or different than, the product unit data [col. 5 line 9 – col. 6 line 10, Figs. 3-7 — instead of analyzing each semiconductor wafer 105 processed by the processing tool 510, the wafer sample calculation unit 340 calculates a selected number of wafers that is less than the total number of wafers being processed for analysis by the integrated metrology tool 310. In one embodiment, the wafer sample calculation unit 340 calculates an optimum number of wafers, which does not interfere with the processing flow of semiconductor wafers 105 from one processing tool 510a to another tool 510b, yet provides a sufficient amount of metrology data for feedback and/or feed-forward purposes. The processing tool 510a routes a certain number of semiconductor wafers 105 dictated by the wafer sample calculation unit 340 to the integrated metrology tool 310, while the non-selected semiconductor wafers 105 are routed to another processing tool 510b]; obtain metrology results from the performance of one or more metrology steps, using a physical measurement or inspection apparatus, only on the selected one or more sample product units, wherein the selection of one or more of the product units as one or more sample product units and obtaining of metrology results is done separately [col. 5 line 9 – col. 6 line 10, Figs. 3-7 — instead of analyzing each semiconductor wafer 105 processed by the processing tool 510, the wafer sample calculation unit 340 calculates a selected number of wafers that is less than the total number of wafers being processed for analysis by the integrated metrology tool 310. In one embodiment, the wafer sample calculation unit 340 calculates an optimum number of wafers, which does not interfere with the processing flow of semiconductor wafers 105 from one processing tool 510a to another tool 510b, yet provides a sufficient amount of metrology data for feedback and/or feed-forward purposes. The processing tool 510a routes a certain number of semiconductor wafers 105 dictated by the wafer sample calculation unit 340 to the integrated metrology tool 310, while the non-selected semiconductor wafers 105 are routed to another processing tool 510b]; and based at least partly on the metrology results of the selected one or more sample product units, cause physical control of a physical process performed in semiconductor manufacturing performed on the subsets of product units and/or other product units [col. 6 lines 39-61, Figs. 3-7 — the processing tool control unit 430 receives the wafer sample data and sends a certain number of sample wafers to the integrated metrology tool 310 while routing the other wafers 105 to the next processing tool, e.g., processing tool B 510b. Communications between processing tool A 510a and processing tool B 510b are coordinated by the system 300 such that the production wafers 105 are routed directly from the process chamber 420 on processing tool A 510a to processing tool B 510b, while a certain amount of wafers 105 are routed via the integrated metrology tool 310 to the processing tool B 510b as indicated in. FIG. 4. Similarly, processing tool B 510b also receives sample data from the wafer sample calculation unit 340 and performs the sampling described above. Furthermore, feed-forward and/or feedback data is calculated by the system 300 using the data acquired by the integrated metrology tool 310. The feed-forward and/or feedback data can be implemented into the processes performed by the processing tool B 510b; col. 6 line 62 – col. 7 line 17, Fig. 5 — semiconductor wafers 105 are processed on processing tools 510a, 510b]. But Pasadyn fails to clearly specify partition a set of product units from a plurality of product units into a plurality of subsets of product units, the partitioning into the plurality of subsets dictated at least partly by a multi-variate, regression or mixture model analysis of product unit data, the product unit data measured from at least some of the product unit and the product units; refine the partitioned subsets based on context data representing a physical processing history of one or more product units of the plurality of product units; the selection of the one or more sample product units based at least partly on statistical analysis of object data representing one or more parameters measured in relation to the plurality of product units, the object data being the same as, or different than, the product unit data wherein the selection of one or more of the product units as one or more sample product units and obtaining of metrology results is done separately for each subset. However, Maeritz teaches the selection of the one or more sample product units based at least partly on statistical analysis of object data representing one or more parameters measured in relation to the plurality of product units, the object data being the same as, or different than, the product unit data [col. 7 line 38 col. 8 line 30 — Represented in FIG. 4 is a distribution of the values of a process parameter which were recorded in the manufacturing process of a wafer. Chosen as an example was a process parameter which shows the misalignment, i.e. the deviation in the X and/or Y direction… the misalignment values (process parameters) of all the wafers are entered in a diagram in the statistical analysis…In FIG. 4, the values for a lot comprising 50 wafers are entered. By means of the analysis, the wafers which best characterize the lot in this process parameter are then determined] wherein the selection of one or more of the product units as one or more sample product units and obtaining of metrology results is done separately for each subset [col. 7 line 38 col. 8 line 6 — Represented in FIG. 4 is a distribution of the values of a process parameter which were recorded in the manufacturing process of a wafer. Chosen as an example was a process parameter which shows the misalignment, i.e. the deviation in the X and/or Y direction… the misalignment values (process parameters) of all the wafers are entered in a diagram in the statistical analysis…In FIG. 4, the values for a lot (subset) comprising 50 wafers are entered. By means of the analysis, the wafers which best characterize the lot in this process parameter are then determined]. Pasadyn and Maeritz are analogous art. They relate to process control for semiconductor manufacturing. Therefore before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the above non-transitory computer program product, as taught by Pasadyn, by incorporating the above limitations, as taught by Maeritz. One of ordinary skill in the art would have been motivated to do this modification in order to utilize product units/wafers that best characterize the group of product units/wafers, as taught by Maeritz [col. 8 lines 2-30]. But the combination of Pasadyn and Maeritz fails to clearly specify partition a set of product units from a plurality of product units into a plurality of subsets of product units, the partitioning into the plurality of subsets dictated at least partly by a multi-variate, regression or mixture model analysis of product unit data, the product unit data measured from at least some of the product unit and the product units; refine the partitioned subsets based on context data representing a physical processing history of one or more product units of the plurality of product units. However, Ho teaches partition a set of product units from a plurality of product units into a plurality of subsets of product units, the partitioning into the plurality of subsets dictated at least partly by a multi-variate, regression or mixture model analysis of product unit data, the product unit data measured from at least some of the product unit and the product units comprising semiconductor substrates; refine the partitioned subsets based on context data representing a physical processing history of one or more product units of the plurality of product units [0060-0065 — Analysis may, alternatively or additionally, be made more efficient/accurate by first performing automated clustering/classification of wafer (partitioning into the plurality of subsets of semiconductor substrates)… the processed wafers may be grouped according the processed patterns (e.g., over-etching along the top half, over-etching along the bottom half, etc.) (multi-variate) or any tool-related parameter (e.g., chamber pressure) (context data) or any material-related parameter (e.g., a particular critical dimension range of values) (measurements from product units) or any combination thereof (measured product unit data and context data)…. . Generically speaking, clustering/classification aims to group subsets of the materials into "single cause" groups or "single dominant cause" groups to improve accuracy in, for example, root-cause analysis. For example, when a subset of the materials (e.g., wafers) are grouped into a group that reflects a similar process result or a set of similar process results, it is likely to be easier to pinpoint the root cause for the similar process result(s) for that subset than if the wafers are arbitrarily grouped into arbitrary subsets/groups without regard for process result similarities or not grouped at all… Classification refers to applying predefined criteria or predefined libraries to the current data set to sort the wafer set into predefined "buckets". Clustering refers to applying statistical analysis to look for common attributes and creating sub-sets of wafers based on these common attributes/parameter; 0055 — analysis may correlate a particular etch pattern on the wafer with a particular pressure setting on a particular tool (context data); 0039 —material-related data from tools 214-220 may be collected using an appropriate I/O module or I/O modules and may include, for example, wafer ID or material ID, wafer history data or material history data, which contains the date/time information, the process step ID, the tool ID, the processing recipe ID, and any material-related quality measurements such as any physical measurements, for example film thickness, film resistivity, critical dimension… data (multi-variate) — It would at least be obvious to use the available multiple measured variables to in order to properly cluster the wafers to account for these variables.]. Pasadyn, Maeritz and Ho are analogous art. They relate to process control for semiconductor manufacturing. Therefore before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the above non-transitory computer program product, as taught by the combination of Pasadyn and Maeritz, by incorporating the above limitations, as taught by Ho. One of ordinary skill in the art would have been motivated to do this modification in order to enable more efficient/accurate analysis, as taught by Ho [0060-0065] and to account for tool-related effects in the process control system. Regarding claim 23, the combination of Pasadyn, Maeritz and Ho teaches all the limitations of the base claims as outlined above is otherwise rejected under the same rationale as a claim 2. Regarding claim 24, the combination of Pasadyn, Maeritz and Ho teaches all the limitations of the base claims as outlined above is otherwise rejected under the same rationale as a claim 3. Regarding claim 25, the combination of Pasadyn, Maeritz and Ho teaches all the limitations of the base claims as outlined above is otherwise rejected under the same rationale as a claim 4. Claim(s) 5-7, 19-20 and 27-29 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Pasadyn, Maeritz and Ho in view of Burch et al. U.S. Patent Publication No. 20070288185 (hereinafter Burch). Regarding claim 5, the combination of Pasadyn, Maeritz and Ho teaches all the limitations of the base claims as outlined above. But the combination of Pasadyn, Maeritz and Ho fails to clearly specify the statistical analysis of the object data is based on positions of product units of the product units in a multi-dimensional space. However, Burch teaches the statistical analysis of the object data is based on positions of product units of the product units in a multi-dimensional space [0029-0031 — At step 1100, bin data (for example, failure bit map (FBM), die sort data, or multi-probe data), and the within-wafer spatial failure distribution of that bin data are mapped into an N-dimensional vector space; 0039 — An N-dimensional vector, where N is equal to the number of failure bin modes multiplied by the number of zones selected, is constructed and can represent all possible states of the wafer population. For a given wafer and zone, m-bins may fail and the number of failures would constitute the distance along that wafer/zone/bin(s) axes. In this way, an N-dimensional Euclidean "distance" matrix can be constructed for the entire population of wafers being analyzed such that each wafer is represented as a single point in this N-dimensional space… Principal Component Analysis is applied to identify the "natural" major cluster groups on which additional drilldown analysis can be performed]. Pasadyn, Maeritz, Ho and Burch are analogous art. They relate to process control for semiconductor manufacturing. Therefore before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the above process control system and method, as taught by the combination of Pasadyn, Maeritz and Ho, by incorporating the above limitations, as taught by Burch. One of ordinary skill in the art would have been motivated to do this modification in order to account for variations of more than one parameter (multiple dimensions), as suggested by Burch [0029-0031, 0039]. Regarding claim 6, the combination of Pasadyn, Maeritz, Ho and Burch teaches all the limitations of the base claims as outlined above. Further, Burch teaches the multi-dimensional space is defined at least partly by multivariate analysis of the object data [0029-0031 — At step 1100, bin data (for example, failure bit map (FBM), die sort data, or multi-probe data), and the within-wafer spatial failure distribution of that bin data are mapped into an N-dimensional vector space; 0039 — An N-dimensional vector, where N is equal to the number of failure bin modes multiplied by the number of zones selected, is constructed and can represent all possible states of the wafer population. For a given wafer and zone, m-bins may fail and the number of failures would constitute the distance along that wafer/zone/bin(s) axes. In this way, an N-dimensional Euclidean "distance" matrix can be constructed for the entire population of wafers being analyzed such that each wafer is represented as a single point in this N-dimensional space… Principal Component Analysis is applied to identify the "natural" major cluster groups on which additional drilldown analysis can be performed ]. Therefore before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the above process control system and method, as taught by the combination of Pasadyn, Maeritz, Ho and Burch, by incorporating the above limitations, as taught by Burch. One of ordinary skill in the art would have been motivated to do this modification in order to account for variations of more than one parameter (multiple dimensions), as suggested by Burch [0029-0031, 0039]. Regarding claim 7, the combination of Pasadyn, Maeritz, Ho and Burch teaches all the limitations of the base claims as outlined above. Further, Burch teaches the multi-dimensional space is defined at least partly by multivariate analysis of object data for product units processed previously [0025-0031 — The methods disclosed herein address the identification of the source of the systematic yield loss as derived from the e-test data, by providing a partitioning method to group wafers with similar systematic yield patterns (wafers previously processed)… At step 1100, bin data (for example, failure bit map (FBM), die sort data, or multi-probe data), and the within-wafer spatial failure distribution of that bin data are mapped into an N-dimensional vector space; 0039 — An N-dimensional vector, where N is equal to the number of failure bin modes multiplied by the number of zones selected, is constructed and can represent all possible states of the wafer population. For a given wafer and zone, m-bins may fail and the number of failures would constitute the distance along that wafer/zone/bin(s) axes. In this way, an N-dimensional Euclidean "distance" matrix can be constructed for the entire population of wafers being analyzed such that each wafer is represented as a single point in this N-dimensional space… Principal Component Analysis is applied to identify the "natural" major cluster groups on which additional drilldown analysis can be performed]. Therefore before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the above process control system and method, as taught by the combination of Pasadyn, Maeritz, Ho and Burch, by incorporating the above limitations, as taught by Burch. One of ordinary skill in the art would have been motivated to do this modification in order to account for variations of more than one parameter (multiple dimensions), as suggested by Burch [0029-0031, 0039]. Regarding claim 19, the combination of Pasadyn, Maeritz and Ho teaches all the limitations of the base claims as outlined above is otherwise rejected under the same rationale as a claim 5. Regarding claim 20, the combination of Pasadyn, Maeritz and Ho teaches all the limitations of the base claims as outlined above is otherwise rejected under the same rationale as a claim 6. Regarding claim 27, the combination of Pasadyn, Maeritz and Ho teaches all the limitations of the base claims as outlined above is otherwise rejected under the same rationale as a claim 5. Regarding claim 28, the combination of Pasadyn, Maeritz and Ho teaches all the limitations of the base claims as outlined above is otherwise rejected under the same rationale as a claim 6. Regarding claim 29, the combination of Pasadyn, Maeritz and Ho teaches all the limitations of the base claims as outlined above is otherwise rejected under the same rationale as a claim 7. Citation of Pertinent Prior Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Wang et al. U.S. Patent No. 7050879 that discloses a method and an apparatus for adjusting a sampling protocol in an adaptive control process. Note that any citations to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP 2123. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BERNARD G. LINDSAY whose telephone number is (571)270-0665. The examiner can normally be reached Monday through Friday from 8:30 AM to 5:30 PM EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mohammad Ali can be reached on (571)272-4105. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from Patent Center. Status information for published applications may be obtained from Patent Center. Status information for unpublished applications is available through Patent Center for authorized users only. Should you have questions about access to Patent Center, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant may call the examiner or use the USPTO Automated Interview Request (AIR) Form at https://www.uspto.gov/patents/uspto-automated- interview-request-air-form. /BERNARD G LINDSAY/ Primary Examiner, Art Unit 2119
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Prosecution Timeline

Apr 10, 2019
Application Filed
Apr 10, 2019
Response after Non-Final Action
Jan 16, 2021
Non-Final Rejection — §103
Jul 21, 2021
Response Filed
Sep 01, 2021
Final Rejection — §103
Jan 07, 2022
Request for Continued Examination
Jan 13, 2022
Response after Non-Final Action
Jan 26, 2022
Non-Final Rejection — §103
May 10, 2022
Response Filed
Jun 10, 2022
Final Rejection — §103
Oct 14, 2022
Request for Continued Examination
Oct 18, 2022
Response after Non-Final Action
Oct 27, 2022
Examiner Interview (Telephonic)
Nov 04, 2022
Non-Final Rejection — §103
Apr 14, 2023
Response Filed
May 25, 2023
Final Rejection — §103
Jul 31, 2023
Response after Non-Final Action
Aug 15, 2023
Request for Continued Examination
Aug 22, 2023
Response after Non-Final Action
Oct 03, 2023
Non-Final Rejection — §103
Feb 02, 2024
Response Filed
Mar 05, 2024
Final Rejection — §103
Jul 29, 2024
Response after Non-Final Action
Aug 08, 2024
Request for Continued Examination
Aug 14, 2024
Response after Non-Final Action
Oct 28, 2024
Non-Final Rejection — §103
Mar 26, 2025
Response Filed
Apr 22, 2025
Examiner Interview (Telephonic)
May 13, 2025
Final Rejection — §103
Nov 17, 2025
Request for Continued Examination
Nov 19, 2025
Response after Non-Final Action
Jan 27, 2026
Non-Final Rejection — §103 (current)

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