DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-14 and 16-20 are pending for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 4, 8, 10, 14, 16-17 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kanai et al. US Pub 2007/0220230 (hereafter Kanai) in view of Weimer US Pub 2016/0147559 (hereafter Weimer).
Reference Kanai was cited in the previous office action.
Reference Weimer was cited in the IDS filed on 11/6/2025.
As per claim 1, Kanai teaches the invention substantially as claimed including one or more processors, comprising: one or more circuits circuitry to: cause one or more threads of a first software kernel to store information in local storage used by the first software kernel (para[0135, 0145], FIG. 26, first thread of VPU0 (first software kernel) and the second thread of VPU1 each has its local storage, and stores data in their local storage);
one or more first threads to access information stored in the local storage by the one or more threads of the first software kernel without accessing global storage (para[0135], FIG. 26, thread A prepares and store data on local storage LS0, then the thread B reads the data from the local storage LS0, thus the first thread (thread B) accesses information stored in the local storage used by the thread (thread A) of the VPU0).
Kanai does not explicitly teach In response to an application binary interfaces (ABIs), cause one or more threads of a second software kernel to read information stored in the local storage; based at least in part, on an instruction indicating a memory address in the local storage used by the first software kernel generated by a compiler.
However, Weimer teaches in response to an application binary interfaces (ABIs), cause one or more threads of a second software kernel to read information stored in the local storage (para[0023, 0029, 0039], application (thread of a kernel) sends a system call (ABI function call) to restore a register value using the register save buffer, thus the register save buffer is read in response to the ABI call);
based at least in part, on an instruction indicating a memory address in the local storage used by the first software kernel generated by a compiler (para[0014, 0020, 0029], modification module cause a compiler to perform an operation to insert a function (ABI) call, indicating a memory location of the register save buffer).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Weimer’s teaching to Kanai’s invention in order to provide a system implementing an application binary interface ABI defining a system call interface allowing user space programs, such as application, to execute kernel level functions of the operating system, and additionally implement a 32bit ABI affording certain user space programs numerous benefits of the 64 bit processor architecture while using 32 bit pointers in order to avoid the overhead of 64 bit pointers and decreasing the memory footprint of a running user space program (para[0022-0023]).
As per claim 2, Kanai and Weimer teach the one or more processors processor of claim 1, Kanai teaches further comprising: one or more multiprocessors to store one or more results into the local storage in response to performing the one or more threads of the first software kernel, wherein the local storage includes registers and shared memory in the one or more multiprocessors (para[0131, 0135, 0145], FIG. 26, thread A prepares and store data on local storage LS0 (register), then the thread B reads the data from the local storage LS0, thus the first thread (thread B) accesses information stored in the local storage used by the thread (thread A) of the VPU0).
As per claim 3, Kanai and Weimer teach the one or more processors of claim 1, and Kanai further teaches comprising: one or more multiprocessors to store one or more results into the local storage in response to performing the one or more threads of the first software kernel (para[0135], FIG. 26, thread A prepares and store data on local storage LS0, then the thread B reads the data from the local storage LS0);
one or more logic circuits to cause the one or more results to be read from the local storage by the one or more threads of the second software kernel (para[0135], FIG. 26, thread A prepares and store data on local storage LS0, then the thread B reads the data from the local storage LS0, thus the first thread (thread B) accesses information stored in the local storage used by the thread (thread A) of the VPU0).
In addition, Weimer teaches the one or more results to be read from the local storage by the one or more threads of the second software kernel in response to a call from the one or more threads of the first software kernel via the ABI according to a convention published for the ABI (para[0023, 0029, 0039], application (thread of a kernel) sends a system call (ABI function call) to restore a register value using the register save buffer, thus the register save buffer is read in response to the ABI call, where the ABI include calling convention).
As per claim 4, Kanai teaches wherein the one or more threads of the first software kernel correspond to a first set of operators compiled separately from a second set of operators corresponding to the one or more threads of the second software kernel (para[0135, 0145], FIG. 26, first thread of VPU0 (first software kernel) and the second thread of VPU1, thus separate kernels compiled separately).
As per claim 8, it is a system claim of claim 1 above, thus it is rejected for the same rationale.
As per claim 10, it is a system claim of claim 4 above, thus it is rejected for the same rationale.
As per claim 14, it is a method claim of claim 1 above, thus it is rejected for the same rationale.
As per claim 16, it is a method claim of claim 3 above, thus it is rejected for the same rationale.
As per claim 17, it is a method claim of claim 4 above, thus it is rejected for the same rationale.
As per claim 19, Kanai teaches enabling one or more individual threads of the one or more threads of the first software kernel to exit the one or more threads of the first software kernel without impacting threads participating in the one or more threads of the second software kernel (para[0023-0024, 0032-0033], FIG. 2, the main thread’s context switched out and the micro threads execute).
Claim(s) 5-7, 9, 11-13, 18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kanai in view of Weimer as applied to claim 1, and further in view of Ben-kiki et al. US Pub 2014/0189713 (hereafter Ben-kiki).
Reference Ben-kiki was cited in the previous office action.
As per claim 5, Kanai and Weimer teach the one or more processors processor of claim 1, Kanai teaches further comprising: one or more multiprocessors to store one or more results into the local storage in response to performing the one or more thread of the first software kernel; one or more logic circuits to cause the one or more results to be read from the local storage (para[0135], FIG. 26, thread A prepares and store data on local storage LS0, then the thread B reads the data from the local storage LS0, thus the first thread (thread B) accesses information stored in the local storage used by the thread (thread A) of the VPU0);
wherein the one or more logic circuits are further to limit access to the results stored in the local storage to the one or more first threads and the one or more second threads (para[0129-0131], tightly coupled thread group running cooperation with each other and accesses each other’s resources).
Kanai and Weimer do not explicitly teach the one or more results to be read from the local storage in response to a call from the one or more threads of the first software kernel to one or more threads of the second software kernel using the ABI and without accessing the global storage.
However, Ben-kiki teaches the one or more results to be read from the local storage in response to a call from the one or more first threads to one or more second threads using the one or more ABIs and without accessing the global storage (para[0030, 0033, 0038-0039], a calling thread making a function call to micro-thread through an ABI, where a function call passes an input parameters to the sub-routine, according to the ABI standard conventions specified in ABI).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate to incorporate Ben-kiki’s teaching to Kanai and Weimer’s invention in order to provide a method for invocation of a multi-threaded accelerator which increases the effectiveness and efficiency of the CPU cores, using ABI that defines how a function call is made from first routine to a second subroutine and limits a subset of registers to be used rather than the entire context of the calling thread (para[0003, 0037-0039]).
As per claim 6, Kanai and Weimer teach the one or more processors processor of claim 1, Kanai teaches further comprising: one or more multiprocessors to store one or more results into the local storage in response to performing the one or more first threads; one or more logic circuits to cause the one or more results to be read from the local storage (para[0135], FIG. 26, thread A prepares and store data on local storage LS0, then the thread B reads the data from the local storage LS0, thus the first thread (thread B) accesses information stored in the local storage used by the thread (thread A) of the VPU0).
Kanai and Weimer do not explicitly teach the one or more results to be read from the local storage in response to a call from the one or more first threads to one or more second threads using the one or more ABIs and without accessing the global storage, wherein the one or more logic circuits are further to allow individual threads of the one or more first threads to exit the one or more first threads without impacting threads participating in the one or more second threads.
However, Ben-kiki teaches the one or more results to be read from the local storage in response to a call from the one or more first threads to one or more second threads using the one or more ABIs and without accessing the global storage (para[0030, 0033, 0038-0039], a calling thread making a function call to micro-thread through an ABI, where a function call passes an input parameters to the sub-routine, according to the ABI standard conventions specified in ABI);
wherein the one or more logic circuits are further to allow individual threads of the one or more first threads to exit the one or more first threads without impacting threads participating in the one or more second threads (para[0023-0024, 0032-0033], FIG. 2, the main thread’s context switched out and the micro threads execute).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate to incorporate Ben-kiki’s teaching to Kanai and Weimer’s invention in order to provide a method for invocation of a multi-threaded accelerator which increases the effectiveness and efficiency of the CPU cores, using ABI that defines how a function call is made from first routine to a second subroutine and limits a subset of registers to be used rather than the entire context of the calling thread (para[0003, 0037-0039]).
As per claim 7, Kanai and Weimer teach the one or more processors processor of claim 1, and Kanai teaches further comprising: one or more multiprocessors to store one or more results into the local storage in response to performing the one or more thread of the first software kernel; and
one or more logic circuits to cause the one or more results to be read from the local storage (para[0135], FIG. 26, thread A prepares and store data on local storage LS0, then the thread B reads the data from the local storage LS0, thus the first thread (thread B) accesses information stored in the local storage used by the thread (thread A) of the VPU0);
wherein the results correspond to a computation performed in parallel by all threads in at least one of the one or more threads of the first software kernel or the one or more threads of the second software kernel (para[0161], plurality of threads are executed in parallel to one another).
Kanai and Weimer do not explicitly teach the one or more results to be read from the local storage in response to a call from the one or more threads of the first software kernel to one or more threads of the second software kernel using the one or more ABIs and without accessing the global storage.
However, Ben-kiki teaches the one or more results to be read from the local storage in response to a call from the one or more threads of the first software kernel to one or more threads of the second software kernel using the one or more ABIs and without accessing the global storage (para[0030, 0033, 0038-0039], a calling thread making a function call to micro-thread through an ABI, where a function call passes an input parameters to the sub-routine, according to the ABI standard conventions specified in ABI).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate to incorporate Ben-kiki’s teaching to Kanai and Weimer’s invention in order to provide a method for invocation of a multi-threaded accelerator which increases the effectiveness and efficiency of the CPU cores, using ABI that defines how a function call is made from first routine to a second subroutine and limits a subset of registers to be used rather than the entire context of the calling thread (para[0003, 0037-0039]).
As per claim 9, Kanai and Weimer teach the system of claim 8, and Kanai teaches one or more multiprocessors coupled to one or more registers and shared memory, wherein the one or more multiprocessors are to cause one or more results to be read from the one or more registers or shared memory (para[0131, 0135, 0145], FIG. 26, thread A prepares and store data on local storage LS0 (register), then the thread B reads the data from the local storage LS0, thus the first thread (thread B) accesses information stored in the local storage used by the thread (thread A) of the VPU0).
Kanai and Weimer do not explicitly teach one or more results to be read in response to a call from the one or more threads of the first software kernel to the one or more threads of the second software kernel using the one or more ABIs; wherein the one or more multiprocessors are further to enable the one or more threads of the first software kernel to issue the call via the one or more ABIs to be received to the one or more threads of the second software kernel according to a convention published for the one or more ABIs (para[0030, 0033, 0038-0039], a calling thread making a function call to micro-thread through an ABI, where a function call passes an input parameters to the sub-routine, according to the ABI standard conventions specified in ABI).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate to incorporate Ben-kiki’s teaching to Kanai and Weimer’s invention in order to provide a method for invocation of a multi-threaded accelerator which increases the effectiveness and efficiency of the CPU cores, using ABI that defines how a function call is made from first routine to a second subroutine and limits a subset of registers to be used rather than the entire context of the calling thread (para[0003, 0037-0039]).
As per claim 11, it is a system claim of claim 5 above, thus it is rejected for the same rationale.
As per claim 12, it is a system claim of claim 6 above, thus it is rejected for the same rationale.
As per claim 13, it is a system claim of claim 7 above, thus it is rejected for the same rationale.
As per claim 18, it is a method claim of claim 5 above, thus it is rejected for the same rationale.
As per claim 20, it is a method claim of claim 7 above, thus it is rejected for the same rationale.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-14, 16-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hodson et al. US Pub 2008/0244599 teaches an application binary interface (ABI) shim is loaded with application binary images to direct kernel ABI calls to a local subordinate kernel or to the main OS kernel depending on which kernel manifestation is controlling requested resources.
Ray et al. US Pub 2018/0011711 teaches an apparatus to optimize shared local memory access by threads executing on a graphics processor, where the read requests are from a first thread of a first execution unit and a second thread of a second execution unit of a graphics processor.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAMMY EUNHYE LEE whose telephone number is (571)270-7773. The examiner can normally be reached Mon, Tues, Thur 9PM-4PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Meng-Ai An can be reached at (571)272-3756. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TAMMY E LEE/Primary Examiner, Art Unit 2195
Prosecution Insights