DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 7-10 and 12-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Majhi et al. (WO 2019055051; herein “Majhi”) in view of Endo et al. (US 2015/0041803; herein “Endo”).
Regarding claim 7, Majhi discloses in Fig. 1C and related text and related text integrated circuit structure, comprising:
an insulator structure (157, see pg. 5 line through 27-pg. 6 line 4) above a substrate (154), the insulator structure having a topography that varies along a plane parallel with a global plane of the substrate (plane ab, see Fig. 1C);
a semiconducting oxide material (156, see pg. 6 line 27-33) on the insulator structure, the semiconducting oxide material conformal with the topography of the insulator structure;
a gate electrode (158, see pg. 7 line 4-11) over a first portion of the semiconducting oxide material (e.g. portion of 156 under 172/164/158) on the insulator structure, the gate electrode having a first side opposite a second side, wherein both the first side and the second side are perpendicular to the global plane of the substrate;
a first conductive contact (a first 174, see pg. 7 line 4-11) adjacent the first side of the gate electrode, the first conductive contact in direct contact with a second portion of the semiconducting oxide material, the second portion of the semiconducting oxide material in direct contact with the first portion of the semiconducting oxide material;
a second conductive contact (a second 174) adjacent the second side of the gate electrode, the second conductive contact in direct contact with a third portion of the semiconducting oxide material on the insulator structure, the third portion of semiconducting oxide material in direct contact with the first portion of the semiconducting oxide material, wherein the first and second conductive contacts each comprise a metal species (e.g. aluminum, see pg. 13 lines 3-11); and
a gate dielectric layer (164, see pg. 5 line through 27-pg. 6 line 4) between the gate electrode and the first portion of the semiconducting oxide material on the insulator structure, the gate dielectric layer shaped as a U, the gate dielectric layer in an opening between the first conductive contact and the second conductive contact, the gate dielectric layer along and in direct contact with the first side and the second side of the gate electrode, and the gate electrode filling the gate dielectric layer (see Fig. 1C).
Majhi does not explicitly disclose
wherein the metal species originates from the first contact and the second contact and diffuses into the second and third portions of the semiconducting oxide material but is not in the first portion of the semiconducting oxide material.
In the same field endeavor, Endo teaches in Fig. 3B and related text an integrated circuit structure comprising
a first conductive contact (107a) adjacent the first side of the gate electrode, the first conductive contact in direct contact with a second portion of the semiconducting oxide material;
a second conductive contact (107b) adjacent the second side of the gate electrode, the second conductive contact in direct contact with a third portion of the semiconducting oxide material;
wherein the first and second conductive contacts each comprise a metal species (see [0087], [0179], and [0270]), wherein the metal species originates from the first contact and the second contact and diffuses into the second and third portions of the semiconducting oxide material but is not in the first portion of the semiconducting oxide material (e.g. in the source/drain regions but not in the channel region under the gate electrode).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Noda by having a pair of conductive contacts comprising a metal species in direct contact with the second and third portions, the metal species is in the second and third portions of the semiconducting oxide material but is not in the first portion of the semiconducting oxide material, as shown by Endo, in order to lower resistance of the source/drain regions of the transistor, increase on-state current, and improve performance (see Endo [0179]-[0181] at least).
Note that the limitation “wherein the metal species originates from the first contact and the second contact and diffuses into the second and third portions of the semiconducting oxide material” recites a process, however the claim is directed to a product. Therefore, this limitation is considered to be product by process limitations. "Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). See MPEP 2113. In the instant case, the metal species doped into the second and third portions of the semiconducting oxide material are the same as the metal species in the first contact and second contact. The presence of the metal species in the second and third portions of the semiconducting oxide material after doping as shown by the art would be the same as or obvious from the species being doped by diffusion from the first contact and the second contact.
Regarding claim 8, Majhi further discloses wherein the insulator structure (104) comprises one or more fins, each of the fins having a top and sidewalls, the semiconducting oxide material (106) on the top and the sidewalls of the each of the one or more fins.
Regarding claim 9, Majhi further discloses wherein the semiconducting oxide material (106) comprises indium gallium zinc oxide (see pg. 6 line 27-33).
Regarding claim 10, Majhi further discloses wherein the semiconducting oxide material (106) comprises a material selected from the group consisting of tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide and tungsten oxide (see pg. 6 line 27-33).
Regarding claim 12, Majhi further discloses wherein the gate dielectric layer (164) comprises a layer of a high-k dielectric material (see pg. 6 line 27-33) directly on the semiconducting oxide material (156).
Regarding claim 13, Majhi further discloses
a first dielectric spacer (first 172, see [0040]) between the first conductive contact and the first side of the gate electrode, the first dielectric spacer over a fourth portion of the semiconducting oxide material on the insulator structure, wherein the second portion of the semiconducting oxide material includes the fourth portion; and
a second dielectric spacer (second 172) between the second conductive contact and the second side of the gate electrode, the second dielectric spacer over a fifth portion of the semiconducting oxide material on the insulator structure, wherein the third portion of the semiconducting oxide material includes the fifth portion.
Regarding claim 14, Majhi further discloses wherein the gate dielectric layer (164) is between the first dielectric spacer and the second dielectric spacer (see Fig. 1C).
Regarding claim 15, Majhi further discloses wherein the gate dielectric layer (164) comprises a layer of a high-k dielectric material (see pg. 6 line 27-33) directly on the semiconducting oxide material (156) (see Fig. 1C).
Response to Arguments
Applicant’s arguments filed 3/18/2026 have been considered but are moot in view of the new grounds of rejection presented above. In particular, it is noted that the limitation “wherein the metal species originates from the first contact and the second contact and diffuses into the second and third portions of the semiconducting oxide material” recites a process, however the claim is directed to a product. Therefore, this limitation is considered to be product by process limitations. "Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). See MPEP 2113. In the instant case, the metal species doped into the second and third portions of the semiconducting oxide material are the same as the metal species in the first contact and second contact. The presence of the metal species in the second and third portions of the semiconducting oxide material after doping as shown by the art would be the same as or obvious from the species being doped by diffusion from the first contact and the second contact.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren R Bell whose telephone number is (571)272-7199. The examiner can normally be reached M-F 8am-5pm.
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/LAUREN R BELL/Primary Examiner, Art Unit 2896
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