/JOHN R COTTINGHAM/Director, Art Unit 2100 DETAILED ACTION
This Office Action is in response to the Patent Board Decision dated March 2, 2026. A Technology Center Director has approved the reopening of prosecution by signing at the end of this Office Action. When responding to this Office Action, applicant is reminded of the options outlined in MPEP 1204(II).
Claims 1-2, 6-9, 11-16, 18-24, and 26-27 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed on January 30, 2026, fails to comply with 37 CFR 1.97(d) because it lacks the timing fee set forth in 37 CFR 1.17(p). It has been placed in the application file, but the information referred to therein has not been considered.
Claim Interpretation
At least one claim is identified as including a non-limiting contingent limitation. “The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met.” “The broadest reasonable interpretation of a system (or apparatus or product) claim having structure that performs a function, which only needs to occur if a condition precedent is met, requires structure for performing the function should the condition occur. The system claim interpretation differs from a method claim interpretation because the claimed structure must be present in the system regardless of whether the condition is met and the function is actually performed.” See MPEP 2111.04(II).
Regarding claim 1, only one of two modes is required to be identified. When a first mode is identified and a second mode is not identified, the executing in the last paragraph is not required to be performed. Alternatively, when a second mode is identified and a first mode is not identified, the executing in lines 6-7 is not required to be performed.
Regarding claim 6, the shader program only needs to be modified to be executed in one of two modes. When in the first mode and not in the second mode, the first processor is not required to execute as claimed in the last paragraph. Alternatively, when in the second mode and not in the first mode, the first processor is not required to execute as claimed in lines 9-10.
Claim Recommendations
Regarding claim 6, the examiner recommends moving the “analyzing…” paragraph to before the “modifying…” paragraph (and making all necessary changes for proper antecedent basis), to better match the flow set forth in claim 16 and paragraph 60 of the specification, which states “…a shader program is analyzed for register usage on a program section-by-section basis and then modified so as to control the mode of operation of a GPU of the computing system for each program section based on its register usage…”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Grover et al. (US 2009/0259996).
Referring to claim 1, Grover has taught a computer-implemented method comprising: identifying, based on at least one indication (e.g. TABLE 1, _synchthreads() indication) present in a shader program (from paragraph 27, a program may be, for instance, a shader program intended for a GPU (paragraph 26, and FIG.1, 112)), one of a first mode and a second mode (the idea in Grover is that a shader program for a GPU can be translated to be executed on a CPU (FIG.2) that does not support the barrier synchronization primitive (paragraph 38), which ensures that all threads in a thread block complete pre-barrier memory operations before post-barrier memory operations (paragraphs 34-35). Thus, the GPU shader code sequence in TABLE 1 is translated into CPU shader code in TABLE 2, where the second mode, in which threads are synchronized, is carried out by emulating the barrier with a “for” loop, where each thread of the thread block executes serially (paragraph 62). As can be seen from the “for” loop in TABLE 2, instructions for thread 0 (which has a thread ID (tid_x) = 0) are executed first, then the instructions for thread 1 are executed, then the instructions for thread 2 are executed, and so on. This loop causes all threads to execute their instructions before the processor moves on to instructions after the loop, thereby maintaining the barrier synchronization of the original shader program without actually executing an explicit barrier instruction), wherein the at least one indication is declared within a code sequence of the shader program and specifies one of the first mode or the second mode (from TABLE 1, the _synchthreads() indication is declared within the program and specifies the second mode to a translator, which translates the TABLE 1 code into the TABLE 2 code so that the second mode is realized);
(this executing limitation is contingent and, thus, not required to be performed when the first mode is not identified. Thus, the prior art does not need to teach this executing to anticipate the claim) and in response to identifying the second mode, executing at the first processor a set of instructions for a portion of a given wavefront before executing the set of instructions for another portion of the given wavefront (as described above, in this second mode identified by the _synchthreads() indication, instructions of the “for” loop for thread 0 (portion) of the thread block (wavefront) are executed before the instructions of the “for” loop for any one or more of the remaining threads (another portion) of the thread block).
Referring to claim 2, Grover has taught the method of claim 1, wherein the at least one indication includes a command for the first processor to operate in the second mode (again, see the _synchthreads() command in the program code of TABLE 1. This command is responsible for causing the first processor to operate in the second mode).
Allowable Subject Matter
Claims 6-9, 11-16, 18-24, and 26-27 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 6, the prior art of record, alone or in combination, has not taught, together with all other claimed features, the analyzing and the modifying in combination with the execution in at least one of the two modes.
Regarding claims 14 and 18, the claims are allowable for reasons given in the Board Decision mailed on March 2, 2026.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183
/JOHN R COTTINGHAM/Director, Art Unit 2100
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