Prosecution Insights
Prosecution Insights
Tech Center 2100 • Art Units: 2183
This examiner grants 58% of resolved cases
| App # | Title | Status | Assignee |
|---|---|---|---|
| 18665725 | DIFFERENTIAL TREATMENT OF CONTEXT-SENSITIVE INDIRECT BRANCHES IN INDIRECT TARGET PREDICTORS | Non-Final OA | HUAWEI TECHNOLOGIES CO., LTD. |
| 18628460 | Interleave Execution Circuit | Final Rejection | Apple Inc. |
| 18453010 | Coprocessor Register Renaming | Non-Final OA | Apple Inc. |
| 17561006 | OPTIMIZATION OF CAPTURED LOOPS IN A PROCESSOR FOR OPTIMIZING LOOP REPLAY PERFORMANCE | Final Rejection | Microsoft Technology Licensing, LLC |
| 18762800 | APPARATUS AND METHOD FOR PERFORMING A SPLICE OPERATION FOR VECTORS | Final Rejection | ARM LIMITED |
| 17804453 | GRAPHICS PROCESSOR TO EXECUTE AN ACTIVATION INSTRUCTION TO ACTIVATE PLURAL EXECUTION LANES | Final Rejection | Arm Limited |
| 17481285 | RECONFIGURABLE CHIP AND COMPUTER ARCHITECTURE USING GOSSIP PROTOCOL FOR MESSAGE PASSING | Final Rejection | THE CURATORS OF THE UNIVERSITY OF MISSOURI |
| 18436982 | BFLOAT16 COMPARISON INSTRUCTIONS | Non-Final OA | Intel Corporation |
| 18399473 | SYSTEMS AND METHODS FOR EXECUTING A FUSED MULTIPLY-ADD INSTRUCTION FOR COMPLEX NUMBERS | Non-Final OA | Intel Corporation |
| 17843179 | SELECTIVE DISABLE OF HISTORY-BASED PREDICTORS ON MODE TRANSITIONS | Final Rejection | Intel Corporation |
| 17841555 | PROCESSOR CIRCUITRY TO DETERMINE A STATE OF ENABLEMENT OF A SYNCHRONIZATION CONTROL FOR THREADS OF EXECUTION | Final Rejection | Intel Corporation |
| 17589428 | APPARATUS AND METHOD FOR SCALING PRE-SCALED RESULTS OF COMPLEX MUTIPLY-ACCUMULATE OPERATIONS ON PACKED REAL AND IMAGINARY DATA ELEMENTS | Final Rejection | Intel Corporation |
| 18089582 | MEMORY CONTROLLER AND MEMORY SYSTEM FOR GENERATING INSTRUCTION SET BASED ON NON-INTERLEAVING BLOCK GROUP INFORMATION | Non-Final OA | SK hynix Inc. |
| 18110605 | SYSTEMS AND METHODS FOR PROCESSING ATOMIC COMMANDS | Final Rejection | Mobileye Vision Technologies Ltd. |
| 18160321 | COMPUTER-READABLE RECORDING MEDIUM STORING PROGRAM AND METHOD OF SPARSE MATRIX OPERATION WITH MASK BIT EXPANSION WHEN PROGRAM COUNTER IS IN SETTING RANGE | Final Rejection | Fujitsu Limited |
| 18176493 | REDUCING A NUMBER OF COMMANDS TRANMITTED TO A CO-PROCESSOR BY COMBINING REGISTER-SETTING COMMANDS WITH CONTINUOUS REGISTER ADDRESSES | Non-Final OA | Glenfly Tech Co., Ltd. |
| 18176496 | REDUCING A NUMBER OF COMMANDS TRANSMITTED TO A CO-PROCESSOR BY COMBINING REGISTER-SETTING COMMANDS WITH SAME AND CONTINUOUS REGISTER ADDRESSES | Final Rejection | Glenfly Tech Co., Ltd. |
| 18148873 | Permute Instructions for Register-Based Lookups | Non-Final OA | Advanced Micro Devices, Inc. |
| 17843640 | Controlling Instruction Dispatch based on Counts of Dynamic VLIW Data Communications | Final Rejection | Advanced Micro Devices, Inc. |
| 17468574 | System of Multiple Stacks in a Processor Devoid of an Effective Address Generator | Non-Final OA | Microchip Technology Inc. |
| 18665108 | PROCESSING METHOD OF MIXED PRECISION OPERATION AND INSTRUCTION PROCESSING APPARATUS | Final Rejection | Alibaba Innovation Private Limited |
| 18819125 | EXECUTION METHOD FOR INSTRUCTION CONFLICT, INSTRUCTION PROCESSING MODULE AND PROCESSOR | Final Rejection | GLENFLY TECH CO., LTD. (SHANGHAI) |
| 18388875 | PARALLEL PROCESSING WITH SWITCH BLOCK EXECUTION | Non-Final OA | Ascenium, Inc. |
| 18239770 | PARALLEL PROCESSING ARCHITECTURE WITH MEMORY BLOCK TRANSFERS | Non-Final OA | Ascenium, Inc. |
| 18236442 | PARALLEL PROCESSING ARCHITECTURE WITH BIN PACKING | Non-Final OA | Ascenium, Inc. |
| 18228001 | PARALLEL PROCESSING ARCHITECTURE WITH DUAL LOAD BUFFERS | Non-Final OA | Ascenium, Inc. |
| 18220331 | PARALLEL PROCESSING ARCHITECTURE WITH COUNTDOWN TAGGING | Non-Final OA | Ascenium, Inc. |
| 18195407 | PARALLEL PROCESSING OF MULTIPLE LOOPS WITH LOADS AND STORES | Non-Final OA | Ascenium, Inc. |
| 17879827 | PARALLEL PROCESSING ARCHITECTURE SUPPORTING MULTICYCLE ATOMIC OPERATIONS | Final Rejection | Ascenium, Inc. |
| 17704056 | PARALLEL PROCESSING ARCHITECTURE USING SPECULATIVE ENCODING | Final Rejection | Ascenium, Inc. |
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