DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the amendment filed on 7/07/25. Claims 27, 29, 32, 33, 48, and 51-55 are pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 48, 32, 33, 27 and 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US PGPub 2013/0062704, hereinafter referred to as “Cheng”) in view of Chuang et al. (US PGPub 2013/0256805, hereinafter referred to as “Chuang”).
Cheng discloses the semiconductor the device substantially as claimed. See figures 1-13 and corresponding text, where Cheng teaches, in claim 48, a device, comprising:
a PMOS transistor, comprising:
a first gate electrode (132) (left side) on a gate dielectric (IL, 115) which is in direct contact with a first portion (above channel region) of semiconductor; (figure 13; [0035], [0049])
a first dielectric material (115) in direct contact with the gate dielectric (IL, 115) (including interfacial layer [0034]) and in direct contact with a second portion (above LDD regions on the left side) of semiconductor (102), adjacent to the first portion, wherein the first dielectric material (115) has a different composition than the gate dielectric (IL, 115) and comprises lanthanum and oxygen; and (figure 13; [0035], [0049])
an NMOS transistor, comprising:
a second gate electrode (132) (right side) on the gate dielectric (IL, 115) which is in direct contact with a third portion (above channel region on the right side) of semiconductor (102); (figure 13; [0035], [0049])
a second dielectric material (115) in direct contact with the gate dielectric (IL, 115) and in direct contact with a fourth portion (above the LDD regions on the right side) of semiconductor, adjacent to the third portion, wherein the second dielectric material (115) has a different composition than the gate dielectric, a different composition than the first dielectric material, and comprises aluminum and oxygen. (figure 13; [0035], [0049])
Cheng fails to explicitly show, in claim 48, wherein the first dielectric material has a different composition than the gate dielectric and comprises lanthanum and oxygen and wherein the second dielectric material has a different composition than the gate dielectric, a different composition than the first dielectric material, and comprises aluminum and oxygen, for the PMOS and NMOS transistors, respectively.
Cheng teaches, having a list of different high-k dielectric materials that include lanthanum, aluminum and oxygen, that formed different material compositions La.sub.2O.sub.3 and Al.sub.2O.sub.3 ([0035]). In addition, these high-k gate dielectric materials are suitable materials to satisfy the work function requirements ([0026]).
Chuang teaches, a similar CMOS semiconductor device having a PMOS (202) and NMOS (204) regions, that includes a gate dielectric layer that includes interfacial layer and a multiple layer of high-k dielectric layers (figure 11a’; [0013]). In addition, Chuang includes a capping layer made of a lanthanum oxide composition [0017]. Lastly, Chuang provides the advantages of tuning the work function of the metal gate layer ([0016-0017]).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed, to incorporate wherein the first dielectric material has a different composition than the gate dielectric and comprises lanthanum and oxygen and wherein the second dielectric material has a different composition than the gate dielectric, a different composition than the first dielectric material, and comprises aluminum and oxygen, for the PMOS and NMOS transistors, respectively, in the device of Cheng, according to the teachings of Cheng and Chuang, with the motivation of tuning the work function of the metal gate layer to satisfy the PMOS and NMOS transistor requirements within the semiconductor devices (ex. adjusting threshold voltages and increasing drive current).
Cheng in view of Chuang shows, in claim 27, wherein the semiconductor comprises a III-V semiconductor compound. ([0030])
Cheng in view of Chuang shows, in claim 29, wherein the gate dielectric comprises a metal and oxygen. ([0030-0035])
Cheng in view of Chuang shows, in claim 32, wherein the III-V semiconductor compound comprises any of In and As, Ga and As, In and P, Ga and P, In and Sb, Al and As, Ga and Sb, a first alloy of In, Ga and As, a second alloy of In, Al and As, a third alloy of Ga, As and Al, a fourth alloy of Ga, As and Sb, and a fifth alloy of In, As and Sb, and wherein the second dielectric layer comprises Al-rich aluminum oxide. ([0030])
Cheng in view of Chuang shows, in claim 33, wherein the III-V semiconductor compound comprises any of In and As, Ga and As, In and P, Ga and P, In and Sb, Al and As, Ga and Sb, a first alloy of In, Ga and As, a second alloy of In, Al and As, a third alloy of Ga, As and Al, a fourth alloy of Ga, As and Sb, and a fifth alloy of In, As and Sb, and wherein the first dielectric layer comprises La-rich lanthanum oxide. ([0035])
Allowable Subject Matter
Claims 51 and 52 are allowed over the prior art of record.
Response to Arguments
Applicant's arguments filed 7/07/25 have been fully considered but they are not persuasive. In the Remarks on pages 5-7:
The applicant raises the clear issue as to whether Cheng alone or in combination with Chuang suggests or render obvious any dielectric material that includes lanthanum/oxygen within a PMOS transistor while another dielectric material includes aluminum/oxygen within an NMOS transistor.
The Examiner views that Cheng in view of Chuang suggests the above limitation and/or statements. Specifically, Cheng teaches forming a first gate electrode (132) (left side) on a gate dielectric (IL, 115) which is in direct contact with a first portion (above channel region) of semiconductor; (figure 13; [0035], [0049]). In addition, Cheng teaches a second gate electrode (132) (right side) on the gate dielectric (IL, 115) which is in direct contact with a third portion (above channel region on the right side) of semiconductor (102); (figure 13; [0035], [0049]). Also, Cheng teaches the high dielectric to include a metal and oxygen that includes both lanthanum/oxygen aluminum/oxygen materials. Lastly, Cheng teaches adjusting the threshold voltages for the PFET and NFET devices by filling the oxygen vacancies in the high-K dielectric layers ([0029]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 11-8.
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/STANETTA D ISAAC/Examiner, Art Unit 2898 October 10, 2025
/JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898