DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the amendment filed on 3/30/26. Claims 1-13 and 15-29 are pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-10, 26, 27 and 29 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US PGPub 2014/0117420, hereinafter referred to as “Chen”).
Chen discloses the semiconductor device as claimed. See figures 1-20 and corresponding text, where Chen teaches, in claim 1, a semiconductor device, comprising:
a semiconductor substrate (101); and
a back end of line (BEOL) stack over the semiconductor substrate (101), wherein the BEOL stack comprises:
first interconnects (130) (one or two on the far left side) and second interconnects (140) (on the far right side) in an interconnect layer of the BEOL stack, wherein the interconnect layer comprises a single dielectric (120), and wherein the first interconnects (130) and the second interconnects (140) are of a same width throughout the interconnect layer of the BEOL stack, and wherein the first interconnects (130) have a first height and the second interconnects (140) have a second height that is different than the first height, and wherein the first interconnects (130) have an uppermost surface at a same level as an uppermost surface of the second interconnects (140), and the BEOL stack comprising (figure 1; [0042-0046])
third interconnects (140) (the center one) of substantially the same width as the first interconnects (130) (one or two on the far left side) and the second interconnects (on the far right side) throughout the interconnect layer of the BEOL stack, wherein the third interconnects (140) have a third height that is between the first height (130) and the second height (140), the third height different than the first height and different than the second height, wherein the third interconnects have an uppermost surface at the same level as the uppermost surface of the first interconnects and the uppermost surface of the second interconnects (figure 1; [0042-0047]),
wherein the first interconnects, the second interconnects, and the third interconnects all have a same total material composition, and wherein each of the first interconnects, the second interconnects and the third interconnects are separate from one another (figure 1; [0043-0047]).
Chen teaches, in claim 2, further comprising:
an air gap dielectric (151) surrounding the first interconnects and/or the second interconnects ([0049]).
Chen teaches, in claim 3, wherein the semiconductor substrate comprises a first processing block and a second processing block (In the applicant’s disclosure defines the first and second processing blocks to be first and second interconnects, respectively, (see [0074-0076]) (figure 1; [0043-0047]).
Chen teaches, in claim 4, wherein an interconnect scheme for the first processing block comprises the first interconnects, and wherein an interconnect scheme for the second processing block comprises the second interconnects (In the applicant’s disclosure defines the first and second processing blocks to be first and second interconnects, respectively, (see [0074-0076]) (figure 1; [0043-0047]).
Chen teaches, in claim 5, wherein the first processing block comprises a first path and a second path (In the applicant’s disclosure defines the first and second processing blocks to be first and second paths, respectively, (see [0074-0076]) (figure 1; [0043-0047]).
Chen teaches, in claim 6, wherein the first path comprises first interconnects, and wherein the second path comprises second interconnects In the applicant’s disclosure defines the first and second processing blocks to be first and second interconnects, respectively, (see [0074-0076]) (figure 1; [0043-0047]).
Chen teaches, in claim 7, wherein the first path comprises a first net and a second net (In the applicant’s disclosure defines the first and second nets to be first and second interconnects, respectively, (see [0079]) (figure 1; [0043-0047]).
Chen teaches, in claim 8, wherein the first net comprises first interconnects, and wherein the second net comprises second interconnects (In the applicant’s disclosure defines the first and second nets to be first and second interconnects, respectively, (see [0079]) (figure 1; [0043-0047]).
Chen teaches, in claim 9, wherein the first net comprises a first segment and a second segment (In the applicant’s disclosure defines the first and second segments to be first and second interconnects, respectively, (see [0081]) (figure 1; [0043-0047]).
Chen teaches, in claim 10, wherein the first segment comprises first interconnects, and wherein the second segment comprises second interconnects (In the applicant’s disclosure defines the first and second segments to be first and second interconnects, respectively, (see [0081]) (figure 1; [0043-0047]).
Chen teaches, in claim 26, a semiconductor device, comprising:
a semiconductor substrate (101); and
a back end of line (BEOL) stack over the semiconductor substrate (101), wherein the BEOL stack comprises:
first interconnects (130) (one or two on the far left side) and second interconnects (140) (on the far right side) in an interconnect layer of the BEOL stack (figure 1; [0043]), wherein the interconnect layer comprises a single dielectric (120), and wherein the first interconnects (130) (one or two on the far left side) and the second interconnects (140) (on the far right side) are of a same width throughout the interconnect layer of the BEOL stack (figure 1; [0043]), and wherein the first interconnects (130) (one or two on the far left side) have a first height and the second interconnects (140) (on the far right side) have a second height that is different than the first height, and wherein the first interconnects (130) (one or two on the far left side) have an uppermost surface at a same level as an uppermost surface of the second interconnects (140) (on the far right side), (figure 1; [0042-0046])
wherein the semiconductor substrate (101) comprises a first processing block and a second processing block (In the applicant’s disclosure defines the first and second processing blocks to be first and second interconnects, respectively, (see [0074-0076]), and wherein an interconnect scheme for the first processing block comprises the first interconnects (130) (one or two on the far left side), and wherein an interconnect scheme for the second processing block comprises the second interconnects (140) (on the far right side), and the BEOL stack comprising third interconnects (140) (the center one) of substantially the same width as the first interconnects (130) (one or two on the far left side) and the second interconnects throughout the interconnect layer of the BEOL stack (figure 1; [0043]), wherein the third interconnects (140) (the center one) have a third height that is between the first height and the second height, the third height different than the first height and different than the second height, wherein the third interconnects (140) (the center one) have an uppermost surface at the same level as the uppermost surface of the first interconnects (130) (one or two on the far left side) and the uppermost surface of the second interconnects, (figure 1; [0043-0047])
wherein the first interconnects (130) (one or two on the far left side), the second interconnects (140) (on the far right side), and the third interconnects (140) (the center one) all have a same total material composition, and wherein each of the first interconnects (130) (one or two on the far left side), the second interconnects, and the third interconnects (140) (the center one) are separate from one another (figure 1; [0043-0047]).
Chen teaches, in claim 27, a semiconductor device, comprising:
a semiconductor substrate (101); and
a back end of line (BEOL) stack (figure 1; [0043]) over the semiconductor substrate (101), wherein the BEOL stack comprises: (figure 1; [0043-0047])
first interconnects (130) (one or two on the far left side) and second interconnects (140) (on the far right side) in an interconnect layer of the BEOL stack (figure 1: [0043]), wherein the interconnect layer comprises a single dielectric (120), and wherein the first interconnects (130) (one or two on the far left side) and the second interconnects (140) (on the far right side) are of a same width throughout the interconnect layer of the BEOL stack (figure 1; [0043]), and wherein the first interconnects (130) (one or two on the far left side) have a first height and the second interconnects (140) (on the far right side) have a second height that is different than the first height, and (figure 1; [0042-0046])
wherein the first interconnects (130) (one or two on the far left side) have an uppermost surface at a same level as an uppermost surface of the second interconnects (140) (on the far right side), wherein the semiconductor substrate (101) comprises a first processing block and a second processing block, and wherein the first processing block comprises a first path and a second path (In the applicant’s disclosure defines the first and second processing blocks to be first and second interconnects, respectively, (see [0074-0076]), and the BEOL stack (figure 1; [0043]) comprising third interconnects (140) (the center one) of substantially the same width as the first interconnects (130) (one or two on the far left side) and the second interconnects (140) (on the far right side) throughout the interconnect layer of the BEOL stack (figure 1; [0043]), wherein the third interconnects (140) (the center one) have a third height that is between the first height and the second height, the third height different than the first height and different than the second height, wherein the third interconnects (140) (the center one) have an uppermost surface at the same level as the uppermost surface of the first interconnects (130) (one or two on the far left side) and the uppermost surface of the second interconnects, (figure 1; [0043-0047])
wherein the first interconnects (130) (one or two on the far left side), the second interconnects (140) (on the far right side), and the third interconnects (140) (the center one) all have a same total material composition, and wherein each of the first interconnects (130) (one or two on the far left side), the second interconnects (140) (on the far right side), and the third interconnects (140) (the center one) are separate from one another (figure 1; [0043-0047]).
Chen teaches, in claim 29, a semiconductor device, comprising:
a semiconductor substrate (101); and
a back end of line (BEOL) stack (figure 1; [0043]) over the semiconductor substrate (101), wherein the BEOL stack comprises:
first interconnects (130) (one or two on the far left side) and second interconnects (140) (on the far right side) in an interconnect layer of the BEOL stack (figure 1; [0043]), wherein the interconnect layer comprises a single dielectric (120), and wherein the first interconnects (130) (one or two on the far left side) and the second interconnects (140) (on the far right side) are of a same width throughout the interconnect layer of the BEOL stack, and wherein the first interconnects (130) (one or two on the far left side) have a first height and the second interconnects (140) (on the far right side) have a second height that is different than the first height, wherein the first interconnects (130) (one or two on the far left side) have an uppermost surface at a same level as an uppermost surface of the second interconnects (140) (on the far right side), and
wherein the BEOL stack (figure 1; [0034]) comprises a plurality of interconnect layers that each comprise first interconnects (130) (one or two on the far left side) and second interconnects (140) (on the far right side), and the BEOL stack comprising third interconnects (140) (the center one) of substantially the same width as the first interconnects (130) (one or two on the far left side) and the second interconnects (140) (on the far right side) throughout the interconnect layer of the BEOL stack, wherein the third interconnects (140) (the center one) have a third height that is between the first height and the second height, the third height different than the first height and different than the second height, wherein the third interconnects (140) (the center one) have an uppermost surface at the same level as the uppermost surface of the first interconnects (130) (one or two on the far left side) and the uppermost surface of the second interconnects (140) (on the far right side), wherein the first interconnects (130) (one or two on the far left side), the second interconnects (140) (on the far right side), and the third interconnects (140) (the center one) all have a same total material composition, and wherein each of the first interconnects (130) (one or two on the far left side), the second interconnects (140) (on the far right side), and the third interconnects (140) (the center one) are separate from one another (figure 1; [0043-0048]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 11 and 12, is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US PGPub 2014/0117420, hereinafter referred to as “Chen”) as applied to claim 1 above, and further in view of Gstrein et al. (US PGPub 2014/0029181, hereinafter referred to as “Gstrein”).
Chen discloses the semiconductor device substantially as claimed. See the rejection above.
However, Chen fails to teach, in claim 11, further comprising:
a drive cell; and
a plurality of load cells, wherein each load cell is electrically coupled to the drive cell by interconnects in the BEOL stack.
Gstrein teaches, in claim 11, a similar device that includes memory cells (figure 2; [0050], [0059-0064]). In addition, Gstrein provides the advantages of reducing current densities and increasing electromigration resistance ([0041]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate comprising:
a drive cell; and
a plurality of load cells, wherein each load cell is electrically coupled to the drive cell by interconnects in the BEOL stack, in the device of Chen, according to the teachings of Gstrein, with the motivation of reducing current densities and increasing electromigration resistance.
Chen fails to teach, in claim 12, wherein a first portion of the signal path proximate to the drive cell is one of the first interconnects, and wherein second portions of the signal path proximate to the plurality of load cells are ones of the second interconnects.
Gstrein teaches, in claim 12, a similar device that includes memory cells (figure 2; [0050], [0059-0064]). In addition, Gstrein provides the advantages of reducing current densities and increasing electromigration resistance ([0041]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate wherein a first portion of the signal path proximate to the drive cell is one of the first interconnects, and wherein second portions of the signal path proximate to the plurality of load cells are ones of the second interconnects, in the device of Chen, according to the teachings of Gstrein, with the motivation of reducing current densities and increasing electromigration resistance.
Claim(s) 15-22 and 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US PGPub 2014/0117420, hereinafter referred to as “Chen”) in view of Gstrein et al. (US PGPub 2014/0029181, hereinafter referred to as “Gstrein”).
Chen discloses the semiconductor device substantially as claimed. See figures 1-20 and corresponding text, where Chen teaches, in claim 15, a semiconductor device, comprising:
a semiconductor substrate (101), comprising:
a back end of line (BEOL) stack (figure 1; [0043]) over the semiconductor substrate (101), wherein the BEOL stack (figure 1; [0043]) comprises a plurality of interconnect layers, wherein one of the plurality of interconnect layers comprises:
a single dielectric (120) (figure 1; [0043-0048]);
first interconnects (130) (one or two on the far left side) having a first height;
second interconnects (140) (on the far right side) having a second height that is less than the first height, wherein the second interconnects (140) (on the far right side) have an uppermost surface at a same level as an uppermost surface of the first interconnects (130) (one or two on the far left side), and wherein the first interconnects and the second interconnects (140) (on the far right side) are of a same width throughout the interconnect layer of the BEOL stack (figure 1; [0043-0048]); and
third interconnects (140) (the center one) of substantially the same width as the first interconnects (130) (one or two on the far left side) and the second interconnects (140) (on the far right side) throughout the interconnect layer of the BEOL stack and having a third height that is between the first height and the second height, the third height different than the first height and different than the second height wherein the third interconnects (140) (the center one) have an uppermost surface at the same level as the uppermost surface of the first interconnects (130) (one or two on the far left side) and the uppermost surface of the second interconnects (140) (on the far right side), wherein the first interconnects (130) (one or two on the far left side), the second interconnects (140) (on the far right side), and the third interconnects (140) (the center one) all have a same total material composition and wherein each of the first interconnects (130) (one or two on the far left side), the second interconnects (140) (on the far right side), and the third interconnects (140) (the center one) are separate from one another (figure 1; [0043-0048]).
However, Chen fails to teach, in claim 15, a processor block; a memory block coupled to the processor block.
Gstrein teaches, in claim 15, a similar device that includes memory cells (figure 2; [0050], [0059-0064]). In addition, Gstrein provides the advantages of reducing current densities and increasing electromigration resistance ([0041]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate a processor; a memory block coupled to the processor block, in the device of Chen, according to the teachings of Gstrein, with the motivation of reducing current densities and increasing electromigration resistance.
Chen in view of Gstrein teaches, in claim 16, wherein the memory block is a register file and comprises word lines and bit lines implemented in the BEOL stack. (figure 2; [0050], [0059-0064], Gstrein)
Chen in view of Gstrein teaches, in claim 17, wherein the word lines are implemented with first interconnects. (figure 2; [0050], [0059-0064], Gstrein)
Chen in view of Gstrein teaches, in claim 18, wherein the bit lines are implemented with second interconnects. (figure 2; [0050], [0059-0064], Gstrein)
Chen in view of Gstrein teaches, in claim 19, further comprising air-gap dielectrics (151) (figure 1; [0048], Chen), wherein the air-gap dielectrics (151) are around the word lines and the bit lines, or wherein the air-gap dielectrics (151) are only around the bit lines. (figure 2; [0038], Gstrein)
Chen in view of Gstrein fails to explicitly teach, in claim 20, wherein the memory block is static random access memory (SRAM), and comprises word lines and bit lines implemented in the BEOL stack.
However, Gstrein does mention about volatile memory ([0059]), where it is conventionally known that a SRAM is specific type of volatile memory device. In addition, Gstrein provides the advantages of reducing current densities and increasing electromigration resistance ([0041]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate wherein the memory block is static random access memory (SRAM), and comprises word lines and bit lines implemented in the BEOL stack, in the device of Chen, according to the teachings of Gstrein, with the motivation of reducing current densities and increasing electromigration resistance. In addition, to the well-known conventional benefits of faster access time.
Chen in view of Gstrein teaches, in claim 21, wherein the bit lines are implemented with second interconnects. (figure 2; [0050], [0059-0064], Gstrein)
Chen in view of Gstrein teaches, in claim 22, further comprising:
an air gap dielectric (155) (Chen teaches ) around the bit lines, and wherein the word lines are implemented with first interconnects. (figure 2; [0038] [0050], [0059-0064], Gstrein)
Chen teaches, in claim 28, a semiconductor device, comprising:
a semiconductor substrate (101);
a back end of line (BEOL) stack (figure 1; [0043]) over the semiconductor substrate (101), wherein the BEOL stack comprises: (figure 1; [0043-0048])
first interconnects (130) (one or two on the far left side) and second interconnects (140) (on the far right side) in an interconnect layer of the BEOL stack, wherein the interconnect layer comprises a single dielectric (120), and wherein the first interconnects (130) (one or two on the far left side) and the second interconnects (140) (on the far right side) are of a same width throughout the interconnect layer of the BEOL stack, and wherein the first interconnects (130) (one or two on the far left side) have a first height and the second interconnects (140) (on the far right side) have a second height that is different than the first height, and wherein the first interconnects (130) (one or two on the far left side) have an uppermost surface at a same level as an uppermost surface of the second interconnects (140) (on the far right side), and the BEOL stack comprising
third interconnects (140) (the center one) of substantially the same width as the first interconnects (130) (one or two on the far left side) and the second interconnects (140) (on the far right side) throughout the interconnect layer of the BEOL stack, wherein the third interconnects (140) (the center one) have a third height that is between the first height and the second height, the third height different than the first height and different than the second height, wherein the third interconnects (140) (the center one) have an uppermost surface at the same level as the uppermost surface of the first interconnects (130) (one or two on the far left side) and the uppermost surface of the second interconnects (140) (on the far right side), wherein the first interconnects (130) (one or two on the far left side), the second interconnects (140) (on the far right side), and the third interconnects (140) (the center one) all have a same total material composition, and wherein each of the first interconnects (130) (one or two on the far left side), the second interconnects (140) (on the far right side), and the third interconnects are separate from one another (figure 1; [0043-0048]).
However, Chen fails to explicitly teach a signal path comprising:
a drive cell; and
a plurality of load cells, wherein each load cell is electrically coupled to the drive cell by interconnects in the BEOL stack.
Gstrein teaches, in claim 28, a similar device that includes memory cells (figure 2; [0050], [0059-0064]). In addition, Gstrein provides the advantages of reducing current densities and increasing electromigration resistance ([0041]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate a signal path comprising:
a drive cell; and
a plurality of load cells, wherein each load cell is electrically coupled to the drive cell by interconnects in the BEOL stack, in the device of Chen, according to the teachings of Gstrein, with the motivation of reducing current densities and increasing electromigration resistance.
Claim(s) 23, 24 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US PGPub 2014/0117420, hereinafter referred to as “Chen”) in view of Gstrein et al. (US PGPub 2014/0029181, hereinafter referred to as “Gstrein”).
Chen discloses the semiconductor device substantially as claimed. See figures 1-20 and corresponding text, where Chen teaches, in claim 23, an electronic system, comprising: (figure 1; [0043-0048])
a semiconductor substrate (101);
first interconnects (130) (one or two on the far left side) and second interconnects (140) (on the far right side) in an interconnect layer over the semiconductor substrate, wherein the interconnect layer comprises a single dielectric, and wherein the first interconnects (130) (one or two on the far left side) and the second interconnects (140) (on the far right side) are of a same width throughout the interconnect layer of the BEOL stack, and wherein the first interconnects (130) (one or two on the far left side) have a first height and the second interconnects (140) (on the far right side) have a second height that is different than the first height, and wherein the first interconnects (130) (one or two on the far left side) have an uppermost surface at a same level as an uppermost surface of the second interconnects (140) (on the far right side); and
third interconnects (140) (the center one) of substantially the same width as the first interconnects and the second interconnects (140) (on the far right side) throughout the interconnect layer of the BEOL stack and having a third height that is between the first height and the second height, the third height different than the first height and different than the second height, wherein the third interconnects (140) (the center one) have an uppermost surface at the same level as the uppermost surface of the first interconnects (130) (one or two on the far left side) and the uppermost surface of the second interconnects (140) (on the far right side), wherein the first interconnects (130) (one or two on the far left side), the second interconnects (140) (on the far right side), and the third interconnects (140) (the center one) all have a same total material composition, and wherein each of the first interconnects (130) (one or two on the far left side), the second interconnects (140) (on the far right side), and the third interconnects (140) (the center one) are separate from one another.
Chen explicitly failed to teach, in claim 23, a board; and
an electronic package coupled to the board, wherein the electronic package comprises a semiconductor die, and wherein the semiconductor die
Gstrein teaches, an electronic package coupled to a circuit board comprising a semiconductor chip (figure 2; [0040]). In addition, Gstrein provides the advantages of reducing current densities and increasing electromigration resistance ([0041]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate a board; and
an electronic package coupled to the board, wherein the electronic package comprises a semiconductor die, and wherein the semiconductor die, in the device of Chen, according to the teachings of Gstrein, with the motivation of reducing current densities and increasing electromigration resistance.
Chen failed to explicitly teach, in claim 24, wherein the semiconductor substrate comprises: a processor block; and
a memory block that is electrically coupled to the processor block by one or more interconnects in the interconnect layer.
Gstrein teaches, in claim 24, a similar device that includes memory cells (figure 2; [0050], [0059-0064]). In addition, Gstrein provides the advantages of reducing current densities and increasing electromigration resistance ([0041]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate wherein the semiconductor substrate comprises: a processor block; and
a memory block that is electrically coupled to the processor block by one or more interconnects in the interconnect layer, in the device of Chen, according to the teachings of Gstrein, with the motivation of reducing current densities and increasing electromigration resistance.
Chen in view of Gstrein shows, in claim 25, wherein the memory block is a register file or a static random access memory (SRAM). ([0061], Gstrein register)
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-13 and 15-29 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant’s amendment has necessitated new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 10-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STANETTA D ISAAC/ Examiner, Art Unit 2898 June 5, 2026
/Leonard Chang/ Supervisory Patent Examiner, Art Unit 2898
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