DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/7/2025 has been entered.
Response to Arguments
Applicant’s arguments filed 9/9/2025 with respect to the pending claims have been fully considered but are moot in view of the new grounds of rejection.
Applicant argues that the prior art does not disclose the newly added limitation.
This argument is not persuasive since the reference to Raaijmakers et al. (US PGPub 2004/0130029) teaches these limitation. The drawing objection was not addressed, therefore are being maintained.
The rejection has updated to include the newly added limitations.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the widths of each interconnect line and the respective pitches as claimed must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Applicant argues that fig. 55A shows claimed features. Examiner respectfully disagrees. As can be seen from the figures, each wiring is drawn to be the same width, where clearly the claims explicitly claim certain metal lines as being the same widths and certain metal lines being different widths. The claims further require the pitches P1 and P3 to be equal to each other. The instant invention claiming these features with specificity should illustrate the invention with equal specificity if this is the focal point of the instant application’s novelty.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 5, 11-19, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kornachuk et al. (US PGPub 2009/0300575; hereinafter “Kornachuk”) in view of Smayling et al. (US PGPub 2008/0222587; hereinafter “Smayling”) and Chang et al. (US PGPub 2017/0194252; hereinafter “Chang”), Himeno et al. (US PGPub 20130112935; hereinafter “Himeno”), and Raaijmakers et al. (US PGPub 2004/0130029; hereinafter “Raaijmakers”).
Re claim 2: Kornachuk teaches (e.g. fig. 10C and labeled fig. 10C below) an integrated circuit structure, comprising: an inter-layer dielectric (ILD) layer (dielectric materials insulate patterned conductive layers from each other; e.g. paragraph 132; hereinafter “IL”) above a substrate (multi-level structures defined on a silicon substrate; e.g. paragraph 132); and a first plurality of conductive interconnect lines (1061, 1030, 1060, 1020 as shown in fig. 10C and labeled fig. 10C; hereinafter “CIL”) in and spaced apart by the ILD layer (IL), the first plurality of conductive interconnect lines (CIL) comprising: a first interconnect line (top-most 1060 as shown in labeled fig. 10C and labeled as “A1”) having a width (SRW); a second interconnect line (top-most 1030 as shown in labeled fig. 10C and labeled as “B2”) immediately adjacent the first interconnect line (A1), the second interconnect line (B2) having a width (W2) different than the width (SRW) of the first interconnect line (A1); a third interconnect line (1061 as shown in fig. 10C and labeled as “A3”) immediately adjacent the second interconnect line (B2), the third interconnect line (A3) having a width (SRW) the same as the width (SRW) of the first interconnect line (A1); and a fourth interconnect line (1024 as shown in labeled fig. 10C and labeled as “C4”) immediately adjacent the third interconnect line (A3), the fourth interconnect line (C4) having a width (W1) different than the width of the first interconnect line (A1), and the width (W1) of the fourth interconnect line (C4) different than the width (W2) of the second interconnect line (B2).
PNG
media_image1.png
702
418
media_image1.png
Greyscale
Kornachuk is silent as to explicitly teaching a fifth interconnect line immediately adjacent the fourth interconnect line, the fifth interconnect line having a width the same as the width of the first interconnect line; and a sixth interconnect line immediately adjacent the fifth interconnect line, the sixth interconnect line having a width the same as the width of the second interconnect line; a second ILD layer above the ILD layer; and a second plurality of conductive interconnect lines in and spaced apart by the second ILD layer, each of the second plurality of conductive interconnect lines having a width greater than a greatest width of the first, second, third, fourth, fifth and sixth interconnect lines of the plurality of conductive interconnect lines.
Smayling teaches, as shown in figs. 5A-5F, that sub-layouts can be formed such that they are combined to generate a desired sequence of M2 level layouts 505A, 505B, for example, combining cell variant 501A and cell variant 501B, as chosen in figs. 5D, 5E, to have alternating M2 layers 505A, 505B (which maintains an ABAB-ABAB pattern) and alternating lines 503A, 503B (which maintains an ABAB pattern by combining ABA-BAB cells). This concept can be applied to the structure of fig. 10C of Kornachuk by repeating 1061, 1030, 1060, and 1020, which when repeating would have a structure similar to 1060, 1061 be immediately adjacent to 1020 as shown in labeled fig. 10C above, these additional repeating element will be referred to as labeled elements “A5” and “B6”.
Therefore Kornachuk in view of Smayling teaches a fifth interconnect line (A5 of Kornachuk) immediately adjacent the fourth interconnect line (C4 of Kornachuk), the fifth interconnect line (A5) having a width (SRW) the same as the width (SRW) of the first interconnect line (A1); and a sixth interconnect line (B6 of Kornachuk) immediately adjacent the fifth interconnect line (A5 of Kornachuk), the sixth interconnect line (B6 of Kornachuk) having a width (W2) the same as the width (W2) of the second interconnect line (B2 of Kornachuk).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the known method of repeating metallization lines in predetermined layout patterns to achieve a desired layout as taught by Smayling in the device of Kornachuk in order to have the predictable result of using a known method of repeating metallization structures since in semiconductor device fabrication, these structures are not made in a one at a time sequence but rather plural identical structures are formed across an entire wafer and these plurality of these elements are made.
Kornachuk in view of Smayling is silent as to explicitly teaching a second ILD layer above the ILD layer; and a second plurality of conductive interconnect lines in and spaced apart by the second ILD layer, each of the second plurality of conductive interconnect lines having a width greater than a greatest width of the first, second, third, fourth, fifth and sixth interconnect lines of the plurality of conductive interconnect lines.
Chang teaches (e.g. figs. 1A and 1B) the general concept of metallization lines and their use to gradually increase in size as metallization layers get further from the semiconductor device so that the signal lines can be large enough to interface with external connections. Chang further teaches a second ILD layer (ILD layer provided between each metallization layers M2, M3, M4, M5, M6, M7; hereinafter “2ILD”) above the ILD layer (IL of Kornachuk); and a second plurality of conductive interconnect lines (110 of metallization level M5) in and spaced apart by the second ILD layer (2ILD), each of the second plurality of conductive interconnect lines (110) having a width greater than a greatest width of the first, second, third, fourth, fifth and sixth interconnect lines (A1, B2, A3, C4 of Kornachuk and A5, B6 of Kornachuk in view of Smayling) of the plurality of conductive interconnect lines (CIL of Kornachuk).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the higher metallization lines as taught by Chang in the device of Kornachuk in view of Smayling in order to have the predictable results of using known fan-out interconnection structures to increase metallization line widths and pitches so that the semiconductor device can make external connections and be able to be packaged into a device.
Kornachuk in view of Smayling and Chang is silent as to explicitly teaching each of the first plurality of conductive interconnect lines including a first conductive barrier layer having a first barrier composition, and each of the first plurality of conductive interconnect lines including a first conductive fill having a first fill composition, and each of the second plurality of conductive interconnect lines including a second conductive barrier layer having a second barrier composition, the second barrier composition of the second conductive barrier layer different than the first barrier composition of the first conductive barrier layer, wherein one of the first barrier composition or the second barrier composition includes an outer layer and an inner layer, one of the outer layer or inner layer having a first metal species not included in the other one of the outer layer or inner layer, and the other one of the outer layer or inner layer having a second metal species not included in the one of the outer layer or inner layer , and each of the second plurality of conductive interconnect lines having a second conductive fill having a second fill composition, the second fill composition of the second conductive fill different than the first fill composition of the first conductive fill.
Himeno teaches (e.g. fig. 1) each of the first plurality of conductive interconnect lines (103) including a first conductive barrier layer (102) having a first barrier composition (first barrier metal layer 102 having a stacked structure of tantalum nitride and tantalum; e.g. paragraph 146), and each of the first plurality of conductive interconnect lines (103) including a first conductive fill having a first fill composition (metal wiring 103 made from a metal other than copper, for example aluminum; e.g. paragraph 105), and each of the second plurality of conductive interconnect lines (119) including a second conductive barrier layer (117) having a second barrier composition (third barrier metal layer 117 made of tantalum nitride; e.g. paragraph 175), the second barrier composition of the second conductive barrier layer (tantalum nitride 117) different than the first barrier composition of the first conductive barrier layer (stacked tantalum nitride and tantalum layers 102), and each of the second plurality of conductive interconnect lines (119) having a second conductive fill having a second fill composition (wiring trench 119 is filled with copper; e.g. paragraph 175), the second fill composition of the second conductive fill (copper) different than the first fill composition of the first conductive fill (aluminum).
Raaijmakers teaches (fig. 13) wherein one of the first barrier composition (WN/TiN bilayer barrier layer 150; e.g. paragraph 101) or the second barrier composition includes an outer layer (WN) and an inner layer (TiN), one of the outer layer or inner layer (TiN) having a first metal species (Ti is not contained in WN) not included in the other one of the outer layer (WN) or inner layer, and the other one of the outer layer (WN) or inner layer having a second metal species (W is not contained in TiN) not included in the one of the outer layer or inner layer (TiN).
It would have been obvious to one of ordinary skill in the art at the time of effective filling, absent unexpected results, to use the barrier metal layers as taught by Himeno and the bilayer barrier layer as taught by Raaijmakers in the device of Kornachuk in view of Smayling and Chang in order to have the predictable result of using the barrier metal layers such that the device lifetime can be improved by preventing diffusion of impurities into the interconnect lines as well as preventing metallic atoms from diffusion into the surrounding ILD layers, and in order to have the predictable result of using a bilayer barrier layer more capable of preventing ion diffusion, respectively.
Re claim 5: Kornachuk teaches the integrated circuit structure wherein a pitch (twice the distance labeled P1 in fig. 10C) between the first interconnect line (A1) and the third interconnect line (A3) is the same as a pitch (twice the distance labeled P1 in fig. 10C) between the second interconnect line (B2) and the fourth interconnect line (C4).
Re claim 11: Kornachuk teaches (e.g. fig. 10C and labeled fig. 10C above) a computing device, comprising: integrated circuit structure, comprising: an inter-layer dielectric (ILD) layer (dielectric materials insulate patterned conductive layers from each other; e.g. paragraph 132; hereinafter “IL”) above a substrate (multi-level structures defined on a silicon substrate; e.g. paragraph 132); and a first plurality of conductive interconnect lines (1061, 1030, 1060, 1020 as shown in fig. 10C; hereinafter “CIL”) in and spaced apart by the ILD layer (IL), the first plurality of conductive interconnect lines (CIL) comprising: a first interconnect line (top-most 1060 as shown in labeled fig. 10C and labeled as “A1”) having a width (SRW); a second interconnect line (top-most 1030 as shown in labeled fig. 10C and labeled as “B2”) immediately adjacent the first interconnect line (A1), the second interconnect line (B2) having a width (W2) different than the width (SRW) of the first interconnect line (A1); a third interconnect line (1061 as shown in fig. 10C and labeled as “A3”) immediately adjacent the second interconnect line (B2), the third interconnect line (A3) having a width (SRW) the same as the width (SRW) of the first interconnect line (A1); and a fourth interconnect line (1024 as shown in labeled fig. 10C and labeled as “C4”) immediately adjacent the third interconnect line (A3), the fourth interconnect line (C4) having a width (W1) different than the width of the first interconnect line (A1), and the width (W1) of the fourth interconnect line (C4) different than the width (W2) of the second interconnect line (B2).
Kornachuk is silent as to explicitly teaching a fifth interconnect line immediately adjacent the fourth interconnect line, the fifth interconnect line having a width the same as the width of the first interconnect line; and a sixth interconnect line immediately adjacent the fifth interconnect line, the sixth interconnect line having a width the same as the width of the second interconnect line; a second ILD layer above the ILD layer; and a second plurality of conductive interconnect lines in and spaced apart by the second ILD layer, each of the second plurality of conductive interconnect lines having a width greater than a greatest width of the first, second, third, fourth, fifth and sixth interconnect lines of the plurality of conductive interconnect lines.
Smayling teaches, as shown in figs. 5A-5F, that sub-layouts can be formed such that they are combined to generate a desired sequence of M2 level layouts 505A, 505B, for example, combining cell variant 501A and cell variant 501B, as chosen in figs. 5D, 5E, to have alternating M2 layers 505A, 505B (which maintains an ABAB-ABAB pattern) and alternating lines 503A, 503B (which maintains an ABAB pattern by combining ABA-BAB cells). This concept can be applied to the structure of fig. 10C of Kornachuk by repeating 1061, 1030, 1060, and 1020, which when repeating would have a structure similar to 1060, 1061 be immediately adjacent to 1020 as shown in labeled fig. 10C above, these additional repeating element will be referred to as labeled elements “A5” and “B6”.
Therefore Kornachuk in view of Smayling teaches a fifth interconnect line (A5 of Kornachuk) immediately adjacent the fourth interconnect line (C4 of Kornachuk), the fifth interconnect line (A5) having a width (SRW) the same as the width (SRW) of the first interconnect line (A1); and a sixth interconnect line (B6 of Kornachuk) immediately adjacent the fifth interconnect line (A5 of Kornachuk), the sixth interconnect line (B6 of Kornachuk) having a width (W2) the same as the width (W2) of the second interconnect line (B2 of Kornachuk).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the known method of repeating metallization lines in predetermined layout patterns to achieve a desired layout as taught by Smayling in the device of Kornachuk in order to have the predictable result of using a known method of repeating metallization structures since in semiconductor device fabrication, these structures are not made in a one at a time sequence but rather plural identical structures are formed across an entire wafer and these plurality of these elements are made.
Kornachuk in view of Smayling is silent as to explicitly teaching a second ILD layer above the ILD layer; and a second plurality of conductive interconnect lines in and spaced apart by the second ILD layer, each of the second plurality of conductive interconnect lines having a width greater than a greatest width of the first, second, third, fourth, fifth and sixth interconnect lines of the plurality of conductive interconnect lines.
Chang teaches (e.g. figs. 1A and 1B) the general concept of metallization lines and their use to gradually increase in size as metallization layers get further from the semiconductor device so that the signal lines can be large enough to interface with external connections. Chang further teaches a second ILD layer (ILD layer provided between each metallization layers M2, M3, M4, M5, M6, M7; hereinafter “2ILD”) above the ILD layer (IL of Kornachuk); and a second plurality of conductive interconnect lines (110 of metallization level M5) in and spaced apart by the second ILD layer (2ILD), each of the second plurality of conductive interconnect lines (110) having a width greater than a greatest width of the first, second, third, fourth, fifth and sixth interconnect lines (A1, B2, A3, C4 of Kornachuk and A5, B6 of Kornachuk in view of Smayling) of the plurality of conductive interconnect lines (CIL of Kornachuk).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the higher metallization lines as taught by Chang in the device of Kornachuk in view of Smayling in order to have the predictable results of using known fan-out interconnection structures to increase metallization line widths and pitches so that the semiconductor device can make external connections and be able to be packaged into a device.
Kornachuk in view of Smayling and Chang is silent as to explicitly teaching each of the first plurality of conductive interconnect lines including a first conductive barrier layer having a first composition, and each of the first plurality of conductive interconnect lines including a first conductive fill having a first composition, and each of the second plurality of conductive interconnect lines including a second conductive barrier layer having a second composition, the second composition of the second conductive barrier layer different than the first barrier composition of the first conductive barrier layer, wherein one of the first barrier composition or the second barrier composition includes an outer layer and an inner layer, one of the outer layer or inner layer having a first metal species not included in the other one of the outer layer or inner layer, and the other one of the outer layer or inner layer having a second metal species not included in the one of the outer layer or inner layer, and each of the second plurality of conductive interconnect lines having a second conductive fill having a second composition, the second composition of the second conductive fill different than the first composition of the first conductive fill.
Himeno teaches (e.g. fig. 1) each of the first plurality of conductive interconnect lines (103) including a first conductive barrier layer (102) having a first barrier composition (first barrier metal layer 102 having a stacked structure of tantalum nitride and tantalum; e.g. paragraph 146), and each of the first plurality of conductive interconnect lines (103) including a first conductive fill having a first fill composition (metal wiring 103 made from a metal other than copper, for example aluminum; e.g. paragraph 105), and each of the second plurality of conductive interconnect lines (119) including a second conductive barrier layer (117) having a second barrier composition (third barrier metal layer 117 made of tantalum nitride; e.g. paragraph 175), the second barrier composition of the second conductive barrier layer (tantalum nitride 117) different than the first barrier composition of the first conductive barrier layer (stacked tantalum nitride and tantalum layers 102), and each of the second plurality of conductive interconnect lines (119) having a second conductive fill having a second fill composition (wiring trench 119 is filled with copper; e.g. paragraph 175), the second fill composition of the second conductive fill (copper) different than the first fill composition of the first conductive fill (aluminum).
Raaijmakers teaches (fig. 13) wherein one of the first barrier composition (WN/TiN bilayer barrier layer 150; e.g. paragraph 101) or the second barrier composition includes an outer layer (WN) and an inner layer (TiN), one of the outer layer or inner layer (TiN) having a first metal species (Ti is not contained in WN) not included in the other one of the outer layer (WN) or inner layer, and the other one of the outer layer (WN) or inner layer having a second metal species (W is not contained in TiN) not included in the one of the outer layer or inner layer (TiN).
It would have been obvious to one of ordinary skill in the art at the time of effective filling, absent unexpected results, to use the barrier metal layers as taught by Himeno and the bilayer barrier layer as taught by Raaijmakers in the device of Kornachuk in view of Smayling and Chang in order to have the predictable result of using the barrier metal layers such that the device lifetime can be improved by preventing diffusion of impurities into the interconnect lines as well as preventing metallic atoms from diffusion into the surrounding ILD layers, and in order to have the predictable result of using a bilayer barrier layer more capable of preventing ion diffusion, respectively.
Re claims 12-19: It is readily apparent to one of ordinary skill in the art that electrical computing devices such as smart phones are widely used devices which require memory structures on a board to operate, these devices further include communication chips, camera/imager chips, a battery, antennas, and processors attached to the board.
Further, Kornachuk in view of Smayling and Chang teaches a computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure, a memory structure, a communication chip, a camera, a battery, an antenna, a packaged integrated circuit die, a processor, communication chip, and DSP, or a computer (paragraphs 45-47 and fig. 8 of Chang discusses memory integrated with processors, i/o devices (keyboard/mouse), displays to create a computing system).
Re claim 21: Kornachuk teaches the computing device, wherein a pitch (twice the distance labeled P1 in fig. 10C) between the first interconnect line (A1) and the third interconnect line (A3) is the same as a pitch (twice the distance labeled P1 in fig. 10C) between the second interconnect line (B2) and the fourth interconnect line (C4).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached on M-F, 8:30AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached on 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898