DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is responsive to Applicant’s amendment filed on 04/27/2026. Claims 1-2, 4-9, 11-15, 17-20, and 22-23 are pending. The amendments have overcome the specification objection, claims objection, and rejection under 35 U.S.C. 112(a) as set forth in previous office action.
Response to Arguments
In responsive to Applicant’s argument for rejection under 35 U.S.C. 101 on page 10-11, “Here, the Office Action appears to rely on Figures 3-4 of Applicant’s Specification, … The presence of numerical representations or bit-level operations in Applicant's Specification does not mean that the claim itself recites a mathematical concept. Rather, the question is whether the claim language defines a mathematical formula, equation, or calculation. Amended claim 1 does not recite any such formula, equation, or calculation. Instead, amended claim 1 recites operations performed by GPU circuitry, including moving a portion of a first floating point value into least significant portions of a second floating point value, extracting the least significant portions of the second floating point value to obtain a binary representation of a corresponding integer value, providing the corresponding integer value to integer hardware of the GPU configured to perform integer matrix multiply accumulate (IMMA) operations, and causing that hardware to perform IMMA operations using the corresponding integer value.”
Examiner respectfully disagrees because the claim recites mathematical concepts, such mathematical calculations, and MPEP 2106.04(a)(2)(C) recites “A claim that recites a mathematical calculation, when the claim is given its broadest reasonable interpretation in light of the specification, will be considered as falling within the "mathematical concepts" grouping”. Thus, under broadest reasonable interpretation in light of the specification, the step of moving a portion of a first floating point value into least significant portions of a second floating point values, such moving operation is merely performing bit shifting by adding number as illustrated in figures 3-4. Furthermore, the claim also recites step of performing integer operations, such as IMMA, which is also a mathematical operations of multiply and accumulate. Therefore, the claim recites limitations that fall under mathematical concept, and Examiner did not rely on figures 3-4 of the specification to describe operations of floating point values, but Examiner used figures 3-4 to better illustrates how the claim as recited and interpreted under BRI in light of the specification fall under the mathematical concept. The additional elements, such as GPU circuitry and integer hardware of the GPU are merely recited at a high level of generality that amounts to no more than mere instructions to apply the judicial exception using computer component (see MPEP 2106.05(f)).
Applicant further asserted on page 12, “Here, Applicant's Specification describes how the claimed GPU circuitry enables integer hardware to operate directly on values derived from floating-point representations without performing separate floating-point-to-integer conversion operations. A person of ordinary skill in the art would recognize that this configuration improves GPU processing efficiency by reducing the computational overhead associated with such conversion operations.”
Examiner respectfully disagrees because any arguably improvements, such as enabling integer hardware to operate directly on values derived from floating point representation without performing separate floating point to integer conversion operations, are a direct consequence of performing the mathematical operations of moving/shifting and extract bit to approximate integer value as recited in the claim or described in figure 3. MPEP 2106.05(a) states “It is important to note, the judicial exception alone cannot provide the improvement. The improvement can be provided by one or more additional elements.” As explained above and in [0050-0051], any arguably improvements are the result of performing mathematical operation to represent integer value without having to performing conversion, such as adding 2^23 to shift or move portions of the first floating point value to the least significant portion of second floating point number and use the last 8 bit to represent an integer number without actually conversion floating point and integer is merely abstract idea.
Applicant further asserted on page 12, “Consistent with the guidance of MPEP § 2106.04(d)(1), amended claim 1 recites a specific technological improvement to the manner in which a GPU processes numerical data, rather than merely invoking generic computer components.”
Examiner respectfully disagrees because the amended claim 1 still recites the additional elements at a high level of generality, e.g., computer component performing computer function of processing data, which amounts to no more than mere instructions to apply the judicial exception using computer component. Thus, such recitation fails to integrate the judicial exception into a practical application under step 2A prong two or provide significantly more. Moreover, as explained above, any arguably improvement is a result of performing the mathematical concept as recited in the claims.
Applicant further asserted on page 13, “Applicant submits that claim 1 is analogous to the claims found patent-eligible in Enfish, LLC V. Microsoft Corp., 822 F.3d 1327, 1339 (Fed. Cir. 2016). In Enfish, the Federal Circuit held that claims directed to a specific improvement in the way computers store and process information were not abstract because they improved the functioning of the computer itself. Similarly, amended claim 1 recites a specific technique for preparing data derived from floating-point representations so that it can be processed by integer hardware of the GPU. In particular, the claim recites extracting least significant portions of a floating-point value to generate a binary representation of a corresponding integer value and providing that value to integer hardware configured to perform IMMA operations. Together, these elements define the claimed improvement. Like the self-referential table in Enfish, which improved how a computer stores and retrieves data, the claimed elements improve how numerical data is represented and processed within the GPU to enable more efficient execution of matrix operations. Furthermore, the GPU circuitry, the API, and integer hardware are not generic extras, rather, they are the technological environment in which the improvement occurs. See Enfish, 822 F.3d at 1335-36. In particular, the combination of the elements recited in amended claim 1 are integrated into a process that reduces the computational resources necessary to perform IMMA operations using floating point values and/or integer values. This is performed in a way where additional hardware to convert floating point values to integer values becomes unnecessary. Specifically, amended claim 1 recites extracting least significant portions of a floating-point value to generate a binary representation of a corresponding integer value and providing that value to integer hardware of the GPU configured to perform integer matrix multiply accumulate (IMMA) operations. As described at least at paragraph [0051] of Applicant's Specification, avoiding conversion operations between data types reduces computational overhead and improves processing efficiency. Thus, amended claim 1 is directed to an improvement to computing technology, specifically improving the efficiency of GPU execution by enabling integer hardware to process values derived from floating-point representations without performing costly conversion operations.”
Examiner respectfully disagrees because the claimed invention is not analogous to Enfish since the claims in Enfish were specifically directed to a self-referential table for a computer database that functioned differently than conventional database structures, but the claimed invention is directed to a technique that reduces mathematical conversions for different data type, wherein mathematical operations are performed by representing numbers in a way that removes a need to convert between data type as described in [0051]. In other words, the specific technique of the claimed invention is to represent floating point number as integer number without performing conversion, such new technique is characterized as an abstract idea and MPEP 2106.04(I) “The Supreme Court’s decisions make it clear that judicial exceptions need not be old or long-prevalent, and that even newly discovered or novel judicial exceptions are still exceptions” and MPEP 2106.05(I) “a claim for a new abstract idea is still an abstract idea”. The additional elements, such as the GPU circuitry, the API, and integer hardware are merely recited at a high level of generality that amounts to no more than mere instructions to apply the judicial exception using computer components. Moreover, as explained above, any arguably improvements are a direct consequence of performing this new technique of representing floating point value as integer value by performing the steps of bit moving and extracting, which are characterized as abstract idea.
Applicant further asserted on page 14, “For example, amended claim 1 recites a specific, technical arrangement of GPU circuitry and integer hardware that goes far beyond generic computing. In particular, claim 1 recites moving a portion of a floating-point value into least significant portions of another floating-point value, extracting the least significant portions of that value to produce a binary representation of a corresponding integer value, providing the corresponding integer value to integer hardware of the GPU configured to perform integer matrix multiply accumulate (IMMA) operations, and causing the integer hardware to perform IMMA operations using the corresponding integer value. These elements do not merely instruct a computer to apply a mathematical concept. Rather, they define a concrete GPU-implemented processing technique in which values derived from floating-point representations are provided to integer hardware of the GPU for execution of IMMA operations independent of using additional hardware to convert the floating-point value to an integer value. As described in Applicant's Specification at least at [0051], avoiding such conversion operations reduces computational overhead and improves processing efficiency. Accordingly, the ordered combination of elements recited in claim 1 amounts to significantly more than any alleged abstract idea.”
Examiner respectfully disagrees because the claim does not recite a specific technical arrangement of GPU circuitry and integer hardware that goes far beyond generic computing, but the claim merely recite those components at a high level of generality, that are simply added to perform the mathematical operation. MPEP 2106.05(f) recites “simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more.” Moreover, as explained above, any arguably improvements, such as avoiding conversion operations reduces computational overhead and improve processing efficiency, are a direct consequence of performing this new technique of representing floating point value as integer value by performing the steps of bit moving and extracting, which are characterized as abstract idea.
Claim Objections
Claim 1-2, 4-9, 11-15, 17-20, and 22-23 are objected to because of the following informalities:
Claim 1 line 15; claim 8 line 16-17; claim 14 line 16-17; claim 20 line 13-14 “one or more IMMA operations” should be “the IMMA operations” as antecedently recited.
Dependent claims are also objected for the inheriting the same deficiencies in which claims they depend on.
Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 1-2, 4-9, 11-15, 17-20, and 22-23 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding claim 1, recites an apparatus
Under Prong One of Step 2A of the USPTO current eligibility guidance (MPEP 2106). The claim recites moving a portion of a first floating point value into least significant portions of a second floating point value, wherein the first floating point number is within a range that includes both negative and positive values; extract the least significant portions of the second floating point value to result in a binary representation of a corresponding integer value; perform one or more integer matrix multiply accumulate (IMMA) operations using the corresponding integer value of the first floating point value identified from the least significant portions of the second floating point value. Such limitation covers mathematical calculations, relationship, and/or formula (see at least figures 3-4 [0060] discloses one embodiment of adding 2^23 to the original number to move/shift portion of mantissa to the least significant portions of result floating point value, wherein extract the last 8 bit of the shifted number represented as integer, and use the integer in integer operation such as matrix multiply accumulate operation. Thus figures 3-4 illustrates the step of moving, extracting and using the floating point value as integer number based on shifting or moving the bit, and floating point numbers includes a sign bit, thus each floating point number represents a range of value includes both negative and positive number). Therefore, the claim include limitations that fall within the “Mathematical Concepts” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Under Prong Two of Step 2A, this judicial exception is not integrated into a practical application. The claim additionally recites a GPU comprises circuitry, in response to an API call, integer hardware. However, such additional elements are recited at a high level of generality, i.e., as computer components to perform computer functions such as processing data and performing API calls function to perform abstract idea. The claim further recites “independent of using additional hardware to convert the first floating point value to the corresponding integer value”, such limitation is at most considered as a result of performing the abstract idea of moving/shifting and extract the portions of second floating point value to represent integer value without performing conversion. Moreover, the claim recites a step of providing the corresponding integer to integer hardware of the GPU, but such limitation is at most considered as insignificant extra solution activity, such as mere data gathering. Such element fails to provide a meaningful limitation on the claim invention, and amount to no more than mere instructions to apply the exception using computer elements. Thus, the claim is directed to an abstract idea.
Under Step 2B, the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed previously with respect to the step 2A prong two, the additional elements in the claim amount to no more mere instructions to apply the exception. Furthermore, the step of providing data to the integer hardware is considered as insignificant extra solution activity under step 2A prong two and determined to be well-understood, routine and conventional activity under step 2B (see MPEP 2106.05(d)(II)(i). Receiving or transmitting data over a network). Thus, the claim does not provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim in addition to (beyond) the judicial exception, and fails to ensure the claim as a whole amount to significantly more than the judicial exception itself. Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 2 further recites moving the portion of the first floating point value is performed using a plurality of GPU instructions. The step of moving the portion of the floating point value covers the mathematical concept as explained above. The limitation using a plurality of GPU instructions is recited at a high level of generality, e.g., GPU instructions to be executed on a GPU, such element fails to provide a meaningful limitation on the claim invention, and amount to no more than mere instructions to apply the exception using computer elements. Therefore, the claim recite additional element that fails to integrate the judicial exception into a practical application under step 2A prong two or provide an inventive concept under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 4 further recites the least significant portions are associated with a plurality of mantissa bits of the second floating point value, Such limitation covers mathematical calculations, relationship, and/or formula (see at least figure 3-4 illustrate the last 8 bits of the shifted mantissa represent the corresponding integer). The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 5 further recites the step of determining a type of data comprising the first floating point value, such limitation covers mathematical calculations, relationship, and/or formula (such as determining the data type to be operated on). The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 6 further recites generate a third floating point value based, at least in part, on the corresponding integer value such limitation covers mathematical calculations, relationship, and/or formula (generating floating point value based on the corresponding integer value, which are the portion of bits being shifted). The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 7 further recites adding at least one mantissa bit to values stored in the least significant portions after moving the portion of the first floating point value, such limitation covers the mathematical calculations, relationship, and/or formula (adding one mantissa bit to the value). The claim does not recite any additional element that would integrate the judicial exception into a practical application under step 2A or provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim in addition to (beyond) the judicial exception, and fails to ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claims 8-9 and 11-13 recite apparatus claim having similar limitation as recited in the apparatus claims 1-2 and 5-7. Thus, they are rejected for the same reasons.
Claims 14-15, 17, and 19 recite product claims having limitations that are similar to apparatus claim 1-2, 7, 6, respectively. Thus, they are rejected for the same reasons. Claim 14 further recites a non-transitory machine readable medium having stored thereon a set of instructions, such additional elements are recited at a high level of generality, e.g., computer component performing computer function of storing. Such limitation fails to provide a meaningful limitation on the claimed invention, and amount to no more than mere instructions to apply the exception using a computer component, and mere instructions to apply an exception using computer component fails to integrate the claim into a practical application under step 2A prong, and cannot provide an inventive concept under step 2B. Accordingly, the claims are not patent-eligible under 35 U.S.C. 101.
Claim 18 further recites wherein the first floating point value is identified in a binary format, such limitation covers the mathematical calculations, relationship, and/or formula (mere describes floating point value as binary format of 0 and 1 as illustrated in figure 3). The claim does not recite any additional element that would integrate the judicial exception into a practical application under step 2A or provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim in addition to (beyond) the judicial exception, and fails to ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claims 20 and 22-23 recite method claims that would be practiced by the apparatus claims 1, 6 and 5, respectively. Thus, they are rejected for the same reasons.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-2, 4-5, 7-9, 11-12, 14-15, 17-18, 20, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Alsup – US 20190384600 in view of Hecker NPL – Let’s get to the (floating) point, Markovic - US 20080005731, and Kaul - US 20210124579.
Regarding claim 1, Alsup teaches a graphics processing unit (GPU) (Alsup, figure 1 a GPU 100) comprising circuitry to convert a floating point value to an integer value, provide the integer value to an integer hardware of the GPU to perform integer operations; cause the integer hardware to perform one or more integer operations using the integer value (Alsup figure 1 illustrates GPU comprising at least one processing engine PE [i.e., circuitry], wherein figure 5 illustrates each PE includes a format conversion unit (FCU) 510 to convert value from a floating point format [i.e., a floating point value] to an integer format [i.e., an integer value] as described in [0068-0089] and also includes an integer processing unit (IPU) 530 for performing integer operations [0063] based on the converted integer value. Thus, the converted integer value is provided to the IPU to perform integer operations)
Alsup does not teach the step of moving a portion of a first floating point value into a least significant portions of a second floating point value; wherein the first floating point value is within a range that includes both negative and positive values extract the least significant portions of the second floating point value; and use a corresponding integer value of the first floating point value generated from the least significant portions of the second floating point value. However, Hecker teaches move a portion of a first floating point value into a least significant portions of a second floating point value, wherein the first floating point value is within a range that includes both negative and positive values; extract the least significant portions of the second floating point value to result in a binary representation of a corresponding integer value independent of using additional hardware to convert the first floating point value to the corresponding integer value; and use the corresponding integer value of the first floating point value identified from the least significant portions of the second floating point value (Hecker page 22 section Conversions middle column describes a method to convert floating point into integer using shifting/moving bit. Figure 2 illustrates a floating point value 8.75 [i.e., a first floating point value], which includes the integer part is the implicit 1 bit and the three leading 0s in the mantissa [i.e., a portion of the first floating point value]. The following 11 in the mantissa is .75 in binary fractional bits, just waiting to be turned into a fixed-point number, as illustrated in figure 2, the floating point number has a sign bit, thus, each floating point number represent a range of value [i.e., a range] that includes both negative and positive value. Page 22 middle column describes when adding 2^23 to 8.75, the mantissa is shifted down 20 bit, leaving just 1000 for the 8 (because we shifted .75 off the end of the single precision mantissa). Thus, when adding 2^23 to 8.75, the 8 integer part [i.e., a portion of a first floating point value] is shifted/moved down 20 bit, in which the 1000 to represent 8 is shifted to the last 4 bit of the shifted floating point value [i.e., a least significant portions of a second floating point value]. Therefore, the last 4 bit 1000 is extracted to be used for integer representation (e.g., value 8), which is a corresponding integer value of the 8.75 generated from the last 4 bit of the shifted value [i.e., the least significant portions of the second floating point value]. Accordingly, using this shifting technique or adding 2^23, a floating point value can be represented as an integer independent of using additional hardware to convert the first floating point value to the corresponding integer value)
It would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to substitute method of converting data from floating point format to integer format used by the FCU with the method disclosed by Hecker. This modification would have been obvious because both references disclose the step of converting floating point to integer data. The claim would have been obvious because the substitution of one known element for another would have yielded predictable results to one of ordinary skill in the art, converting data format. Furthermore, Hecker’s method of converting is merely shifting the bit representation of a floating point number until it is the same as an integer bit representation. Thus, Hecker’s method avoid the mathematical expensive computation process for conversion between data types.
The combined system of Alsup in view of Hecker does not teach an application programming interface (API) call
However, Markovic discloses an application programming interfaces (API) call to convert of a floating point value into an integer (Markovic figure 2 illustrates a system of GPU having compiler module 220, memory 250, state management system 210, application 260, runtime module 240 to perform an API comprise operation that comprises a run-time conversion, wherein the run-time conversion comprises a conversion from floating point value to integer value as described in claims 10-14, [0044] and [0048])
It would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to modify the combined system of Alsup in view of Hecker to perform the floating point to integer conversion in response to an API call as taught by Markovic. This modification would have been obvious because the references disclose system to perform conversion of floating point value to integer value using GPU, and incorporating the API of Markovic into the GPU of combined system of Alsup in view of Hecker would permit the application to reuse the existing floating point conversion circuitry (e.g., FCU) instead of implementing separate software conversion routines, thereby avoiding redundant implementation.
As modified, the combined system of Alsup in view of Hecker and Markovic discloses a GPU having circuitry to convert floating point value to integer value, in response to an API call, by moving portion of mantissa of the floating point value into the least significant portion of the shifted value and extract the least significant portion [e.g., 1000] to represent the corresponding integer value [e.g., 8], provide the corresponding integer value to the hardware integer of the GPU to perform integer operations.
However, the combined system of Alsup in view of Hecker and Markovic does not teach perform integer matrix multiply accumulate (IMMA) operations. Kaul teaches performing integer matrix multiple accumulate (IMMA) operations (Kaul, [0340] discloses a system having parallel multiplication circuit and accumulation circuit to multiply and accumulate integer operands in response to a second FMA instruction to perform integer multiplication and integer accumulation (IMMA operations)
It would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to modify the IPU of the combined system of Alsup in view of Hecker and Markovic to include a multiply and accumulate circuit to perform integer multiply accumulate operations as disclosed in [0340] of Kaul. This modification would have been obvious because the system of Alsup in view of Hecker and Markovic discloses system and method to convert floating point value to integer value and having hardware to perform integer operation, and Kaul describes a system to operate on integer values. Furthermore, having the multiply accumulate circuit to perform integer operations in parallel allows the system to calculate operation faster as GPU is known for handling parallel operations.
Regarding claim 2, the combined system of Alsup in view of Hecker, Markovic, and Kaul teaches the GPU of claim 1, wherein moving the portion of the floating point value is performed using a plurality of GPU instructions (Alsup, [0065] each PE includes a FCU 510 configured to receive instructions and conversion information, thus the FCU performs conversion the format using a plurality of GPU instructions).
Regarding claim 4, the combined system of Alsup in view of Hecke, Markovic, and Kaul teaches the GPU of claim 1, wherein the least significant portions are associated with a plurality of mantissa bits of the second floating point value (as modified, Hecker page 22 middle column describes last 4 bit 1000 [i.e., the least significant portions] of the mantissa of the shifted value [i.e., a plurality of mantissa bits of the second floating point value] represents the integer value 8)
Regarding claim 5, the combined system of Alsup in view of Hecker, Markovic, and Kaul teaches the GPU of claim 1, wherein the circuitry is to determine a type of data comprising the first floating point value (Alsup [0065] the format conversion unit 510 determines whether the source format is floating point, [0068-0089] disclose conversion from floating point to integer. Thus, the processing engine PE is to determine a type of data comprising floating point value as source).
Regarding claim 7, the combined system of Alsup in view of Hecker, Markovic, and Kaul teaches the GPU of claim 1, wherein the circuitry is to add at least one mantissa bit to values stored in the least significant portions after moving the portion of the first floating point value (as modified, Hecker page 22 section Conversions middle column describes adding 2^23 to 8.75 to shift down 20 bit, leaving 1000 to represent the value 8, and see figure 2 illustrates 23 mantissa bits of 8.75, as 000 1100 0000 0000 0000 0000, thus after adding 2^23 to 8.75, which results in a right shift of 20 bit, the implicit bit or hidden bit of 1 [i.e., at least one mantissa bit] becomes explicit bit, which is added into values of the mantissa and result in 1000 to represent the value 8).
Claims 8-9, 11-12, 20, and 23 recite apparatus, product, and method claims having similar limitations as the apparatus claims 1-2, 7, and 5. Thus, they are rejected for the same reasons.
Claims 14-15, and 17 recites product claims having similar limitations as the apparatus claims 1-2, and 7. Thus, they are rejected for the same reasons. Furthermore, claim 14 further recites a non-transitory machine-readable medium having stored thereon a set of instructions (Alsup [0045] figure 1 a memory 140 [i.e., a non-transitory machine-readable medium] stores instructions [i.e., a set of instructions] for the processing engine to operate).
Regarding claim 18, the combined system of Alsup in view of Hecker, Markovic, and Kaul teaches the non-transitory machine-readable medium of claim 14, wherein the first floating point value is identified in an binary format (as modified Hecker page 22 figure 2 illustrates 8.75 [i.e., the first floating point value] is identified in a binary format).
Claims 6, 13, 19, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Alsup in view of Hecker, Markovic, and Kaul as applied to claims 1, 8, 14, and 20 above, and further in view of Kim - US 20200167632.
Regarding claim 6, the combined system of Alsup in view of Hecker, Markovic, and Kaul teaches the GPU of claim 1, including the circuitry to perform conversion between integer and floating point format (Alsup figure 5), but the combined system of Alsup in view of Hecker, Markovic, and Kaul does not teach generate a third floating point value based, at least in part, on the corresponding integer value. However, Kim teaches a system and method to generate a third floating point value based, at least in part, on a converted integer value (Kim figure 1 illustrates data converter 20, and figure 4 illustrates a method performed by the neural network device 120 of figure 1, wherein the method includes receiving floating point data, convert to integer data, perform integer operation, then convert the integer type output to floating point output data [i.e., generate a third floating point value based on a converted integer value])
It would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to modify the combined system of Alsup in view of Hecker, Markovic, and Kaul to perform the step of converting data back to floating point format as disclosed in Kim. This modification would have been obvious because Alsup discloses processing engine having floating point unit for performing floating point operation, integer unit for performing integer operation and an format conversion unit to convert data between integer and floating point format. Thus, the combined system of Alsup in view of Hecker, Markovic, and Kaul includes all the components to operate between floating point and integer operations. Furthermore, converting the data back to original format allow the system to operate on subsequent operation that needed to be performed in floating point format in some applications, such as neural network as disclosed in figure 4 of Kim, which increases system flexibility to operate between floating point and integer operations
Claims 13, 19, and 22 recite claims having similar limitations as claim 6. Thus, they are rejected for the same reasons.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/HUY DUONG/Examiner, Art Unit 2182 (571)272-2764
/ANDREW CALDWELL/ Supervisory Patent Examiner, Art Unit 2182
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