DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/29/2025 has been entered.
Response to Amendment
This Office Action is responsive to Applicant’s amendment filed on 12/29/2025. Claims 1-2, 4—9, 11-15, 17-20, and 22-23 are pending. The amendment have overcome the claims objection and rejection under 35 U.S.C. 103 as set forth in previous office action. However, a new ground of rejection has been made.
Response to Arguments
Applicant’s arguments, see Remarks page 9-10, filed 12/29/2025, with respect to rejection under 35 U.S.C. 103 have been fully considered and are persuasive. The rejection under 35 U.S.C. 103 has been withdrawn because Hecker does not teach or suggest the limitation of “move a portion of a first floating point value into least significant portions of a second floating point value irrespective of a sign of the first floating point value” since Hecker mentioned on page 22 that “this trick works for positive numbers, but if you try to convert a negative number it will fail”.
In responsive to Applicant’s argument for rejection under 35 U.S.C. 101 on Remarks 12/29/2025 page 8, “the claims, when read as a whole, do not simply recite mathematical concepts. Applicant submits that claim 1 is analogous to Example 41 of the 2019 USPTO Subject Matter Eligibility Guidance, in which a claim was found patent eligible because "the combination of additional elements. integrates the exception into a practical application." As in Example 41, claim 1 recites specific GPU circuitry that performs the mathematical operations using integer hardware and IMMA instructions in a manner that directly improves computational efficiency for processing floating point values, rather than merely reciting the mathematical concepts in the abstract. In particular, the combination of the elements recited in amended claim 1 are integrated into a process that reduces the computational resources necessary to perform IMMA operations using floating point values and/or integer values. This is performed in a way where "additional hardware" to convert floating point values to integer values become unnecessary. Accordingly, any alleged abstract idea is integrated into a practical application by the claimed GPU circuitry, and claim 1 is therefore not directed to a judicial exception under Step 2A of the USPTO Guidance.”
Examiner respectfully disagrees because Example 41 is not similar to the instant claim as claim of Example 41 recites a combination of additional elements (receiving the plaintext word signal at the first computer terminal, transforming the plaintext word signal to one or message block word signals MA, and transmitting the encoded ciphertext word signal CA to the second computer terminal over a communication channel), wherein the combination of additional elements use the mathematical formulas and calculations in a specific manner that sufficiently limits the use of the mathematical concepts to the practical application of transmitting the ciphertext word signal to a computer terminal over a communication channel. However, the additional elements recited in the instant claim are merely recited at a high level of generality, e.g., using computer components (e.g., GPU comprising circuitry, integer hardware) to perform computer functions (moving/shifting portion of data to least significant portions, extracting bits, performing integer matrix multiply accumulate (IMMA) operations), such additional elements amount no more than mere instructions to apply the exception using computer components (see MPEP 2106.05(f)). Furthermore, the limitation of “independent of using additional hardware to convert the first floating point value to the corresponding integer value” is merely a result of performing the abstract idea, which is moving or shifting the portion of first floating point value to the least significant portions and extract the least significant portions to represent integer value. Thus, by performing the shifting and extracting steps (e.g., the abstract idea), an integer value is approximated without using additional hardware to perform the conversion. Accordingly, it is the result of performing the abstract idea that eliminates the use of additional hardware to perform conversion. Moreover, any arguably improvements, such as computational efficiency and reduces the computational resources necessary, are a direct consequence of performing the mathematical operations of moving/shifting and extract bit to approximate integer value as recited in the claim or described in figure 3. MPEP 2106.05(a) states “It is important to note, the judicial exception alone cannot provide the improvement. The improvement can be provided by one or more additional elements.” As explained above and in [0050-0051], any arguably improvements are the result of performing mathematical operation to represent integer value without having to performing conversion and performing mathematical operation, such as adding 2^23 to shift or move portions of the first floating point value to the least significant portion of second floating point number and use the last 8 bit to represent an integer number without actually conversion floating point and integer is merely abstract idea.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). See the rejection under 35 U.S.C. 112 below.
Claim Objections
Claims 12-13, 17, 19 are objected to because of the following informalities:
Claims 12-13 line 1 and claims 17, 19 line 2 recite “the GPU” should be “the one or more GPUs” as antecedently recited in claims 8 and 14, respectively.
Appropriate correction is required.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-2, 4-9, 11-15, 17-20, and 22-23 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 1, 8, 14, and 20 recite “move a portion of a first floating point value into least significant portions of a second floating point value irrespective of a sign of the first floating point value … extract the least significant portions of the second floating point value to result in a representation of a corresponding integer value”. However, the specification fails to provide sufficient disclosure for such limitation. Figure 2 illustrates a first floating point value as 85.125, which represents for positive value, and figure 3 illustrates an operation that adds 2^23 to 85.125, which moves/shifts portions of the first floating point value into least significant portions of a second floating point value (e.g., last 8 bit of 308). Thus, figures 2-3 illustrate concept of representing an integer value using least significant portions of a modified positive floating point value (e.g., adding 85.125 to 2^23), but the specification fails to describe the negative floating point value would work the same. Applicant further asserted that support for amendment can be found at least in [0049] and [0055]. However, Examiner is unable to find the support for the identified limitation above because [0049] merely describes the concept of shifting of a first floating point value by adding 2^23, and extract a specific byte (last 8 bit) of the added result to approximate an integer representation and use the extracted integer to perform matrix multiply accumulate instruction on the extracted integer, and [0055] merely describes the minimum and maximum values for the floating point number to represent -1040384 <= floating point number <= 1048576, but [0055] does not describe that the operation performed in figure 3 would work for negative floating point value. Thus, the specification fails to describe the step of moving a portion of a first floating point into least significant portions of a second floating point and extract the least significant portions to represent a corresponding integer regardless of the first floating point value being positive or negative. In other words, figure 3 illustrates the step of moving a portion of a first floating point value (e.g., positive 85.125) into least significant portions of a second floating point value by adding 85.125 to 2^23 equals to 8388693.125 in step 306, in which the last 8 bit represents 01010101, which is 85 (e.g., the extracted integer), but the specification fails to provide sufficient disclosure that the same concept would work when the first floating point value is negative. For example, if the number is -85.125, which is represented as 1 10000101 01010100100000000000000, when adds 2^23, the result is 8388522.875, which represents as 0 10010101 11111111111111101010110. Thus, it is clear that a portion of the first floating point number (-85.125) is not moved into least significant portions of a second floating point value to represent the corresponding integer when extracted. Accordingly, the claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Dependent claims are also rejected for inheriting the same deficiencies in which claims they depend on.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 1-2, 4-9, 11-15, 17-20, and 22-23 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding claim 1, recites an apparatus
Under Prong One of Step 2A of the USPTO current eligibility guidance (MPEP 2106). The claim recites moving a portion of a first floating point value into least significant portions of a second floating point value irrespective of a sign of the first floating point value; extract the least significant portions of the second floating point value to result in a representation of a corresponding integer value; perform one or more integer matrix multiply accumulate (IMMA) operations using the corresponding integer value of the first floating point value generated from the least significant portions of the second floating point value. Such limitation covers mathematical calculations, relationship, and/or formula (see at least figures 3-4 [0060] discloses one embodiment of adding 2^23 to the original number to move/shift portion of mantissa to the least significant portions of result floating point value, wherein extract the last 8 bit of the shifted number represented as integer, and use the integer in integer operation such as matrix multiply accumulate operation. Thus figures 3-4 illustrates the step of moving, extracting and using the floating point value as integer number based on shifting or moving the bit). Therefore, the claim include limitations that fall within the “Mathematical Concepts” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Under Prong Two of Step 2A, this judicial exception is not integrated into a practical application. The claim additionally recites a GPU comprises circuitry, in response to an API call, integer hardware. However, such additional elements are recited at a high level of generality, i.e., as computer components to perform computer functions such as processing data and performing API calls function to perform abstract idea. The claim further recites “independent of using additional hardware to convert the first floating point value to the corresponding integer value”, such limitation is at most considered as a result of performing the abstract idea of moving/shifting and extract the portions of second floating point value to represent integer value without performing conversion. Such element fails to provide a meaningful limitation on the claim invention, and amount to no more than mere instructions to apply the exception using generic computer elements. Thus, the claim is directed to an abstract idea.
Under Step 2B, the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed previously with respect to the step 2A prong two, the additional elements in the claim amount to no more mere instructions to apply the exception. Thus, the claim does not provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim in addition to (beyond) the judicial exception, and fails to ensure the claim as a whole amount to significantly more than the judicial exception itself. Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 2 further recites moving the portion of the first floating point value is performed using a plurality of GPU instructions. The step of moving the portion of the floating point value covers the mathematical concept as explained above. The limitation using a plurality of GPU instructions is recited at a high level of generality, e.g., GPU instructions to be executed on a GPU, such element fails to provide a meaningful limitation on the claim invention, and amount to no more than mere instructions to apply the exception using computer elements. Therefore, the claim recite additional element that fails to integrate the judicial exception into a practical application under step 2A prong two or provide an inventive concept under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 4 further recites the least significant portions are associated with a plurality of mantissa bits of the second floating point value, Such limitation covers mathematical calculations, relationship, and/or formula (see at least figure 3-4 illustrate the last 8 bits of the shifted mantissa represent the corresponding integer). The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 5 further recites the step of determining a type of data comprising the first floating point value, such limitation covers mathematical calculations, relationship, and/or formula (such as determining the data type to be operated on). The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 6 further recites generate a third floating point value based, at least in part, on the corresponding integer value such limitation covers mathematical calculations, relationship, and/or formula (generating floating point value based on the corresponding integer value, which are the portion of bits being shifted). The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 7 further recites adding at least one mantissa bit to values stored in the least significant portions after moving the portion of the first floating point value, such limitation covers the mathematical calculations, relationship, and/or formula (adding one mantissa bit to the value). The claim does not recite any additional element that would integrate the judicial exception into a practical application under step 2A or provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim in addition to (beyond) the judicial exception, and fails to ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claims 8-9 and 11-13 recite apparatus claim having similar limitation as recited in the apparatus claims 1-2 and 5-7. Thus, they are rejected for the same reasons.
Claims 14-15, 17, and 19 recite product claims having limitations that are similar to apparatus claim 1-2, 7, 6, respectively. Thus, they are rejected for the same reasons. Claim 14 further recites a non-transitory machine readable medium having stored thereon a set of instructions, such additional elements are recited at a high level of generality, e.g., computer component performing computer function of storing. Such limitation fails to provide a meaningful limitation on the claimed invention, and amount to no more than mere instructions to apply the exception using a computer component, and mere instructions to apply an exception using computer component fails to integrate the claim into a practical application under step 2A prong, and cannot provide an inventive concept under step 2B. Accordingly, the claims are not patent-eligible under 35 U.S.C. 101.
Claim 18 further recites wherein the first floating point value is identified in a binary format, such limitation covers the mathematical calculations, relationship, and/or formula (mere describes floating point value as binary format of 0 and 1 as illustrated in figure 3). The claim does not recite any additional element that would integrate the judicial exception into a practical application under step 2A or provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim in addition to (beyond) the judicial exception, and fails to ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claims 20 and 22-23 recite method claims that would be practiced by the apparatus claims 1, 6 and 5, respectively. Thus, they are rejected for the same reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hecker – NPL let’s get to the (floating) point – page 22 discloses a trick to add 8.75 to 2^23 to shift mantissa of the floating point value 8.75 down 20 bit, leaving just 4 bit to represent the 8 as integer.
Tang – US 20040254973 – discloses a system and method for performing rounding operation that can represent an integer based on adding a constant value S of 2^22+2^23 to a floating point number 7.75 that shift the rounded integer portion into the rightmost bits of the significant as illustrated in figure 2 [0027]. [0028] also describes that the resulting significand contains the integer as a (b-2) bit 2’s complement integer and having a bit to ensure that negative integers do not get renormalized. Thus, Tang discloses the concept of representing positive and negative integer.
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/HUY DUONG/Examiner, Art Unit 2182 (571)272-2764
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182