DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 4-7, 13, 15 and 19 have been amended. Claims 1-13, 15 and 19-24 remain pending and have been examined.
Response to Arguments/Amendments
The previous objections to claims 1 and 19 are withdrawn in view of the claim amendments.
Applicant’s arguments, see p. 12, filed 1/23/2026, with respect to the rejection(s) of claim(s) 6 and 15 under 35 USC § 103, have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of “Neuromorphic computing with multi-memristive synapses” by Boybat et al.
Applicant's remaining arguments filed 1/23/2026 have been fully considered but they are not persuasive.
On p. 11 of the remarks filed 1/23/2026, Applicant argues that the rejection of claim 19 under 35 USC § 112(b) has been addressed. However, the issue remains as stated in the previous rejection. The rejection is maintained.
On pp. 11-12 of the remarks, Applicant argues that the cited art of record Das in view of Linderman fails to disclose or suggest the limitations of claims 1, 13, and 19 in view of the amended claims. In particular, Applicant argues that Das fails to disclose a multilevel resistive device including a switchable resistive element made up of resistive devices connected in series with a switching device. It is noted that Applicant has not cited a particular portion of the disclosure for support of the amended limitations of claim 1. After further review, Applicant’s amendment appears to draw support from Fig. 1 along with ¶ 0014 of Applicant’s disclosure:
PNG
media_image1.png
195
271
media_image1.png
Greyscale
[0014] … The resistive assembly is symbolically illustrated by a resistive element R 132 and a selecting element 134 but are implemented by multiple resistive and selective elements, as explained in more detail below.
This is similar to Das Fig. 6 which depicts a multilevel resistive element in series with a switching device 58:
PNG
media_image2.png
255
255
media_image2.png
Greyscale
The resistive element of Das is further depicted as a multilevel resistive device in Fig. 8 elements 62a and 62b which is connected in series with switching transistors 64a and 64b which is similar to the multilevel device depicted in Fig. 3 Applicant’s disclosure. Thus, Das discloses the claimed limitations according to a broad but reasonable interpretation.
Claim Objections
Claim 4 is objected to because of the following informalities: the phrase “each of the switching device” appears to be a clerical error and should be changed to “each of the switching devices.” Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 19-24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 19 recites the limitation "connected to the second common output line" in line 6 on p. 7 as filed 1/23/2026. There is insufficient antecedent basis for this limitation in the claim. For the purpose of further examination, the limitation will be interpreted as “connected to a second common output line.”
Claims 20-24 are rejected as being dependent upon a rejected base claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 8-13 and 19-24 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication 2019/0236445 by Das et al. (“Das”) in view of U.S. Patent Application Publication 20140172937 by Linderman et al. (“Linderman”).
In regard to claim 1, Das discloses:
1. An analog computer, comprising: See Das, Fig. 2, depicting a computer.
a first plurality of nodes; See Das, Fig. 3, depicting nodes associated with signal V1.
a second plurality of nodes; See Das, Fig. 3, depicting nodes associated with signal V2.
Das does not expressly disclose: a plurality of differential amplifiers; However, this is taught by Linderman. See Linderman, Fig. 1, element 40, depicting a subtraction amplifier, i.e. a differential amplifier. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Das’ nodes with Linderman’s amplifier in order to provide a matrix-vector multiplication implementation which provides performance, area, and energy advantages as suggested by Linderman (see ¶ 0011).
Das also discloses:
a first column of resistive assemblies, the first plurality of nodes being connected to a first common output line via respective ones of the first column of resistive assemblies. See Das, Fig. 5, depicting a column of resistive assemblies at the far left. Common node 21’ connects the resistive assemblies. Also see ¶ 0085, “The crosspoint array module shown in FIG. 5 comprises a 4x4 array of row signal lines 18′ and column signal lines 20′ and 21′ …” Also see Figs. 3 and 8, depicting multiple inputs, outputs, nodes, and their respective node subsets and resistive assemblies.
a second column of resistive assemblies, the first plurality of nodes being further connected to a second common output line via respective ones of the second column of resistive assemblies; See Das, Fig. 5, depicting a column of resistive assemblies at the second column from the left. Common node 20’ connects the resistive assemblies. Also see ¶ 0085, “The crosspoint array module shown in FIG. 5 comprises a 4x4 array of row signal lines 18′ and column signal lines 20′ and 21′ …” Also see Fig. 8, depicting multiple inputs, outputs, nodes, and their respective node subsets and resistive assemblies.
a third column of resistive assemblies, the first plurality of nodes being further connected to a third common output line via respective ones of the third column of resistive assemblies; a fourth column of resistive assemblies, the first plurality of nodes being further connected to a fourth common output line via respective ones of the fourth column of resistive assemblies, See Das, Fig. 5, depicting a third and fourth column of resistive assemblies at the right. Common nodes 20’ and 21’ connects the resistive assemblies, respectively. Also see ¶ 0085, “The crosspoint array module shown in FIG. 5 comprises a 4x4 array of row signal lines 18′ and column signal lines 20′ and 21′ …” Also see Figs. 3 and 8, depicting multiple inputs, outputs, nodes, and their respective node subsets and resistive assemblies.
each resistive assembly in each of the first, second, third, and fourth columns of resistive assemblies comprising a plurality of resistive elements connected to each other in parallel, at least a subset of the resistive elements being switched resistive elements, See Das, Fig. 6, depicting parallel resistive assemblies. Also see ¶ 0071, “The non-volatile memory element may be a bipolar switching non-volatile memory element. In embodiments, the non-volatile memory element is any one of: a memristor, a resistive random access memory (ReRAM) …” Also see Fig. 8, depicting resistive assembly 12 having two resistive elements in parallel in the same manner as elements 62a and 62b and having switching elements 64a and 64b.
each of the switched resistive elements comprising a multilevel resistive device and a switching device connected in series with the multilevel resistive device; Note Fig. 1 along with ¶ 0014 of Applicant’s disclosure, describing the series depiction of Fig. 1 as being “symbolically illustrated … implemented by multiple resistive and selective elements.” See Das, Fig. 8, depicting each node with multiple selectable resistive elements in series with a switching transistor, providing a multilevel resistance device. Also see ¶ 0111, “Also see ¶ 0111, “At each neural network node 12 there are at least two non-volatile memory elements that are connected in parallel between the neural network node input 22 and neural network node output 24. In the illustrated example, there are two non-volatile memory elements 62a and 62b in each crosspoint array module at each neural network node 12. Each non-volatile memory element 62a, 62b is coupled to a switching transistor 64a, 64b.”
the first and second columns of resistive assemblies being adjacent to each other without any intervening resistive assemblies; the second and third common output lines being adjacent to each other without any intervening resistive assemblies, the third and fourth common output lines being adjacent to each other without any intervening resistive assemblies. See Das, Fig. 5, depicting four adjacent columns. Note that each column is considered to be electrically adjacent whereby each column is connected by row lines 18’, i.e. without any intervening resistive assemblies. This appears to be consistent with Applicant’s resistive assemblies (e.g. see Fig. 4 of Applicant’s drawings).
Das does not expressly disclose:
a first one of the plurality of differential amplifiers having inputs adapted to receive, respectively, a first output signal from the first output line and a second output signal from the second output line, and to output to a first respective one of the second plurality of nodes an output signal indicative of the difference between the first and second output signals; and a second one of the plurality of differential amplifiers having inputs adapted to receive, respectively, a third output signal from the third output line and a fourth output signal from the fourth output line, and to output to a second respective one of the second plurality of nodes an output signal indicative of the difference between the third and fourth output signals. However, this is taught by Linderman. See Linderman, Fig. 1, element 40, depicting “Subtraction Amplifiers,” i.e. differential amplifiers. Also see Linderman, Fig. 3, element 40, depicting a subtraction amplifier, i.e. a differential amplifier. Also see ¶ 0035, “In the present invention, the input signal VI along with VO+ and VO-, the corresponding voltage outputs of two memristor crossbar arrays, are fed into a number of analog subtraction amplifier circuits 40.” Note that Fig. 3 depicts signals voi+ and voi- with elements “i” which make up each element of the output vectors VO+ and VO- referenced above. The element i provides for first (e.g. vo1+), second (e.g. vo1-), third (e.g. vo2+), and fourth (e.g. vo2-) outputs which are fed to two differential amplifiers which produce the differential output signals vo1 and vo2. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Das’ nodes with Linderman’s amplifiers in order to provide a matrix-vector multiplication implementation which provides performance, area, and energy advantages as suggested by Linderman (see ¶ 0011).
In regard to claim 2, Das also discloses:
2. The analog computer of claim 1, wherein at least a subset of the second plurality of nodes are connected to a common one of the first plurality of nodes via respective ones of the first plurality of resistive assemblies. See Das, Fig. 6, depicting a common node connecting assembly 50b with array 50c.
In regard to claim 3, Das also discloses:
3. The analog computer of claim 2, wherein each combination of a node in the first plurality of nodes and a node in the second plurality of nodes are interconnected via a respective one of the first plurality of resistive assemblies. See Das, Fig. 6, depicting interconnection of nodes via resistive assemblies.
In regard to claim 4, Das also discloses:
4. The analog computer of claim 1, wherein each of the switching [devices] comprises a switching transistor. See Das, Fig. 6, depicting resistive device R10 in series with transistor 58. Also see ¶ 0099, “each non-volatile memory element may be coupled to a switching transistor.”
In regard to claim 5, Das also discloses:
5. The analog computer of claim 1, wherein each of the first plurality of resistive elements comprises a multilevel resistive device See Das, Fig. 8, depicting nodes comprising resistors. For example, elements 62a, 62b, 64a and 64b provides a multilevel resistive device.
In regard to claim 8, Das also discloses:
8. The analog computer of claim 1, further comprising:
a third plurality of nodes; and See Das, Fig. 3, depicting nodes associated with input signal Vm.
a second plurality of resistive assemblies, each comprising a plurality of resistive elements connected to each other in parallel, at least a subset of the plurality of resistive elements being switched resistive elements, See Das, Fig. 6 and ¶ 0071 as similarly cited in the rejection of claim 1 above.
at least a subset of the second plurality of nodes are connected to a common one of the third plurality of nodes via respective ones of the second plurality of resistive assemblies. See Das Fig. 6, as similarly cited in the rejection of claim 1 above.
In regard to claim 9, Das also discloses:
9. The analog computer of claim 3, further comprising:
a third plurality of nodes; and a second plurality of resistive assemblies, each comprising a plurality of resistive elements connected to each other in parallel, at least a subset of the plurality of resistive elements being switched resistive elements, See Das, Figs. 3 and 6 along with ¶ 0071 as similarly cited in claims 1 and 8 above.
wherein each combination of a node in the second plurality of nodes and a node in the third plurality of nodes are interconnected via a respective one of the second plurality of resistive assemblies. See Das, Fig. 6, as similarly cited in the rejection of claim 3 above.
In regard to claim 10, Das also discloses:
10. The analog computer of claim 9, wherein:
each of the first plurality of resistive assemblies is configurable into: a first configuration wherein a first subset of the plurality of resistive elements in each of the first plurality of resistive assemblies are adapted to be connected to each other in parallel; a second configuration wherein a second subset of the plurality of resistive elements in each of the first plurality of resistive assemblies are adapted to be connected to each other in parallel; and See Das, Fig. 8 and ¶ 0111, “Each non-volatile memory element 62a, 62b is coupled to a switching transistor 64a, 64b. The switching transistors enable a particular non-volatile memory element to be connected or disconnected from the crosspoint array module of a neural network node 12.”
each of the second plurality of resistive assemblies is configurable into: a first configuration wherein a first subset of the plurality of resistive elements in each of the second plurality of resistive assemblies are adapted to be connected to each other in parallel; a second configuration wherein a second subset of the plurality of resistive elements in each of the second plurality of resistive assemblies are adapted to be connected to each other in parallel; See Das, Fig. 8 and ¶ 0111, in a similar manner as cited above.
the analog computer being configurable into a plurality of mutually exclusive states in which: in a first of the plurality of states, both the first and second pluralities of resistive assemblies are configured into the respective first configuration, and in a second of the plurality of states, both the first and second pluralities of resistive assemblies are configured into the respective second configuration. See Das, Fig. 8 and ¶ 0111, in a similar manner as cited above.
In regard to claim 11, Das also discloses:
11. The analog computer of claim 1, wherein
the first plurality of nodes being further connected to a third common output line via respective ones of a third subset of the first plurality of resistive assemblies, the first plurality of nodes being further connected to a fourth common output line via respective ones of a fourth subset of the first plurality of resistive assemblies, each of the fourth subset of the first plurality of resistive assemblies being disposed adjacent a respective one of the third subset of the first plurality of resistive assemblies, … the third output line being disposed between the second and fourth output lines. See Das, Fig. 3, depicting nodes associated with common outputs I1, I2, … In, whereby “n” indicates a some number of sequential elements.
Das does not expressly disclose: a second one of the plurality of differential amplifiers having inputs adapted to receive, respectively, a third output signal from the third output line and a fourth output signal from the fourth output line, and to output to a respective one of the second plurality of nodes an output signal indicative of the difference between the third and fourth output signals. However, this is taught by Linderman. See Linderman, Fig. 1, element 40, depicting a subtraction amplifier, i.e. a differential amplifier. Also see Fig. 3 depicting a differential amplifier connecting output signals voi- and voi+ and producing a difference signal voi. Note that each of the respective signals in Fig. 1 are connected using differential amplifiers depicted as element 40.
In regard to claim 12, Das also discloses:
12. The analog computer of claim 1, wherein each of the first plurality of nodes is adapted to receive a current signal, and the first plurality of the resistive assemblies are adapted to generate at each of the second plurality of nodes a respective weighted sum of the current signals received at the first plurality of nodes. See Das, ¶ 0064, “output a summed signal representing the summed weighted signals.” Also see ¶ 0065, “the crosspoint array 10 may be configured to receive currents.”
In regard to claim 13, Das discloses:
13. A method of computing, comprising: See Das, Fig. 7, broadly depicting a method.
receiving a first plurality of signals at a respective first plurality of nodes; See Das, Fig. 3, depicting nodes associated with input signals.
selecting at least one subset of a plurality of multilevel resistive elements in each of a first plurality of resistive assemblies by turning on a switching transistor connected in series to the respective multilevel resistive element; Note Fig. 1 along with ¶ 0014 of Applicant’s disclosure, describing the series depiction of Fig. 1 as being “symbolically illustrated … implemented by multiple resistive and selective elements.” See Das, Fig. 8, depicting each node with multiple selectable resistive elements providing a multilevel resistance device. Also see ¶ 0111, “Also see ¶ 0111, “At each neural network node 12 there are at least two non-volatile memory elements that are connected in parallel between the neural network node input 22 and neural network node output 24. In the illustrated example, there are two non-volatile memory elements 62a and 62b in each crosspoint array module at each neural network node 12. Each non-volatile memory element 62a, 62b is coupled to a switching transistor 64a, 64b.”
for each of the first plurality of resistive assemblies, configuring the selected multilevel resistive elements into a parallel combination; See Das, Fig. 6, depicting parallel resistive assemblies. Also see ¶ 0071, “The non-volatile memory element may be a bipolar switching non-volatile memory element. In embodiments, the non-volatile memory element is any one of: a memristor, a resistive random access memory (ReRAM) …” Also ¶ 0095, “The control circuity may comprise means (e.g. transistors 54, 56) to select a column signal line and means (e.g. shorting transistors 52a-52d) to couple column signal lines together.”
transmitting the first plurality of signals from the first plurality of nodes to a first common output line via a first subset of the first plurality of resistive assemblies to generate a first output signal on the first common output line, the first subset being arranged in a first column; See Das, Fig. 3, depicting output I1 related to inputs V1, V2 … Vm in a first column.
transmitting the first plurality of signals from the first plurality of nodes to a second common output line via a second subset of the first plurality of resistive assemblies to generate a second output signal on the second common output line, See Das, Fig. 3, depicting output I2 related to inputs V1, V2 … Vm in a second output line.
the second subset of the first plurality of resistive assemblies being disposed adjacent to the first subset of the first plurality of resistive assemblies without any intervening subset of the first plurality of resistive assemblies; See Das, Fig. 5, depicting four adjacent columns. Note that each column is considered to be electrically adjacent whereby each column is connected by row lines 18’, i.e. without any intervening resistive assemblies. This appears to be consistent with Applicant’s resistive assemblies (e.g. see Fig. 4 of Applicant’s drawings).
transmitting the first plurality of signals from the first plurality of nodes to a third common output line via a third subset of the first plurality of resistive assemblies to generate a third output signal on the third common output line, the third subset being arranged in a third column; transmitting the first plurality of signals from the first plurality of nodes to a fourth common output line via a fourth subset of the first plurality of resistive assemblies to generate a fourth output signal on the fourth common output line, the fourth subset being arranged in a fourth column, … See Das, Fig. 3, depicting output “In” (i.e. output current “I,” signal “n”) related to inputs V1, V2 … Vm in a column “n.” Note that “n” is used to represent a series of an arbitrary number of outputs. In this case it could represent a third as well as a fourth output. Also see Linderman, Fig. 3, depicting adjacent signals voi- and voi+ connected to subtraction/differential amplifier 40 as related to depiction of resistive assemblies and signal arrays VO+ and VO- in Fig. 1. Note that the letter i is representative of any arbitrary number of common output line pairs.
… the third column being disposed between the second and fourth columns without any intervening subset of the first plurality of resistive assemblies; See Das, Fig. 5, depicting four adjacent columns. Note that each column is considered to be electrically adjacent whereby each column is connected by row lines 18’, i.e. without any intervening resistive assemblies. This appears to be consistent with Applicant’s resistive assemblies (e.g. see Fig. 4 of Applicant’s drawings).
transmitting to a first one of a second plurality of nodes a first … output signal … transmitting to a second one of the second plurality of nodes a second … output signal … via the respective parallel combinations. See Das, Fig. 11a and 11b.
Das does not expressly disclose: differential output signal …indicative of the difference between the first and second output signals: and a differential output signal … indicative of the difference between the third and fourth output signals. However, this is taught by Linderman. See Linderman, Fig. 1, element 40, depicting a subtraction amplifier, i.e. a differential amplifier, providing a differential output signal. In the context of Fig. 3, output pairs from Fig. 1 are combined as depicted in Fig. 3 to provide an associated output voi. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Das’ nodes with Linderman’s amplifier in order to provide a matrix-vector multiplication implementation which provides performance, area, and energy advantages as suggested by Linderman (see ¶ 0011).
In regard to claim 19, Das discloses:
19. An artificial neural network, comprising: See Das, Fig. 1a, depicting an artificial neural network.
an upstream layer comprising a first plurality of nodes adapted to receive a respective plurality of signals; a first downstream layer comprising a second plurality of nodes; See Fig. 1a, depicting an input node layer, hidden layers, and an output layer.
…
each resistive assembly in each of the first, second, third, and fourth columns of resistive assemblies … comprising a multilevel resistive device and a switching device configured to connect the resistive device in parallel with the other resistive elements in the resistive assembly; See Das, Fig. 8, depicting a crosspoint array of parallel/multilevel resistive devices 62 connected to switching devices 64. Also see ¶ 0111, “Each non-volatile memory element 62a, 62b is coupled to a switching transistor 64a, 64b. The switching transistors enable a particular non-volatile memory element to be connected or disconnected from the crosspoint array module of a neural network node 12.” Note that this arrangement is similar to the resistive assemblies depicted in Fig. 3 of Applicant’s drawings.
All further limitations of claim 19 have been addressed in the above rejection of claim 1.
In regard to claim 20, Das also discloses:
20. The artificial neural network of claim 19, wherein each of the switching devices comprises a control input adapted to receive a select-signal, the switching device adapted to connect the respective resistive device in parallel with the other resistive elements in the resistive assembly upon receiving the select-signal, each of the resistive elements comprising a multi-level resistance device. See Das, Fig. 6, depicting transistors for connecting resistive devices in parallel. Also see Fig. 8, depicting each node with multiple selectable resistive elements providing a multilevel resistance device.
In regard to claim 21, parent claim 19 is addressed above. All further limitations of claim 21 have been addressed in the above rejection of claim 11.
In regard to claim 22, Das discloses:
22. The artificial neural network of claim 19, further comprising:
a second downstream layer comprising a third plurality of nodes; and a second plurality of resistive assemblies, at least a subset of the second plurality of nodes being connected to a common one of the third plurality of nodes via respective ones of the second plurality of resistive assemblies. See Das, Fig. 1a, depicting the connection of upstream inputs, and downstream outputs in multiple layers. Citation of the nodes and assemblies above applies to the additional layered nodes of Fig. 1a.
In regard to claim 23, Das discloses:
23. The artificial neural network of claim 22, further comprising
Das does not expressly disclose: a second plurality of differential amplifiers, However, Linderman teaches differential amplifiers as cited above. Also, see Das, Fig. 1a, depicting the connection of upstream inputs, and downstream outputs in multiple layers. Citation of the nodes and assemblies above applies to the nodes of Fig. 1a. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Das’ nodes with Linderman’s amplifier in order to provide a matrix-vector multiplication implementation which provides performance, area, and energy advantages as suggested by Linderman (see ¶ 0011).
the second plurality of nodes being connected to a third common output line via respective ones of a first subset of the second plurality of resistive assemblies, the second plurality of nodes being further connected to a fourth common output line via respective ones of a second subset of the second plurality of resistive assemblies, each of the second subset of the second plurality of resistive assemblies being disposed adjacent a respective one of the first subset of the second plurality of resistive assemblies, See Das, at least Fig. 6, depicting connection of resistive assemblies. Also see Fig. 1a, depicting the connection of upstream inputs, and downstream outputs in multiple layers. Citation of the nodes and assemblies above applies to the additional layered nodes of Fig. 1a.
Das does not expressly disclose: a first one of the second plurality of differential amplifiers having inputs adapted to receive, respectively, a first output signal from the third output line and a second output signal from the fourth output line, and to output to a respective one of the third plurality of nodes an output signal indicative of the difference between the first and second output signals. However, this is taught by Linderman. See Linderman, Fig. 1, element 40, and Fig. 3, as cited above. Also see Das, Fig. 1a, depicting the connection of upstream inputs, and downstream outputs in multiple layers. Citation of the nodes and assemblies above applies to the layered nodes of Fig. 1a.
In regard to claim 24, Das discloses:
24. The artificial neural network of claim 23, wherein:
the second plurality of nodes being further connected to a fifth common output line via respective ones of a third subset of the second plurality of resistive assemblies, the second plurality of nodes being further connected to a sixth common output line via respective ones of a fourth subset of the second plurality of resistive assemblies, each of the fourth subset of the first plurality of resistive assemblies being disposed adjacent a respective one of the third subset of the second plurality of resistive assemblies, See Das, at least Fig. 6, depicting connection of resistive assemblies. As noted above, see Das, Fig. 1a, depicting the connection of upstream inputs, and downstream outputs in multiple layers comprised of multiple nodes. Citation of the nodes and assemblies above applies to the additional layered nodes of Fig. 1a.
Das does not expressly disclose: a second one of the second plurality of differential amplifiers having inputs adapted to receive, respectively, a third output signal from the fifth output line and a fourth output signal from the sixth output line, and to output to a respective one of the third plurality of nodes an output signal indicative of the difference between the third and sixth output signals, However, this is taught by Linderman. See Linderman, Fig. 1, element 40, depicting a subtraction amplifier, i.e. a differential amplifier. Also see Fig. 3 and ¶ 0011 as cited with respect to parent claim 19 above. Also see the multiple layers and nodes of Das Fig. 1a as noted above.
the fifth output line being disposed between the fourth and sixth output lines. See Das, Fig. 3, depicting output In related to inputs V1, V2 … Vm in a column. Note that “n” is used to represent a series of outputs, in this case it could represent a third and a fourth output.
Claims 6-7 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Das in view of Linderman as applied above, and further in view of “Neuromorphic computing with multi-memristive synapses” by Boybat et al. (“Boybat”).
In regard to claim 6, Das also discloses:
6. The analog computer of claim 1, wherein each of the switching device elements comprises an input terminal adapted to receive a respective select signal for selectively connecting the respective multilevel resistance device between respective node and common output line,… See Das, Fig. 8, depicting each node with multiple selectable resistive elements providing a multilevel resistance device. See also Fig. 6 element 58 utilizing a switching transistor which inherently provides an input terminal for connecting the remaining two signals.
Das does not expressly disclose: the select signal being sequenced to generate the first output signal at a different time from generating the second output signal and generate the third output signal at a different time from generating the fourth output signal. However, Boybat teaches differential architecture. See Boybat p. 3, left column, “When the synapse has to be potentiated, one device from the group representing G+ is selected and potentiated, and when the synapse has to be depressed, one device from the group representing G− is selected and potentiated. … To alter the synaptic weight, one of the word lines is activated according to the value of the selection counter to program the selected device.” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Boybat’s differential architecture with the crossbar arrays of Das and Linderman in order to achieve relatively high classification accuracies as suggested by Boybat (see p. 6, top right column).
In regard to claim 7, Das also discloses:
7. The analog computer of claim 6, wherein each of the multilevel resistance devices comprises a multilevel resistive random access memory (RRAM) element. See ¶ 0002, “resistive random access memory (RRAM/ReRAM).” Also see ¶ 0056, “In embodiments, the non-volatile memory element may be a memristor, a resistive random access memory (ReRAM), …” Also see ¶ 0111, “At each neural network node 12 there are at least two non-volatile memory elements that are connected in parallel between the neural network node input 22 and neural network node output 24.”
In regard to claim 15, Das does not expressly disclose:
15. The method of claim 13, generating the first output signal at a different time from generating the second output signal, and generating the third output signal at a different time from generating the fourth output signal further comprising setting a resistance value of each of the at least one subset of a plurality of resistive elements in each of the first plurality of resistive assemblies to one of a plurality of resistance values.
However, Boybat teaches differential architecture. See Boybat p. 3, left column, “When the synapse has to be potentiated, one device from the group representing G+ is selected and potentiated, and when the synapse has to be depressed, one device from the group representing G− is selected and potentiated. … To alter the synaptic weight, one of the word lines is activated according to the value of the selection counter to program the selected device.” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Boybat’s differential architecture with the crossbar arrays of Das and Linderman in order to achieve relatively high classification accuracies as suggested by Boybat (see p. 6, top right column).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to James D Rutten whose telephone number is (571)272-3703. The examiner can normally be reached M-F 9:00-5:30 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Li B Zhen can be reached on (571)272-3768. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/James D. Rutten/Primary Examiner, Art Unit 2121
Prosecution Insights