DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 4-5, 8, 12-13, 15, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kamikubo (US 11119930 B2), and further in view of Iwasaki (US 20200201556 A1).
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Claim 15. (Previously presented) A computer system for managing application execution, the computer system comprising:
one or more computer processors;
one or more computer readable storage devices;
stored program instructions on the one or more computer readable storage devices for execution by the one or more computer processors, the stored program instructions comprising:
program instructions for sending a READ cache memory command for an address's content as part of a speculatively executed branch routine;
program instructions for receiving a cache miss result for the address associated with the READ cache memory command;
program instructions for receiving a resolution for the branch routine, the resolution including the READ cache memory command, subsequent to receiving the cache miss result;
program instructions for sending a READ memory directly command for the address in response to receiving the resolution for the branch routine including the READ cache memory command; and
program instructions for receiving the address's content in response to the READ memory directly command.
Referring to claims 1, 8, 15 (Previously presented), and taking claim 15 as exemplary, Kamikubo teaches a computer system for managing application execution, the computer system comprising:
one or more computer processors; ([Kamikubo Figs. 1, 2])
one or more computer readable storage devices; ([Kamikubo Figs. 1, 2])
stored program instructions on the one or more computer readable storage devices for execution by the one or more computer processors, ([Kamikubo Abstract] instruction) the stored program instructions comprising:
program instructions for sending a READ cache memory command for an address's content as part of a speculatively executed branch routine; ([Kamikubo Fig. 17, Claim 1, 1:60-2:23 (8), 5:16-30 (37)] the instruction issuer issues an instruction that is a read command, which is a part of a speculative branch instruction.)
program instructions for receiving a cache miss result by for the address associated with the READ cache memory command; ([Kamikubo Fig. 17, Claim 1, 1:60-2:23 (8), 7:13-29 (50), 9:44-10:35 (65)] cache controller preforms a cache hit judgment (Fig. 17, S40) if there is a hit or miss)
program instructions for receiving a resolution for the branch routine, the resolution including the READ cache memory command, subsequent to receiving the cache miss result; ([Kamikubo Fig. 17, Claim 1, 1:60-2:23 (8), 7:13-29 (50), 8:60-9:12 (60-61), 9:44-10:35 (65)] a resolution for the branch routine is received, as there is an indication of a cache registration performed by a speculative memory access. The speculative instruction includes memory access, which includes a read command. Memory access can be issued before the determination of the branch instruction.)
program instructions for sending a READ memory directly command for the address in response to receiving the resolution for the branch routine including the READ cache memory command; and ([Kamikubo Fig. 17, Claim 1, 1:60-2:23 (8), 25:18-34 (153)] The memory access request is issued (Fig. 17, S41). The branch ID ensures the instruction is for that specific branch. Memory access request includes a read command.)
[Kamikubo 1:60-2:23 (8), 25:18-34 (153)] teaches executing memory access, but does not explicitly teach program instructions for receiving the address's content in response to the READ memory directly command.
program instructions for receiving the address's content in response to the READ memory directly command. ([Iwasaki 0058-61, 0069-70] The CPU receives the address’s contents from the memory module.)
Before the effective date of invention, it would have been obvious to a person of ordinary skill in the art, having the teachings of Kamikubo and Iwasaki before them to combine the memory access of Kamikubo with the reception of data of Iwasaki. The reason or motivation for doing so would be ([Iwasaki Background] to increase the processing speed of personal computers and servers).
Claim 1 is a computer implemented method, and claim 8 is a computer program product variation of the computer system of claim 15 and are rejected using the same rationale.
Referring to claims 4 and 13 (Previously presented), and taking claim 4 as exemplary, Kamikubo modified teaches the computer implemented method according to claim 1, further comprising:
storing, an address for which the cache miss result has been received. ([Kamikubo Claim 1, 1:60-2:23 (8)] the memory access instruction is issued for the same address as an address of the first memory access instruction, which resulted in a cache miss. Thus, the system knows (stored) the address.)
Claim 13 is a computer program product variation of the computer implemented method of claim 4 and is rejected using the same rationale.
Referring to claims 5, 12 and 18 (Previously presented), and taking claim 18 as exemplary, Iwasaki teaches the computer system according to claim 15, the stored program instructions further comprising:
program instructions for receiving the READ cache memory command for an address; ([Kamikubo Fig. 17, Claim 1, 1:60-2:23 (8), 5:16-30 (37)] the cache controller receives a memory access/read instruction from the instruction issuer.)
program instructions for sending the cache miss result; ([Kamikubo Fig. 17, Claim 1, 1:60-2:23 (8)] as the cache controller preforms a cache hit judgment (Fig. 17, S40), and subsequently, issues a command based on this result, the cache miss result was sent and received.)
program instructions for receiving the READ memory directly command for the address; and ([Kamikubo Fig. 17, Claim 1, 1:60-2:23 (8), 5:17-30 (37), 25:18-34 (153)] The cache controller issues the memory access request (Fig. 17, S41). The branch ID ensures that the instruction issued is for the identified branch. The memory access request is received by the memory access controller MAC, which controls the memory module.)
program instructions for returning the address's content. ([Iwasaki 0058-61, 0069-70] The CPU receives the address’s contents from the memory module via the memory controller M_CON.)
17. Claim 5 is a computer implemented method, and claim 12 is a computer program product variation of the computer system of claim 18, and are rejected using the same rationale.
Claims 6, 14, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kamikubo (US 11119930 B2), in view of Iwasaki (US 20200201556 A1) as applied to claims 1, 8, and 15 above, and further in view of Oracle Corporation, (Chapter 8 Direct Memory Access (DMA), 2010).
Referring to claims 6, 14, 19 (Previously presented), and taking claim 19 as exemplary, Kamikubo modified does disclose a direct memory access (DMA) structure [Iwasaki 0060], but does not explicitly teach the program instructions for defining a READ memory directly command.
However, Oracle teaches program instructions for defining the READ memory directly command. ([Oracle. DMA Model] Performing First-Party DMA Transfers In general, the driver should perform the following steps for first-party DMA.
1. Allocate a DMA channel.
2. Configure the channel with ddi_dmae_1stparty(9F).
3. Ensure that the DMA object is locked in memory (see physio(9F) or ddi_umem_lock(9F)).
4. Allocate DMA resources for the object.
5. Program the DMA engine on the device and start it (this is device specific). When the transfer is complete, continue the bus-master operation. (Transfer is deemed reading)
6. Perform any required object synchronizations.
7. Release the DMA resources.
8. Deallocate the DMA channel.)
Kamikubo modified and Oracle are analogous art because they are from the same field of endeavor in instruction code. Before the effective date of the invention, it would have been obvious to a person of ordinary skill in the art having the teaching of Kamikubo modified and Oracle before them to modify the DMA structure of Kamikubo modified to define a direct memory read command of Oracle. The reason or motivation for doing so would be to ([Oracle. DMA Model] Perform any required object synchronizations).
Claim 6 is a computer implemented method, and claim 14 is a computer program product variation of the computer system of claim 19 and are rejected using the same rationale.
Claims 7, 11, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kamikubo (US 11119930 B2), in view of Iwasaki (US 20200201556 A1) as applied to claims 1, 8, and 15 above, and further in view of Imar Spaanjaars, (Logging Errors to the Event Log in ASP.NET Applications, 2004).
Referring to claims 7, 11, 20 (Previously presented), and taking claim 20 as exemplary, Kamikubo modified does disclose generating and indicating a cache miss result that could be included in an exception log [Iwasaki 0060], but does not explicitly teach generating an exception log.
However, Spaanjaars teaches the computer system according to claim 15, the stored program instructions further comprising: program instructions for generating an exception log including details about the cache miss result ([Spaanjaars. Creating Your Own Event Log] call the static CreateEventSource method of the EventLog class that lives in the System.Diagnostics namespace).
Kamikubo modified and Spaanjaars are analogous art because they are from the same field of endeavor in instruction code. Before the effective date of the invention, it would have been obvious to a person of ordinary skill in the art having the teaching of Kamikubo modified and Spaanjaars before them to modify the cache miss indication mechanism of Kamikubo modified to include error logging of Spaanjaars. The reason or motivation for doing so would be to ([Spaanjaars. Creating Your Own Event Log. Introduction] catch errors and log them for viewing later.)
Claim 7 is a computer implemented method, and claim 11 is a computer program product variation of the computer system of claim 20 and are rejected using the same rationale.
Response to Arguments
Applicant's arguments filed 08/22/2024 have been fully considered but they are not persuasive.
The Applicant argues:
“The cited portions of Kamikubo fail to disclose at least the limitations of "receiving a resolution for the branch routine, the resolution including the READ command subsequent to receiving the cache miss result;” … the reference "judges as a speculative entry cache miss" after receipt of a second memory access instruction to the common address and issues the memory access request after the second load request without regard to receipt of a branch resolution including the same read command as required in the claims."
“Kamikubo 10:30-35 provides that the memory access occurs in response to subsequent LOAD instructions: "With this, in the subsequent LOAD instructions, the provisional registration entry is subjected to an L1 cache miss. Data registration request DA_RG_RQ: A memory access request which is issued to the main memory side when the cache miss or the speculative entry cache miss occurs. Not in response to the receipt of a relevant branch resolution.”
In response to Applicant's argument, Kamikubo 9:44-10:35 (65) clarifies: “for a speculative memory access request, a speculative entry cache miss occurs and the data registration request is issued.” A “data registration request” is data retrieval method, where the data address is submitted to the memory address register, and received through the memory data register, see page 1 of “Understanding the MAR and the MDR” in the prior art made of record and not relied upon section of the conclusion. This would mean that a memory read command does not find the data in the cache (i.e., a miss), a determination of a speculative execution is made, and the system issues a main memory read request.
Additionally, Kamikubo Fig. 17 step S40 shows cache hit/miss judgment, after which, and due to which, memory access is executed in S41.
Furthermore, Kamikubo Figs. 20-22 show various embodiments of a speculative execution cache miss and subsequent main memory access. L1 and L2 are taken together as “the cache”.
“The Summary of Kamikubo, discloses that the “cache controller is configured to perform cache hit judgement, in response to a memory access instruction issued from the instruction issuer, based on an address of the memory access instruction and configured to issue a memory access request to a memory in a case where the cache hit judgement is a cache miss”, the summary goes on to provide: “in response to a second memory access instruction...judges as a speculative entry cache miss and issues the memory access request’. So the judgement of a cache miss leading to the memory access request, occurs after the receipt of the second memory access instruction. No mention is made in this of the timing of the branch determination relative to the judgement of a cache miss.”
In response to Applicant's argument, the quotation providing context is “…in a case where the provisional registration information of an entry in the cache tag for which a cache hit occurs has the provisional registration state, judges as a speculative entry cache miss and issues the memory access request.” “In a case where” means the condition has to have had occurred before the issuance of a memory access instruction. This quote recites the determination of what the tag/flag indicates. The case where the assignment of the branch determination happens, is in fact described at the beginning of this paragraph/ run-on sentence: “and to which a speculative access flag indicating speculative execution and an identification (IID) of a branch instruction are added”. It also appears to be a reference to the events described in Figs. 16A-B, a part of the process not relevant to the claims above.
Kamikubo 9:44-10:35 (65) and Figs. 17, 20-22 provide much clearer detail on the progression of the method, discussed just above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Charles C. Lin, Understanding the MAR and the MDR, 2003, University of Maryland. Discusses memory address and data registers, related to the data registration request.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ALEXANDER VINNITSKY/Examiner, Art Unit 2136 /ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133
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