Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/12/2025 has been entered.
Response to Arguments
Applicant's arguments with respect to the claims have been considered but are moot in view of the new ground(s) of rejection. The independent claims have been amended to include new limitations that were never previously presented; thereby, these amendments change the scope of the claims. However, newly found prior arts are applied.
Claim Objections
Claim 2 is objected to because of the following informalities: in claim 2, the word “and” in the limitation “and OpenCL graph” appears to be a typo.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-4, 7, 17, 20, 22, 25-27 and 30-32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Capalija et al. (U.S. PG Pub. No. 20200401402 A1, hereinafter “Capalija”) in view of Vercellotti et al. (U.S. PG Pub. 20210200505 A1, hereinafter “Vercellotti”).
Regarding claim 1, Capalija teaches a processor, comprising:
one or more circuits to:
identify one or more portions of an of processing core operational codes and a set of operand identifiers to execute the directed graph and a set of operand identifiers”);
perform the one or more optimizations on the one or more identified portions (Capalija ¶0041, “The compiler can also output an assignment of packets for storage on specific processing cores within the set of processing cores to initialize the directed graph for execution and breakdown the instructions of the application code into instructions for execution on individual processing cores in such a way that the execution of the application code is maximally parallelized with minimal memory latency and such that data movement is optimized for that purpose”); and
cause the
Capalija fails to explicitly teaches the graph is an instantiated graph and the identification based on part of the changes made subsequent to instantiation. However, in the same field of endeavor, Vercellotti teaches the graph is an instantiated graph and the identification based on part of the changes made subsequent to instantiation (Vercellotti ¶0030, “The controller then instantiates the optimized signal graph in the system hardware, software, and available connections (FIG. 1, 116). This may be performed iteratively or as the optimized graph is developed, or as a separate step after the optimization process has been completed. Graph recomposition (106) and instantiation in hardware/software (116) may be merged into a single step in a system which instantiates all graph changes directly while the graph is being optimized”, “The controller maintains internal representation 232 that is updated to reflect the user's current requirements. Having determined that an audio signal graph recomposition is required, the controller performs graph configuration step 106 (FIG. 1) to generate an optimized graph that meets the user's requirements subject to the system constraints”). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Capalija by incorporating the teachings of Vercellotti. The motivation would be for providing an optimized graph that meet user’s requirements subject to the system constraints (Vercellotti ¶0031).
As to claim 3, Capalija as modified by Vercellotti also teaches the processor of claim 1, wherein the one or more optimizations for executing the instantiated graph are reused the instantiated graph is performed different times using the one or more changes to the one or more operands (Capalija ¶0041, “The compiler can also output an assignment of packets for storage on specific processing cores within the set of processing cores to initialize the directed graph for execution and breakdown the instructions of the application code into instructions for execution on individual processing cores in such a way that the execution of the application code is maximally parallelized with minimal memory latency and such that data movement is optimized for that purpose”).
As to claim 4, Capalija as modified by Vercellotti also teaches also teaches the processor of claim 1, wherein the instantiated graph is optimized, prior to a first performance of the instantiated graph, for execution on a processing unit, and the optimized instantiated graph is reused (Capalija ¶0041, i.e., optimized instantiated graph is reused after initializing).
As to claim 7, Capalija as modified by Vercellotti also teaches the processor of claim 1, the one or more circuits to determine that the instantiated graph can be performed, using the one or more changes to the one or more operands, without changing a topology for executing the instantiated graph (Capalija ¶0042, i.e., optimized instantiated graph is performed after initializing).
Claim 17 recites the limitations substantially similar to those of claim 1 and is similarly rejected.
Claim 20 recites the limitations substantially similar to those of claim 7 and is similarly rejected.
As to claim 22, Capalija as modified by Vercellotti also teaches the system of claim 17, the one or more processors to:
generate optimized instructions for performing the instantiated graph a first time based on a first set of the one or more operands (Capalija ¶0041); and
perform the instantiated graph a second time, using a second set of the one or more operands, using the optimized instructions (Capalija ¶¶0041-0042).
Regarding claim 25, Capalija as modified by Vercellotti also teaches a system comprising:
a memory comprising a first buffer and a second buffer (Capalija ¶0054); and
at least one processor to perform the same method as recited in claim 1.
Claim 25 is similarly rejected.
As to claim 26, Capalija as modified by Vercellotti also teaches the system of claim 25, wherein the instantiated graph is optimized based at least in part on the first buffer (Capalija ¶0042 and ¶0054).
As to claim 27, Capalija as modified by Vercellotti also teaches the system of claim 26, wherein optimizations of the instantiated graph based at least in part on the first buffer operates are used to perform the instantiated graph the second time (Capalija ¶0042 and ¶0054).
As to claim 30, Capalija as modified by Vercellotti also teaches the system of claim 25, wherein the instantiated graph is optimized upon being instantiated prior to a first time the instantiated graph is performed (Capalija ¶0041).
As to claim 31, Capalija as modified by Vercellotti also teaches the system of claim 25 but fails to explicitly teach wherein the instantiated graph is optimized for performance on selected processing unit (Capalija ¶0041).
As to claim 32, Capalija as modified by Vercellotti also teaches the processor of claim 1, wherein the instantiated graph is compiled prior to the multiple executions and at least part of the instantiated graph is reused (Capalija ¶0041).
Claims 2, 18 and 28-29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Capalija and Vercellotti, and further in view of Liu et al. (U.S. PG Pub. No. 2020/0334083 A1, hereinafter “Liu”).
As to claim 2, Capalija as modified by Vercellotti teaches the processor of claim 1, but failed to explicitly teach wherein the instantiated graph is at least one of a compute unified architecture, (“CUDA”) graph, and OpenCL graph, or a heterogeneous compute interface for portability (“HIP”) graph. However, in the same field of endeavor, Liu teaches the instantiated graph is at least one of a compute unified architecture (“CUDA”) graph (Liu ¶0035) and OpenCL graph, or a heterogeneous compute interface for portability (“HIP”) graph. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Capalija and Vercellotti by incorporating the teachings of Liu. The motivation would be for tuning CUDA application performance (Liu ¶0036).
Claim 18 recites the limitations substantially similar to those of claim 2 and is similarly rejected.
As to claim 28, Capalija as modified by Vercellotti also teaches the system of claim 25, but fails to explicitly teach wherein the instantiated graph is a CUDA graph. However, in the same field of endeavor, Liu teaches the instantiated graph is a CUDA graph (Liu ¶0035). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Capalija and Vercellotti by incorporating the teachings of Liu. The motivation would be for tuning CUDA application performance (Liu ¶0036).
As to claim 29, Capalija as modified by Vercellotti and Liu also teaches the system of claim 28, wherein the instantiated graph comprises a plurality of CUDA kernels (Liu ¶0035).
Claims 6 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Capalija and Vercellotti, and further in view of Fleming et al. (U.S. Patent No. 10,416,999 B2, hereinafter “Fleming”).
As to claim 6, Capalija as modified by Vercellotti teaches the processor of claim 1 but fails to explicitly teach wherein the one or more operands comprise a first buffer operated on by the instantiated graph when the instantiated graph is performed a first time, and a second buffer, different than the first buffer, operated on by the instantiated graph when the instantiated graph is performed a second time. However, in the same field of endeavor, Fleming teaches the one or more operands comprise a first buffer operated on by the instantiated graph when the instantiated graph is performed a first time, and a second buffer, different than the first buffer, operated on by the instantiated graph when the instantiated graph is performed a second time (Fleming Claim 1, i.e., different input buffers are used for different data paths). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Capalija and Vercellotti by incorporating the teachings of Fleming. The motivation would be to provide a configurable spatial accelerator (Fleming Col 1 Ln 17-18).
Claim 19 recites the limitations substantially similar to those of claim 6 and is similarly rejected.
Allowable Subject Matter
Claims 9-16 are allowed.
Claims 22-24 are objected to as being dependent upon a rejected base claim(s), but would be allowable if rewritten in independent form including all of the limitations of the base claim(s) and any intervening claims.
The features of claim limitations presented in claim 9, and in claims 8, 10-16 and 22-24 in combination with the other limitations recited in the context of their respective base claim(s) is allowable subject matter.
Conclusion
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/ALEXANDER KHONG/Primary Examiner, Art Unit 2168