DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/09/2025 has been entered.
Response to Amendment
This application is responsive to amendment filed on 06/09/2025. Applicant’s amendments have overcome the claim objections and rejection under 35 U.S.C. 101 directed to non-statutory subject matter as set forth in the previous office action.
Response to Arguments
In response to applicant’s argument regarding rejection under 35 U.S.C. 101 on Remarks page 8, “at least the recited bit matrix multiply and accumulate logic cannot reasonably be reduced to a “mathematical concept.” BMMA logic refers to specific type of computer hardware (e.g., the operation of which is described with reference to at least fig.3-6 of the specification), which does not fall under the category of mathematical concepts”.
Examiner respectfully disagrees because upon further consideration, the BMMA logic invoke 112(f) interpretation and figure 7 illustrates a processor to execute an algorithm to perform BMMA operations to generate the plurality of Galois residues. Thus, such BMMA logic under 112(f) interpretation would include processor performing algorithm, rather than a specific type of computer hardware, which is recited at a high level of generality and amount to no more than mere instructions to apply the judicial exception using computer component. In other words, such BMMA logic is not recited as a specific or particular computer hardware, but simply added after the fact of an abstract idea (e.g., calculating a plurality of Galois residues).
Applicant further asserted on page 9, "Furthermore, with regard to Step 2A, the Office Action asserts that parallel calculation is “at most considered as insignificant extra solution activity because parallelism is a known concept in computer[s].” Office Action, p. 5. This characterization is improper because it views “parallel” in isolation and does not consider the claim as a whole. For example, the recited calculation of a plurality of Galois residues in parallel is enabled by the use of the recited BMMA logic. This is in contrast to conventional computing devices (e.g., lacking BMMA logic) that would lack this capacity, and therefore represents a practical application into which the independent claims are integrated. Therefore, the claims are directed to a specific improvement in computer technology.".
Examiner respectfully disagrees because the concept of performing calculations in parallel is generically recited in the claim and at most determined as well-understood, routine and conventional activity (see at least Hennessy, John L., et al. Computer Architecture : A Quantitative Approach, Elsevier Science & Technology, 2014. ProQuest page 529, describe SIMD model where multiple data are being operated in parallel). MPEP 2106.05(a)(II) provides an example that the courts have indicated may not be sufficient to show an improvement, such as ii. using well-known standard laboratory techniques to detect enzyme levels in a bodily sample such as blood or plasma. Thus, using a well-known technique of performing in parallel is not sufficient to show an improvement under step 2A prong two and fails to integrate the judicial exception into a practical application. Furthermore, as mentioned above, BMMA logic is recited at a high level of generality, e.g. a computer component performing computer function, which amounts to no more than mere instructions to apply judicial exception using computer components. Thus. such limitations fail to integrate the judicial exception into a practical application.
In response to applicant’s argument regarding rejection under 35 U.S.C. 102 on Remarks page 9-10, “Applicant respectfully submits that Stein does not disclose all of these elements. Stein appears to disclose calculating multiple terms of polynomials in parallel, where these polynomials are used to ultimately calculate a Galois residue. See, e.g., Stein, paragraph [0028] et seq. and FIG. 1. As best understood, the Office Action considers these terms to disclose “Galois residue values” calculated in parallel. See Office Action, pp. 12-13. Even assuming arguendo that this characterization is proper, which Applicant does not concede, Stein only discloses, at most, calculating a single Galois residue based on the polynomials. Accordingly, the independent claims are amended to recite “calculate a plurality of Galois residues in parallel,” which Stein does not disclose. Accordingly, Applicant respectfully submits that claim 1 is allowable under 35 U.S.C. § 102 over Stein.”
Examiner respectfully disagrees because Examiner did not considers the terms as disclosed in [0028] as Galois residue values, but rather consider the results of performing modulo p(x) as described in [0039] as the Galois residue values since performing module operation results in a remainder, wherein the step of calculating a plurality of Galois residue values in parallel using transformer units 18a-18n using the results generated by the plurality of multiplier units 12, and performs c(x) modulo p(x), wherein Chart I describes c(0) to c(6), results of c(x) mod p(x) corresponds Galois residue values. However, based on the amended claims, there are new ground of rejections using Stein - US 20040078409. See rejection below for details.
Claim Objections
Claims 9-20 are objected to because of the following informalities:
Claim 9 line 2-4 recites “cause the one or more processors to at least cause the one or more processors to calculate” such limitation of “cause the one or more processors” is redundant. Examiner suggests amending the claim as “cause the one or more processors to calculate”.
Claim 16 line 2-5 recites “using circuitry comprising bit matrix multiply and accumulate (BMMA) logic to calculate a plurality of Galois residues in parallel based, at least in part, on a first matrix and a second matrix using the bit matrix multiply and accumulate (BMMA) logic”. Such recitation of “using the bit matrix multiply and accumulate (BMMA) logic seems redundant. Examiner suggests removing the recitation of “using the bit matrix multiply and accumulate (BMMA) logic” in line 4-5.
Claim 17 recites “the BMMA logic to represents” should be “the BMMA logic to represent”.
Dependent claim is also objected for inheriting the same deficiencies in which claim it depends on.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) :
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) . The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) . The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“bit matrix multiply and accumulate (BMMA) logic” in claims 1-8 and 26. Figure 7 [0091] illustrates a flowchart of a technique of generating Galois Residue based on an 8x8x128 BMMA instructions, such as BMMA.88128.AND.POPC Rd, Ra, Rb, Re) simultaneously determines Galois residues of eight degree-127 GF polynomials. See [0092-0095] describes the steps of calculating Galois values based on Q0 mod p(x) Q1 mod p(x), ... , Q7 mod p(x) for respective eight degree 127 polynomials packed in Matrix A of BMMA instruction and store the eight 8 bit results to a destination register Rd.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 and 26 are rejected under 35 U.S.C. 101 because claimed invention is directed to an abstract idea without significant more.
Claim 1 recites apparatus for performing matrix multiply and accumulate operation to calculate a Galois residue value.
Under Prong One of Step 2A of the 2019 Revised Patent Subject Matter Eligibility Guidance (“2019 PEG”), the claim recites calculate a plurality of Galois residues based, at least in part, one a first matrix and a second matrix (noted that as invoke 112(f) for BMMA logic, figure 7 describes an algorithm operating on a processor to perform operations, such as generating matrix, generating values from matrix and performing BMMA operation). Such limitation covers mathematical calculations, relationship, and/or formula (see figure 7 [0085], [0091-0095] describes a plurality of Galois residue values are calculated using BMMA operation using XOR and AND operations based on matrices). Therefore, the claim includes limitations that fall within the “Mathematical Concepts” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Under Prong Two of Step 2A, this judicial exception is not integrated into a practical application. The claim additionally recites a processor comprises bit matrix multiply and accumulate (BMMA) logic to cause the processor to calculate and store data in one or more destination computer storage locations using the BMMA logic. However, the additional elements are recited at a high level of generality, i.e., as computer components performing computer functions of processing data and storing data. Furthermore, the claim recites step of calculating in parallel, but such step of calculating in parallel is recited at a high level of generality, and at most considered as insignificant extra solution activity because parallelism is a known concept in computer. Moreover, the step of storing data is also considered as insignificant extra solution activity, e.g., mere data gathering. Such additional elements fail to provide a meaningful limitation on the judicial exception, and amount to no more than mere instructions to apply the exception using computer components. Thus, the claim is directed to an abstract idea.
Under Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed previously with respect to the step 2A prong two, the additional elements in the claim amount to no more mere instructions to apply the exception. Furthermore, the step of performing operations in parallel is at most considered as an insignificant extra solution activity because such limitation is determined to be well-understood, routine, and conventional activity (see at least Hennessy, John L., et al. Computer Architecture : A Quantitative Approach, Elsevier Science & Technology, 2014. ProQuest page 529, describe SIMD model where multiple data are being operated in parallel. Moreover, the step of storing data in computer storage determined to be well-understood, routine and conventional activity (See MPEP 2106.05(d)(II)(iv) storing and retrieving information in memory). The claim does not provide an inventive concept. Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 2 recites wherein the BMMA logic causes a bitwise AND operation, such limitation further covers the mathematical concepts of performing AND operation and fails to provide any additional element that would integrate the judicial exception into a practical application under step 2A prong two and does not provide an inventive concept under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 3 recites wherein the processor comprising one or more circuits to calculate the plurality of Galois residues based, at least in part, on an XOR operation applied to at least a portion of a result of the bitwise AND operation, such limitation further covers the mathematical concepts of performing XOR operation to calculate the Galois residue value. The claim further recites one or more circuits, but such limitation is recited at a high level of generality, e.g., generic computer component performing generic computer function of processing data, thus such limitation fails to integrate the judicial exception into a practical application under step 2A prong two and does not provide an inventive concept under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 4 recites wherein the plurality of Galois residues comprise a first Galois residue, and calculate one or more additional Galois residues in response to performing the bit matrix multiply and accumulate operation, such limitation further covers the mathematical concepts to calculate Galois residues (see figure 7 [0085], [0091-0095]). The claim further recites one or more circuits, and calculate one or more additional Galois values in parallel with the first Galois residue value, but such limitations are recited at a high level of generality, e.g., generic computer component performing generic computer function of processing data in parallel. Alternatively, the step of performing operations in parallel is at most considered as an insignificant extra solution activity because such limitation is determined to be well-understood, routine, and conventional under step 2B (see at least Hennessy, John L., et al. Computer Architecture : A Quantitative Approach, Elsevier Science & Technology, 2014. ProQuest page 529, describe SIMD model where multiple data are being operated in parallel. Thus, the additional elements amount to no more than mere instructions to apply the abstract idea on a computer or merely uses a computer as a tool to perform an abstract idea, which do not integrate the judicial exception into a practical application under step 2A prong two and do not provide an inventive concept under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 5 recites generate a first set of values based, at least in part, on a matrix representation of a Galois polynomial, and calculate the plurality of Galois residues based, at least in part, on the first set of values, such limitation further covers the mathematical concepts (see at least figure 7 step 704, 706, and [0092-0094]). The claim further one or more circuits, but such limitation is recited at a high level of generality, e.g., generic computer component performing generic computer function of processing data. Moreover, the claim recites load the first set of values in a first register, such additional element is considered an insignificant extra solution activity under step 2A prong two because the limitation amount to necessary data gathering, thus it fails to provide any additional element that would integrate the judicial exception into a practical application, and is determined to be well-understood, routine, and conventional under step 2B because the courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (see MPEP 2106.05(d)(II)(iv). Storing and retrieving information in memory). Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 6 recites wherein the Galois polynomial is of a first degree value, wherein the second set of values represents one or more polynomials of a second degree value higher than the first degree value, and calculate the plurality of Galois residues based, at least in part, on the second set of values, such limitation further covers the mathematical concepts (see at least figure 7 and [0092-0095]). Claim 6 further recites the one or more circuits are to load a second set of values in a second register, such additional element is considered an insignificant extra solution activity under step 2A prong two, thus it fails to provide any additional element that would integrate the judicial exception into a practical application, and is determined to be well-understood, routine, and conventional under step 2B because The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (see MPEP 2106.05(d)(II)(iv). Storing and retrieving information in memory). Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 7 recites wherein the third set of values represents one or more polynomials, and the one or more circuits are to calculate one or more additional Galois residue values based, at least in part on the first set of values in the first register and the third set of values in the second register, such limitation further cover the mathematical concepts (see at least figure 7 and [0092-0095]). Claim 7 further recites the one or more circuits are to load a third set of values in the second register, such additional element is considered an insignificant extra solution activity under step 2A prong two, thus it fails to provide any additional element that would integrate the judicial exception into a practical application, and is determined to be well-understood, routine, and conventional under step 2B because The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (see MPEP 2106.05(d)(II)(iv). Storing and retrieving information in memory). Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 8 recites wherein the Galois polynomial is of degree 8, and each of the one or more polynomials represented by the third set of values is of degree 127, such limitation further cover the mathematical concepts of polynomials having number of order of degree (see figure 6 [0092]) and fails to provide any additional element that would integrate the judicial exception into a practical application under step 2A prong two and does not provide an inventive concept under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 26 further recites wherein the processor comprises one or more circuits to load one or more registers and perform a BMMA instruction using the loaded one or more registers to calculate the plurality of Galois residues. However, one or more registers and perform a BMMA instruction using the loaded one or register are recited at high level of generality, i.e., generic computer component to perform generic function, such as storing or retrieving data and executing the instruction. Such additional elements amount to no more than mere instructions to apply the exception using generic computer element and fail to integrate the judicial exception into a practical application under step 2A prong two. Furthermore, the claim does not provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim in addition to (beyond) the judicial exception, and fails to ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claims 9-15 recite product claims having similar limitation as the apparatus claims 1-7. Thus, they are rejected for the same reasons. Furthermore, the claims recite a non-transitory machine readable medium having stored therein a set of instructions, which if performed by one or more processors, cause the one or more processors to operate. Such additional elements are recited at a high level of generality, e.g., generic computer components to perform generic computer function, such as storing and executing instructions. Thus, such element amount to no more than mere instructions to apply the exception using generic computer elements and fail to integrate the judicial exception into a practical application under step 2A prong two or provide inventive concept under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claims 16-17 recite method claims are practiced by the apparatus claims 1 and 6. Thus, they are rejected for the same reasons.
Claim 18 further recites limitation that are abstract mathematical concepts without reciting any additional elements that make the claim any less abstract or that impose meaningful limits on practicing the abstract idea. Accordingly, the claims are not patent-eligible under 35 U.S.C. 101.
Claim 19 further recites a first BMMA operation is performed by the BMMA logic, the one or more additional BMMA operations to generate one or more elements of one or more additional result matrices based at least in part on a first set of data elements and a second set of data elements, wherein the result matrix is generated by executing the first BMMA operation based at least in part on executing the first BMMA operation based at least in part on the one or more elements of the one or more additional result matrices. Such limitation covers mathematical calculations, relationship, and/or formula (see figure 7 [0085], [0073], [0091-0095]). The claim further recites receiving one or more additional instructions for a corresponding one or more additional BMMA operations and execute by the processor, such limitation is recited at high level of generality e.g., as a generic system performing a generic computer function of receiving and processing data such as performing multiplying and accumulating operation and the additional element merely includes instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea, therefore, such additional elements fail to provide a meaningful limitation on the claim invention, and amount to no more than mere instructions to apply the exception using generic computer element under step 2A and does not provide an inventive concept under step 2B. Furthermore, the claim recite a first set of data represents bits of payload block of a parity check matrix, and a second set of data elements that represent a portion of a parity encoding matrix, and the result matrix represents a low density parity check (LDPC), such limitation fails to integrate the judicial exception into a practical application under step 2A because such additional element does no more than generally linking the judicial exception into a particular technological environment or field of use of LDPC encoding and does not provide an inventive concept under step 2B. Accordingly, the claims are not patent-eligible under 35 U.S.C. 101.
Claim 20 further recites wherein the first BMMA operation and the one or more additional BMMA operations are a first set of operations, performing a second set of operations the second set of operations includes a plurality of additional BMMA operations calculated based, at least in part, on a third set of data elements and a fourth set of data elements. such limitation covers mathematical calculations, relationship, and/or formula (see figure 7 [0085], [0073], [0091-0095]). Claim further recites executing by a processor, a second set of operations in parallel with the first set of operations, such limitation is recited at a high level of generality, i.e., as a generic system performing a generic computer function of processing data in parallel. Alternatively, the step of performing operations in parallel is at most considered as an insignificant extra solution activity because such limitation is determined to be well-understood, routine, and conventional under step 2B (see at least Hennessy, John L., et al. Computer Architecture : A Quantitative Approach, Elsevier Science & Technology, 2014. ProQuest page 531-532, figures 6.1 and 6.2 illustrates multi-processor operating in parallel. Furthermore, the claim recite a third set of data represents additional bits of payload block of a parity check matrix, and a fourth set of data elements that represent an additional portion of a parity encoding matrix, such limitation fails to integrate the judicial exception into a practical application under step 2A because such additional element does no more than generally linking the judicial exception into a particular technological environment or field of use of LDPC encoding and does not provide an inventive concept under step 2B. Accordingly, the claims are not patent-eligible under 35 U.S.C. 101.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 9-12 and 16-18 are rejected under 35 U.S.C.102(a)(1) as being anticipated by Stein - US 20040078409.
Regarding claim 9, Stein teaches a non-transitory machine-readable medium having stored hereon a set of instructions, which if performed by one or more processors, cause the one or more processor to (Stein, [0047] describes application serial no 10/060,699 or US 20030105791 is incorporated herein in its entirely by this reference (hereinafter ‘791), see figure 5 of ‘791 illustrates a memory storing instructions to load/store and perform operations [i.e., a set of instructions] that are executed by the DSP having registers, multiplier circuit, Galois field linear transformer circuit, and buses [i.e., one or more processor] to perform Galois field multiplication as illustrated in figure 10 of Stein ‘409 in digital processing signal) at least cause the one or more processors to calculate a plurality of Galois residues in parallel (Stein, [0043] describes Galois field polynomial multiplication can implemented in two basic steps, first is c(x) = a(x)*b(x) and [0036] second is d(x) = c(x) modulo p(x) where p(x) is an irreducible polynomial. Figure 10 [0040] describes a plurality of multiplier cells generate a plurality of term polynomial c(x) defined as chart II, e.g., c0 – c14, and [0048] the product represented in chart II is submitted to the Galois field linear transformer unit to predict the modulo remainder of the polynomial product for a predetermined irreducible polynomial (i.e., performing d(x) = c(x) mod p(x)), which results in Galois residue value since mod operation is performed. Thus, figure 10 [0119] describes each engine operates on its own pair of polynomials (e.g., A0-A3 and B0-B3) to generate the corresponding 8 bit Galois field residue values [i.e. a plurality of Galois residues], and figure 10 illustrates each engine operates independently and parallel) based, at least in part, on a first matrix and a second matrix (Stein figure 10 illustrates registers 14 and 16 [0119] each contains 32, 64, or 128 bit wide comprises a plurality of 8 bit data, thus data A0,A1,A2,A3 corresponds to a first matrix and B0,B1,B2,B3 corresponds a second matrix), and to store the plurality of Galois residues in one or more destination computer storage locations using circuitry comprising bit matrix multiply and accumulate (BMMA) logic (Stein, figure 3 illustrates implementation of one engine, wherein the output data of Galois field linear transformer unit 20b is stored in output register 16b. Thus, a plurality of Galois residues generated by the engines are stored in corresponding output register [i.e., one or more destination computer storage locations]. Figure 10 illustrates [0119] a plurality of engines, each includes polynomial multiplier circuit 18 [0046], which includes a plurality of multiplier cells and Galois field linear transformer 20, wherein the circuit 18 and transformer circuit 20 are operated based on [0012] AND gate and XOR gate to perform multiply and accumulate operations and are arranged in a matrix. Thus, such circuits 12 and 18 of the plurality of engines corresponds to BMMA logic).
Regarding claim 10, Stein teaches the non-transitory machine-readable medium of claim 9, wherein the BMMA logic causes a bitwise AND operation to be performed (Stein, figure 4 illustrates implementation of transformer unit having AND gate to perform bitwise AND operation).
Regarding claim 11, Stein teaches the non-transitory machine-readable medium of claim 10, wherein the set of instructions, which if performed by the one or more processors. Further causes the one or more processors to calculate the plurality of Galois residues based, at least in part, on an XOR operation applied to at least a portion of a result of the bitwise AND operation (Stein, as explained above, [0119] results of the plurality of transformer units 20 of the engines corresponds to the Galois residues. Figure 10 illustrates a plurality of multiplier units 10 and a plurality of units 20. See figure 4 illustrate implementation of transformer unit having XOR gate applied to a result of the AND gate).
Regarding claim 12, Stein teaches the non-transitory machine-readable medium of claim 10, wherein the one or more Galois residues comprise a first Galois residue (Stein, [0041] Each of the Galois field linear transformer units predicts in one cycle the modulo remainder by dividing the polynomial product by an irreducible polynomial, thus for example figure 10, 20h generates a first Galois residue), and the set of instructions, which if performed by the one or more processors, further causes the one or more processors to calculate one or more additional Galois residues in parallel with the first Galois residue in response to using the bit matrix multiply and accumulate logic (Stein figure 10 transformer circuits 20i-20n calculate one or more additional Galois residue values in parallel with the first Galois residue value in response to using the multiplier circuits 18 and the transformer circuits 20 of the plurality of engines).
Claim 16 recites method claim having similar limitation as the product claim 9. Thus, it is rejected for the same reasons.
Regarding claim 17, Stein teaches the method of claim 16, further comprising generating a first set of values based, at least in part, on a matrix representation of a Galois polynomial of a first degree value (Stein, [0043] Galois field polynomial multiplication can be implemented in two basic steps, wherein first step is performed by the multiplier circuit (e.g., circuit 18 performs c(x) = a(x)*b(x), one example provided as c(x) =
c
6
x
6
+
c
5
x
5
+
c
4
x
4
+
c
3
x
3
+
c
2
x
2
+
c
1
x
1
+
c
0
, and figure 10 illustrates at least 4 engines to operates on at least 4 pairs of polynomials, thus 4 results of c(x) corresponds to a first set of values generated based on a matrix representation of Galois polynomial (e.g.,
c
6
x
6
+
c
5
x
5
+
c
4
x
4
+
c
3
x
3
+
c
2
x
2
+
c
1
x
1
+
c
0
), wherein a result matrix is generated by the BMMA logic to represent one or more Galois residue values (Stein figure 10 illustrates the multiplier circuits 18 and a number of Galois field linear transformer units 20 of the engines having cells structure as a matrix to perform multiplication using AND gate and accumulation using XOR gate. Thus, the multiplier circuits 18 and transformer circuits 20 corresponds to the BMMA logic that generate a result matrix that represent one or more Galois residue values since the transformer circuits 20 performs modulo operation), and a bitwise logical AND operation is performed with respect to the first set of values and a second set of values that represents one or more polynomials of a second degree value higher than the first degree value (Stein figure 10 illustrates the transformer circuits 20 having a plurality cells, wherein each cell comprises AND gate to perform bitwise logical AND operation as illustrated in figure 4 to perform the second step d(x)=c(x) modulo p(x) as described in [0044], wherein c(x) corresponds to the first set of values and p(x) is the irreducible polynomial having a set of coefficients that are supplied to the transformer circuits 20 to be operated, which can be selected from anyone of the hose shown in chart III [0048]. Thus, the AND gates in transformer circuit 20 operates on the first set of values c(x) (e.g.
c
6
x
6
+
c
5
x
5
+
c
4
x
4
+
c
3
x
3
+
c
2
x
2
+
c
1
x
1
+
c
0
) and second set of values (e.g. the p(x) polynomial selected corresponding to each engine for generating d(x), such as
(
x
8
+
x
4
+
x
3
+
x
2
+
1
)
), wherein second set of values have higher degree than the first degree value).
Regarding claim 18, Stein teaches the method of claim 17, wherein the result matrix represents two or more Galois residue values (Stein, figure 10 illustrates at least 4 results from the 4 engines generated by the transformer units 20 [i.e., two or more Galois residue values] and the second set of values represents two or more polynomials of the second degree value (Stein figure 10 illustrates a plurality of engines to perform d(x) = c(x) mod p(x) [0044], wherein thus the second set of values (e.g. the p(x) polynomial selected corresponding to each engine for generating d(x)) represents at least two or more polynomials of the second degree value)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Stein in view of Chen – US 20020184281 .
Regarding claim 13, Stein teaches the non-transitory machine-readable medium of claim 10, wherein the set of instructions, which if performed by the one or more processors, further cause the one or more processors to generate a first set of values based, at least in part, on a matrix representation of a Galois polynomial (Stein, figure 5 of ‘791 illustrates load/store data buses, multiplier circuit and transformer circuit, thus these circuits correspond to one or more circuits, [0043] describes Galois field polynomial multiplication can be implemented in two basic steps, wherein first step is performed by the multiplier circuit (e.g., circuit 18 performs c(x) = a(x)*b(x), one example provided as c(x) =
c
6
x
6
+
c
5
x
5
+
c
4
x
4
+
c
3
x
3
+
c
2
x
2
+
c
1
x
1
+
c
0
, and figure 10 illustrates at least 4 engines to operates on at least 4 pairs of polynomials, thus 4 results of c(x) corresponds to a first set of values generated based on a matrix representation of Galois polynomial (e.g.,
c
6
x
6
+
c
5
x
5
+
c
4
x
4
+
c
3
x
3
+
c
2
x
2
+
c
1
x
1
+
c
0
), and calculate the plurality of Galois residue values based, at least in part, on the first set of values (Stein, [0044] describes the second step is to calculate d(x) = c(x) modulo p(x), which is being performed by the plurality of Galois transformer circuit 20 as illustrated in figure 10. Thus, at least 4 Galois residues are calculated based on 4 results of c(x) [i.e. the first set of values]). Stein does not teach load the first set of values in a first register. However, Chen teaches the step of loading a first set of values in a first register (Chen figure 1 illustrates a finite field multiplier having a parallel column based matrix vector generator comprises a plurality of AND gates and XOR gates to generate a vector values A [i.e., a first set of values] as illustrated in figure 2, wherein the vector values A are loaded into a plurality of D flip flops [i.e., a first register]).
It would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to modify the system as illustrated in figure 10 of Stein to include a plurality of flip flop as a register after the multiplier circuit 18 to store the calculated values as disclosed in figure 2 of Chen. This modification would have been obvious because both references disclose system and method to perform finite field multiplier using AND gates to perform multiplication and XOR gate to perform addition. Furthermore, having a register to store the intermediate results to act as a temporary storage for data, which reducing the need to repeatedly fetch and store data from main memory, and storing calculated results in register ensure that data can be access quickly for subsequent operations, which reducing the time spent on memory access.
Regarding claim 14, the combined system of Stein in view of Chen discloses the non-transitory machine-readable medium of claim 13, wherein the Galois polynomial is of a first degree value (Stein, [0043 describes c(x) =
c
6
x
6
+
c
5
x
5
+
c
4
x
4
+
c
3
x
3
+
c
2
x
2
+
c
1
x
1
+
c
0
, which corresponds to Galois polynomial of a first degree value), wherein the set of instructions, which if performed by the one or more processors, further causes the one or more processors to load a second set of values in a second register (figure 5 of ‘791 illustrates the load/store buses are to load coefficients for transformer units 20 to operate, wherein Stein figure 10 illustrates transformer unit 20 receives coefficient data from 8x8 GJ poly coeff 80’ [0012] describes control unit supplies to the transformer unit a set of coefficients in parallel to the transformer units, such as 0x11D, which equivalents to
x
8
+
x
4
+
x
3
+
x
2
+
1
[i.e. a second set of values], thus a set coefficients of for polynomial
x
8
+
x
4
+
x
3
+
x
2
+
1
are loaded into an 8x8 GJ poly coeff 80’ [i.e. a second register]), wherein the second set of values represents one or more polynomials of a second degree value higher than the first degree value (Stein [0113] the set of coefficients represent the irreducible polynomial is selected as 0x11D, which equivalents to
x
8
+
x
4
+
x
3
+
x
2
+
1
having higher degree than degree polynomial of c(x), such as
c
6
x
6
+
c
5
x
5
+
c
4
x
4
+
c
3
x
3
+
c
2
x
2
+
c
1
x
1
+
c
0
), and further cause the one or more processors to calculate the plurality of Galois residues based, at least in part, on the second set of values in the second register (Stein, [0044] describes d(x) = c(x) mod p(x), which is being performed by the transformer units 20 as illustrated in figure 10 that provide results correspond to Galois residue values, and [0040] p(x) corresponds to irreducible polynomial, such as
x
8
+
x
4
+
x
3
+
x
2
+
1
).
Regarding claim 15, the combined system of Stein in view of Chen discloses the non-transitory machine-readable medium of claim 14, wherein the set of instructions, which if performed by the one or more processors, further cause the one or more processors to load a third set of values in the second register (Stein figure 10 illustrates an 8x8 GF poly coeff 80’ that comprises polynomial coefficients which are supply to the plurality of transformers unit, wherein chart III describes the possible irreducible or primitive polynomial having different degrees, thus a different irreducible polynomial [i.e., a third set of values] is loaded in the 8x8 GF poly coefficient [i.e., the second register] for used in different transformer unit 20), wherein the third set of values represents one or more polynomials (Stein, [0048] describes the chart III for possible irreducible polynomial to be chosen), and further cause the one or more processors to calculate one or more additional Galois residues based, at least in part on the first set of values in the first register and the third set of values in the second register (Stein [0048] describes each of the Galois field linear transformer units predicts the modulo remainder by dividing the polynomial product by an irreducible polynomial and as illustrated in figure 10, the transformer units 20 are operated independently using different irreducible polynomials to generate one or more Galois residues by performing d(x) = c(x) mod p(x), wherein p(x) is the irreducible polynomial, thus the transformer units 20 calculate d(x) according to a different chosen p(x) according to chart III and values of c(x) corresponding to each engine [i.e.,, the first set of values]).
Allowable Subject Matter
Claims 1-8 and 26 would be allowable if rewritten or amended to overcome the rejection under 35 U.S.C. 101, set forth in this Office action.
Claims 19-20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 101 and claim objections, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
For reasons for allowable subject matter of claims 19-20, see office action dated 06/28/2024 page 19-24.
Furthermore, the primary reasons for indication of allowable subject matter for claims 1-8, 26 is the limitation in combination of all limitations, such as the specific algorithm to calculate a plurality of Galois residues based on first and second matrices using the BMMA logic that invoke 112(f) interpretation, as described in figure 7, which includes the steps to generate matrix, and execute BMMA operations to produce eight 8 bits Galois residues value by performing modulo operation of quads Q0 to Q7 of matrix A and matrix of polynomial P.
Stein – US 20040078409
Stein discloses a system and method to perform Galois field multiplication that calculate residue values of elements A and B in parallel using multiplier circuits 18 and transformer circuits 20 of a plurality of engines as illustrated in figure 10, wherein each cell of multiplier circuit and transformer circuit comprises AND gate and XOR gate to perform bitwise operations on the matrices. However, Stein does not explicitly teach the specific algorithm to generate a plurality of Galois residues as described in figure 7.
For other cited prior art – see office action dated 06/28/2024 page 19-24.
Therefore, none of the closest found prior art teaches the limitations as required in claim 1. Accordingly, Claims 1-8 and 26 would be allowable if rewritten or amended to overcome the rejection under 35 U.S.C. 101, set forth in this Office action.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUY DUONG whose telephone number is (571)272-2764. The examiner can normally be reached Mon-Friday 7:30-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HUY DUONG/Examiner, Art Unit 2183 (571)272-2764
/JYOTI MEHTA/Supervisory Patent Examiner, Art Unit 2183