DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12 May 2025 has been entered.
Drawings
The drawings are objected to because:
The drawings contain deficient line quality and reference characters. All drawings must be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. Reference characters (numerals are preferred), sheet numbers, and view numbers must be plain and legible. Refer to 37 CFR 1.84(l) and 1.84(p(1)). See Figure(s) 1-11.
The view number format is improper. View numbers must be preceded by the abbreviation “FIG.” followed by the numeral identifying the figure. Other punctuation, formatting, graphics are not permitted. Refer to 37 CFR 1.84(u)(1). See Figure(s) 2-6.
The view numbering format is improper because non-partial independent views are inexplicably designated alphanumerically instead of being consecutively numbered using Arabic numerals, leading to a confusing numbering scheme. Only partial views intended to form one complete view, on one or several sheets, must be identified by the same number followed by a capital letter. The different views must otherwise be numbered in consecutive Arabic numerals, starting with 1, independent of the numbering of the sheets and, if possible, in the order in which they appear on the drawing sheet(s). Refer to 37 CFR 1.84(u). See Figure(s) 7a-f and 9a-c
The drawings illustrate a figure comprising two or more independent figures requiring individual designation as separate features and therefore the drawings require a numbering change to the figures. Otherwise, if the multiple figures designated as one represent an exploded view, the figure in question should be properly identified as an exploded view using brackets as objected to supra. For numbering figures, the different views must be numbered in consecutive Arabic numerals, starting with 1, independent of the numbering of the sheets and, if possible, in the order in which they appear on the drawing sheet(s). Refer to 37 CFR 1.84(u). See Figure(s) 7a-f and 9a-c.
The drawings make improper use of shading. The use of shading in views is encouraged if it aids in understanding the invention and if it does not reduce legibility. Shading is used to indicate the surface or shape of spherical, cylindrical, and conical elements of an object. Such shading is preferred in the case of parts shown in perspective, but not for cross sections. Solid black or gray shading areas are not permitted, except when used to represent bar graphs or color. Refer to 37 CFR 1.84(m) and 1.84(h(3)). See Figure(s) 1-7 and 9.
The drawings contain excessive text. Suitable descriptive legends may be used, or may be required by the Examiner where necessary for understanding of the drawing but should contain as few words as possible. Refer to 37 CFR 1.84(o). See Figure(s) 1-7 and 9.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
Package Comprising Encapsulated Passive Device, Integrated Circuit, and Heat Dissipating Dummy Interconnects
Claim Interpretation
Claim 1 recites the limitation “an entire region along a width of the integrated device and located vertically between (i) a surface of the backside of the integrated device and (ii) a surface of the at least one dummy interconnect directly touching the second encapsulation layer is free of any solder interconnect”. The limitation will be interpreted as encompassing a selected region along a width of the integrated device, including only a cross section of an area, that lies between the backside of the integrated device and any surface of the dummy interconnect that is in direct contact with the second encapsulation layer. If the limitation was interpreted to be more narrow and required that no solder interconnect occupy any space in three dimensions that exist between the backside of the die and the dummy interconnect, along the width of the integrated device then the originally filed application would lack support and the newly amended language would introduce new matter, as there is only support for the limitation in cross section.
This application includes one or more claim limitations that use the word “means” or “step” but are nonetheless not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph because the claim limitation(s) recite(s) sufficient structure, materials, or acts to entirely perform the recited function. Such claim limitation(s) is/are: “first means for encapsulation” and “second means for encapsulation” in claim 11. The term “first means for encapsulation” are given the structure of encapsulating the passive device and the “second means for encapsulation” is given the structure of being coupled to the second surface of the substrate, having a first side opposite to the second surface of the substrate, and having a plurality of through encapsulation layer interconnects, a plurality of encapsulation layer interconnects, and at least one dummy interconnect located within the second means of encapsulation.
Because this/these claim limitation(s) is/are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof.
If applicant intends to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation(s) does/do not recite sufficient structure, materials, or acts to perform the claimed function.
Claim 21 recites the limitation “an entire region along a width of the integrated device and located vertically between (i) a surface of the backside of the integrated device and (ii) a surface of the at least one dummy interconnect directly touching the second encapsulation layer is free of any solder interconnect”. The limitation will be interpreted as encompassing a selected region along a width of the integrated device, including only a cross section of an area, that lies between the backside of the integrated device and any surface of the dummy interconnect that is in direct contact with the second encapsulation layer. If the limitation was interpreted to be more narrow and required that no solder interconnect occupy any space in three dimensions that exist between the backside of the die and the dummy interconnect, along a width of the integrated device then the originally filed application would lack support and the newly amended language would introduce new matter, as there is only support for the limitation in cross section.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claim 23 and depending Claim 24 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The claim includes contradicting limitations directed to two distinct species of the disclosed invention. The claim includes the limitations of “a thermal interface material…touching (i) a back side of the integrated device and (ii) that at least one dummy interconnect” (Figures 4-6, 7F, 9C) wherein the parent claim includes the limitation of “an entire region located vertically between (i) a surface of the backside of the integrated device and (ii) a surface of the at least one dummy interconnect directly touching the second encapsulation layer is free of any solder interconnect” (Figure 2). There is no disclosed embodiment wherein a region along a width of the integrated device and located vertically between the backside of the chip and a surface of the dummy interconnect is free of any solder interconnect and wherein a thermal interface material is also between the dummy interconnects and the backside of the chip, touching the backside of said chip. Furthermore, the material of the TIM is never specified and therefore there is no positive recitation of the TIM not being solder interconnect. As noted above, this is taken under consideration of the claim language “an entire region along a width of the integrated device and located vertically…” being interpreted to encompass a selected region equivalent to a cross section, as otherwise there is no support for said limitation in the originally filed specification. This issue had originally been avoided in the claim set filed 22 May 2023, wherein the independent claims were amended to encompass the embodiment of Figure 2 and the dependent claims encompassing the embodiment of Figures 4-6 were canceled. This issue was also ameliorated in the amendments to Claim 11 filed 31 October 2024.
Claim 23 and depending Claim 24 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The claim recites the limitation of “wherein the thermal interface material (TIM) is a different material from solder interconnect and from any interconnect from the plurality of interconnects”. The originally filed disclosure lacks any description of the material makeup of the thermal interface material (TIM), other than that it differs in thermal conductivity value from the second encapsulation layer (“The TIM 460 has better (e.g., higher) thermal conductivity value than the thermal conductivity value of the second encapsulation layer 206” see [0031]). The originally filed description fails to disclose the specific material makeup or value of material property of the TIM and fails to differentiate the material different between the TIM and the solder interconnects and/or plurality of interconnects.
Claim 27 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The claim includes contradicting limitations directed to two distinct species of the disclosed invention. The claim includes the limitation of “wherein the entire region along the width of the integrated device and located vertically between (i) the surface of the back side of the integrated device and (ii) the surface of the at least one dummy interconnect that faces in the direction of the back side of the integrated device, is occupied by the second encapsulation layer”. There is only explicit disclosure for the entire region located vertically between (i) the surface of the back side of the integrated device and (ii) the surface of the at least one dummy interconnect that faces in the direction of the back side of the integrated device in cross section, is occupied by the second encapsulation layer.
Claim 27 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The claim contains the negative limitation of “wherein the surface of the back side of the integrated device is free of direct touching with any interconnect”. There is only explicit disclosure for the surface of the back side of the integrated device is free of direct touching with any interconnect in cross section.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1 and depending claims 2-5, 8-10, 23-24, 27, and Claim 21 and depending claim 22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitations of “a plurality of solder interconnects” and “wherein an entire region…is free of any solder interconnect”. It is unclear if the entire region is limited to be free of any of the plurality of solder interconnects or if the limitation prohibits any sort of solder interconnect from existing in the region. For purposes of examination, the claim will be read as “wherein an entire region…is free from any solder interconnect of the plurality of solder interconnects".
Claim 21 recites the limitations of “a plurality of solder interconnects” and “wherein an entire region…is free of any solder interconnect”. It is unclear if the entire region is limited to be free of any of the plurality of solder interconnects or if the limitation prohibits any sort of solder interconnect from existing in the region. For purposes of examination, the claim will be read as “wherein an entire region…is free from any solder interconnect of the plurality of interconnects".
Claim 23 recites the limitation “wherein a front side of the integrated device” and the parent claim, Claim 1, recites “such that a front side of the integrated device” and it is unclear if the integrated device has two distinct front sides of if the limitations are drawn to the same front surface. It appears this was made in error and the claim will be read as “wherein the front side of the integrated device”.
Claim 23 recites the limitation “wherein the thermal interface material (TIM) is a different material from solder interconnect” but it is unclear if the claim is limiting the TIM to be a different material than the material of the plurality of solder interconnects or if the claim is excluding any solder from the material of the TIM. For purposes of examination, the claim will be interpreted to read “wherein the thermal interface material (TIM) is a different material than the plurality of solder interconnects”.
Claim 27 recites the limitation "the surface of the at least one dummy interconnect that faces in the direction of the back side of the integrated device”. There is insufficient antecedent basis for this limitation in the claim. The claim will be read as “the surface of the at least one dummy interconnect directly touching the second encapsulation layer”.
Claim 27 recites the limitation “wherein the surface of the back side of the integrated device is free of direct touching with any interconnect”. It is unclear if the limitation is directed to the exclusion of the interconnect and/or the plurality of solder interconnects and/or the plurality of through encapsulation layer interconnects and/or encapsulation layer interconnects and/or the at least one dummy interconnect, or if the limitation is direct to the exclusion of any sort of conceivable interconnect. For purposes of examination, the claim will be interpreted to read ““wherein the surface of the back side of the integrated device is free of direct touching with any interconnect of the plurality of interconnects”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 10-13, 15, 20-23, 25, and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. 20180240729) in view of Lin et al. (U.S. 2013/0187268).
Regarding Claim 1, Kim et al. (Figures 8, 9, and 13) discloses a package comprising:
a substrate comprising a first surface and a second surface (150/100), wherein the substrate further comprises a plurality of interconnects (112/114/116);
a passive device coupled to the first surface of the substrate (200a);
a first encapsulation layer located over the first surface of the substrate, wherein the first encapsulation layer encapsulates the passive device (130a);
an integrated device (200b) coupled to the second surface of the substrate through a plurality of integrated device interconnects (202b) such that a front side of the integrated device faces in a direction towards the second surface of the substrate;
a second encapsulation layer coupled to the second surface of the substrate, the second encapsulation layer having a first side that is opposite to the second surface of the substrate (130a);
a plurality of through encapsulation layer interconnects located in the second encapsulation layer and coupled to the substrate (146 or 124);
a plurality of encapsulation layer interconnects located in the second encapsulation layer and coupled to the plurality of through encapsulation layer interconnects (124 or 146); and
at least one dummy interconnect located at least partially in the second encapsulation layer such that the integrated device is located between the at least one dummy interconnect and the substrate (122b and/or 121b/122b),
wherein the integrated device (200b) includes a back side that is closest to the first side of the second encapsulation layer (130b) and furthest away from the second surface of the substrate (100/150),
wherein the second encapsulation layer (130b) is located vertically between the back side of the integrated device (200b) and the at least one dummy interconnect (122b and/or 121b/122b), and
wherein the second encapsulation layer (130b) touches the substrate (100/150), the back side of the integrated device (200b) and the at least one dummy interconnect (122b and/or 121b/122b), and
wherein an entire region located along a width of the integrated device and vertically between (i) a surface of the back side of the integrated device (200b) and (ii) -a surface of the at least one dummy interconnect (122b and/or 121b/122b) directly touching the second encapsulation layer (130b), is free of any solder interconnect.
However, they do not explicitly disclose that the plurality of integrated device interconnects are a plurality of solder interconnects. Lin et al. Figure 9 discloses a similar device wherein an integrated device (400) is coupled to a second surface of a substrate (105) through a plurality of solder interconnects (403, [0036]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the plurality of integrated device interconnects to be a plurality of solder interconnects in Kim et al. in view of Lin et al. in order to form the integrated device interconnects of a suitable type of contact (Lin et al, [0036]). The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
Regarding Claim 2, Kim et al. (Figures 8, 9, and 13) in view of Lin et al. (Figure 9) further discloses wherein the at least one dummy interconnect is configured to be free of an electrical connection with the integrated device (Kim et al, Paragraph 65).
Regarding Claim 3, Kim et al. (Figures 8, 9, and 13) in view of Lin et al. (Figure 9) further discloses wherein the at least one dummy interconnect is configured to be free of an electrical connection with the passive device (Kim et al, Paragraph 65).
Regarding Claim 5, Kim et al. (Figures 8, 9, and 13) in view of Lin et al. (Figure 9) further discloses wherein the plurality of through encapsulation layer interconnects comprises a ball interconnect, a pillar and/or a via (Kim et al, 124 or 146).
Regarding Claim 10, Kim et al. (Figures 8, 9, and 13) in view of Lin et al. (Figure 9) further discloses wherein the package is incorporated into a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle (Kim et al., Paragraph 163).
Regarding Claim 23, Kim et al. (Figures 8, 9, and 13) in view of Lin et al. (Figure 9) further discloses a thermal interface material (TIM) located between the integrated device and the at least one dummy interconnect, wherein the thermal interface material (TIM) is coupled to and touching (i) the back side of the integrated device and (II) the at least one dummy interconnect (Kim et al, 204),
wherein the thermal interface material (TIM), is a different material from solder interconnect and from any interconnect from the plurality of interconnects (Kim et al., [0056], [0064], Lin et al. [0036]),
wherein a side portion of the at least one dummy interconnect (Kim et al., 122b and/or 121b/122b) touches the second encapsulation layer (Kim et al, 130b), and
wherein a front side of the integrated device (Kim et al., 200b) is coupled to the substrate (Kim et al., 100/150) through the plurality of solder interconnects (Lin et al., 403, [0036]).
Regarding Claim 27, Kim et al. (Figures 8, 9, and 13) in view of Lin et al. (Figure 9) further discloses wherein the entire region along the width of the integrated device and located vertically between (i) the surface of the back side of the integrated device and (ii) the surface of the at least one dummy interconnect that faces in the direction of the back side of the integrated device, is occupied by the second encapsulation layer (Kim et al, 130, 200, 122 and/or 121/122),
wherein the surface of the back side of the integrated device (Kim et al., 200b) is free of direct touching with any interconnect (112/114/116).
Regarding Claim 11, Kim et al. (Figures 8, 9, and 13) discloses an apparatus comprising:
a substrate comprising a first surface and a second surface (150/100), wherein the substrate further comprises a plurality of interconnects (112/114/116);
a passive device coupled to the first surface of the substrate (200a);
first means for encapsulation located over the first surface of the substrate, wherein the first means for encapsulation encapsulates the passive device (130a);
an integrated device (200b) coupled to the second surface of the substrate through a plurality of integrated device interconnects (202b);
second means for encapsulation coupled to the second surface of the substrate, the second means for encapsulation having a first side that is opposite to the second surface of the substrate (130b);
a plurality of through encapsulation layer interconnects located in the second means for encapsulation and coupled to the substrate (146 or 124);
a plurality of encapsulation layer interconnects located in the second means for encapsulation and coupled to the plurality of through encapsulation layer interconnects (124 or 146); and
at least one dummy interconnect located at least partially in the second means for encapsulation such that the integrated device is located between the at least one dummy interconnect and the substrate (122b and/or 121b/122b),
a thermal interface material (TIM) located between the integrated device and the at least one dummy interconnect, wherein the thermal interface material (TIM) is coupled to and touching (i) the back side of the integrated device and (II) the at least one dummy interconnect (204).
However, they do not explicitly disclose that the plurality of integrated device interconnects are a plurality of solder interconnects. Lin et al. Figure 9 discloses a similar device wherein an integrated device (400) is coupled to a second surface of a substrate (105) through a plurality of solder interconnects (403, [0036]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the plurality of integrated device interconnects to be a plurality of solder interconnects in Kim et al. in view of Lin et al. in order to form the integrated device interconnects of a suitable type of contact (Lin et al, [0036]). The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
Regarding Claim 12, Kim et al. (Figures 8, 9, and 13) in view of Lin et al. (Figure 9) further discloses wherein the at least one dummy interconnect is configured to be free of an electrical connection with the integrated device (Kim et al., Paragraph 65).
Regarding Claim 13, Kim et al. (Figures 8, 9, and 13) in view of Lin et al. (Figure 9) further discloses wherein the at least one dummy interconnect is configured to be free of an electrical connection with the passive device (Kim et al., Paragraph 65).
Regarding Claim 15, Kim et al. (Figures 8, 9, and 13) in view of Lin et al. (Figure 9) further discloses wherein the plurality of through encapsulation layer interconnects comprises a ball interconnect, a pillar and/or a via (Kim et al., 146 or 124).
Regarding Claim 20, Kim et al. (Figures 8, 9, and 13) in view of Lin et al. (Figure 9) further discloses wherein the apparatus is incorporated into a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle (Kim et al., Paragraph 163).
Regarding Claim 25, Kim et al. (Figures 8, 9, and 13) in view of Lin et al. (Figure 9) further discloses wherein a front side of the integrated device (Kim et al., 202) is coupled to the substrate through the plurality of solder interconnects (Kim et al., 202b).
Regarding Claim 21, Kim et al. (Figures 8, 9, and 13) discloses a method for fabricating a package, comprising:
providing a substrate comprising a first surface and a second surface (150/100), wherein the substrate further comprises a plurality of interconnects (112/114/116);
coupling a passive device to the first surface of the substrate (200a);
forming a first encapsulation layer over the first surface of the substrate, wherein the first encapsulation layer encapsulates the passive device (130a);
coupling a front side of an integrated device (200b) to the second surface of the substrate through a plurality of integrated device interconnects (202b);
forming a second encapsulation layer over the second surface of the substrate, the second encapsulation layer having a first side that is opposite to the second surface of the substrate (130b);
providing a plurality of through encapsulation layer interconnects located in the second encapsulation layer and coupled to the substrate (146 or 124);
providing a plurality of encapsulation layer interconnects located in the second encapsulation layer and coupled to the plurality of through encapsulation layer interconnects (124 or 146); and
providing at least one dummy interconnect in the second encapsulation layer on the first side of the second encapsulation layer, and vertically underneath the integrated device (122b and/or 121b/122b),
wherein the at least one dummy interconnect is provided in the second encapsulation layer such that the integrated device (200b) is located between the at least one dummy interconnect (122b and/or 121b/122b) and the substrate (150/100),
wherein the integrated device (200b) includes a back side that is closest to the first side of the second encapsulation layer (130b) and furthest away from the second surface of the substrate (150/100),
wherein the second encapsulation layer (130b) is located vertically between the back side of the integrated device (200b) and the at least one dummy interconnect (122b and/or 121b/122b), and
wherein the second encapsulation layer is formed such that the second encapsulation layer (130b) touches the substrate (150/100), the back side of the integrated device (200b) and the at least one dummy interconnect (122b and/or 121b/122b), and
wherein an entire region along a width of the integrated device and located vertically between (i) a surface of the back side of the integrated device (200b) and (ii) -a surface of the at least one dummy interconnect (122b and/or 121b/122b) directly touching the second encapsulation layer (130b), is free of any solder interconnect.
However, they do not explicitly disclose that the plurality of integrated device interconnects are a plurality of solder interconnects. Lin et al. Figure 9 discloses a similar device wherein an integrated device (400) is coupled to a second surface of a substrate (105) through a plurality of solder interconnects (403, [0036]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the plurality of integrated device interconnects to be a plurality of solder interconnects in Kim et al. in view of Lin et al. in order to form the integrated device interconnects of a suitable type of contact (Lin et al, [0036]). The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
Regarding Claim 22, Kim et al. (Figures 8, 9, and 13) in view of Lin et al. (Figure 9) further discloses wherein the at least one dummy interconnect is configured to be free of an electrical connection with the integrated device (Kim et al., Paragraph 65).
Claims 4 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. 20180240729) Lin et al. (U.S. 2013/0187268) as applied to claim 1 above, and further in view of and further in view of Takeuchi et al. (U.S. 2005/0184377).
Regarding Claim 4, Kim et al. (Figures 8, 9, and 13) in view of Lin et al. (Figure 9) discloses the package of claim 1 and further discloses further comprising: a second plurality of solder interconnects coupled to the plurality of encapsulation layer interconnects (Kim et al., 160) but they do not explicitly disclose at least one dummy solder interconnect coupled to the at least one dummy interconnect. Takeuchi et al. discloses a similar device wherein there is at least one dummy solder interconnect coupled to the at least one dummy interconnect (Figures 7 and 15, 22, 31). Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to form at least one dummy solder interconnect coupled to the at least one dummy interconnect in Kim et al. in view of Lin et al., further in view of Takeuchi et al. in order to spread heat to the outside via in the stacked package (Takeuchi et al., Paragraphs 69 and 81).
Regarding Claim 24, Kim et al. (Figures 8, 9, and 13) in view of Lin et al. (Figure 9) discloses the package of claim 23 and further discloses wherein the at least one dummy solder interconnect is configured to be free of an electrical connection with the integrated device (Kim et al., Paragraph 65) but they do not explicitly disclose at least one dummy solder interconnect coupled to and touching the at least one dummy interconnect. Takeuchi et al. discloses a similar device wherein there is at least one dummy solder interconnect coupled to and touching the at least one dummy interconnect (Figures 7 and 15, 22, 31). Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to form at least one dummy solder interconnect coupled to and touching the at least one dummy interconnect in Kim et al. in view of Lin et al., further in view of Takeuchi et al. in order to spread heat to the outside via in the stacked package (Takeuchi et al., et al., Paragraphs 69 and 81).
Claims 8 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. 20180240729) Lin et al. (U.S. 2013/0187268) as applied to claim 1 above.
Regarding Claim 8, Kim et al. in view of Lin et al. discloses the limitations of Claim 1 but does not explicitly disclose a second integrated device coupled to the first surface of the substrate. However, they disclose a different embodiment wherein multiple devices are mounted on a single side of a substrate. The Examiner takes Official Notice of the fact that it was known in the art to include multiple devices in a package so as to increase device density and customize device function. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a second integrated device coupled to the first surface of the substrate in Kim et al. in view of Lin et al. to increase device density and to provide an effect of a precise process (Kim et al., Paragraph 114).
Regarding Claim 9, Kim et al. (Figure 14) in view of Lin et al. further discloses wherein the first encapsulation layer encapsulates the second integrated device (Kim et al., 200a, 200b, 130, Figure 14).
Claims 18 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. 20180240729) in view of Lin et al. (U.S. 2013/0187268) as applied to claim 11 above.
Regarding Claim 18, Kim et al. in view of Lin et al. discloses the apparatus of claim 11 but does not explicitly disclose a second integrated device coupled to the first surface of the substrate. However, they disclose a different embodiment wherein multiple devices are mounted on a single side of a substrate. The Examiner takes Official Notice of the fact that it was known in the art to include multiple devices in a package so as to increase device density and customize device function. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a second integrated device coupled to the first surface of the substrate in Kim et al. in view of Lin et al. to increase device density and to provide an effect of a precise process (Kim et al., Paragraph 114).
Regarding Claim 19, Kim et al. (Figure 14) in view of Lin et al. discloses the package of claim 18 and further discloses wherein the first means for encapsulation encapsulates the second integrated device (Kim et al., 200a, 200b, 130, Figure 14).
Claims 14 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. 20180240729) in view of Lin et al. (U.S. 2013/0187268) as applied to claim 11 above, and further in view of Takeuchi et al. (U.S. 2005/0184377).
Regarding Claim 14, Kim et al. (Figures 8, 9, and 13) in view of Lin et al. (Figure 9) discloses the apparatus of claim 11 and further discloses further comprising: a second plurality of solder interconnects coupled to the plurality of encapsulation layer interconnects (Kim et al., 160) but they do not explicitly disclose at least one dummy solder interconnect coupled to the at least one dummy interconnect. Takeuchi et al. discloses a similar device wherein there is at least one dummy solder interconnect coupled to the at least one dummy interconnect (Figures 7 and 15, 22, 31). Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to form at least one dummy solder interconnect coupled to the at least one dummy interconnect in Kim et al. in view of Lin et al., further in view of Takeuchi et al. in order to spread heat to the outside via in the stacked package (Takeuchi et al., Paragraphs 69 and 81).
Regarding Claim 26, Kim et al. (Figures 8, 9, and 13) in view of Lin et al. (Figure 9) discloses the apparatus of claim 11 and further discloses wherein the at least one dummy solder interconnect is configured to be free of an electrical connection with the integrated device (Kim et al., Paragraph 65) but they do not explicitly disclose at least one dummy solder interconnect coupled to and touching the at least one dummy interconnect. Takeuchi et al. discloses a similar device wherein there is at least one dummy solder interconnect coupled to and touching the at least one dummy interconnect (Figures 7 and 15, 22, 31). Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to form at least one dummy solder interconnect coupled to and touching the at least one dummy interconnect in Kim et al. in view of Lin et al., further in view of Takeuchi et al. in order to spread heat to the outside via in the stacked package (Takeuchi et al., Paragraphs 69 and 81).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 11, and 21, regarding the “integrated device coupled to the second surface of the substrate through a plurality of solder interconnects” have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments filed 12 May 2025 have been fully considered but they are not persuasive.
Regarding Claims 1 and 21, the Applicant argues that the Kim reference fails to disclose “an entire region located vertically between (i) a surface of the back side of the integrated device and (ii) a surface of the at least one dummy interconnect directly touching the second encapsulation layer that is free of any solder interconnect”. Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references. Therefore they are not persuasive.
Regarding Claim 11, the Applicant argues that the Kim reference fails to disclose “…a thermal interface material (TIM) located between the integrated device and the at least one dummy interconnect, wherein the thermal interface material (TIM) is coupled to and touching a back side of the integrated device and the at least one dummy interconnect…” because Kim “teaches away from the use of thermal interface material (TIM)”. However, Kim et al. discloses a TIM 204 (Figures 8, 9, and 13). The elements must be arranged as required by the claim, but this is not an ipsissimis verbis test, i.e., identity of terminology is not required. In re Bond, 910 F.2d 831, 15 USPQ2d 1566 (Fed. Cir. 1990), see MPEP 2131. Furthermore, the Applicant argues that the Kim reference “teaches away” from TIM 204 being a TIM because the reference say “the use of the TIM may be omitted” in [0079]. However, if that were true, then the originally filed specification of the present application also teaches away from the claimed TIM from being a TIM, as the originally filed specification states, multiple times, that “The TIM 460 may be optional” ([0051, 0071]). Finally, in response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., the TIM is a material that is not titanium or copper) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). The originally filed specification fails to define the term “Thermal Interface Material” and further fails to provide a single example of material of the TIM. Both titanium and copper as disclosed in the Kim reference ([0064]) have thermal conductivity and are therefore thermally couple the elements on either side of it. The teaching reference, Choudhury et al. (U.S. 2017/0186665), discloses that copper is a known thermal interface material ([0034]). Therefore the arguments are not persuasive.
Regarding Claims 8 and 18, the Officially Noticed fact “it was known in the art to include multiple devices in a package so as to increase device density and customize device function” was not challenged in the response mailed 21 May 2024. Since this Officially Noticed fact was not traversed, it is taken to be admitted prior art (MPEP 2144.03C). Please note that, even though a fact is taken to be admitted prior art, the application of that fact in rendering obvious the claimed features may be traversed in the same manner as if the admitted prior art fact had been presented within a reference.
Conclusion
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Abbigale Boyle whose telephone number is 571-270-7919. The Examiner can normally be reached from 11 A.M to 7 P.M., Monday through Friday.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Zandra Smith, can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Abbigale Boyle
Examiner, Art Unit 2899
/ABBIGALE A BOYLE/Examiner, Art Unit 2899
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899