DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 22, and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over
Fazelpour US 2011/0204515 A1 in view of Stacey US 2012/0199967 A1. Fazelpour discloses (see, for example, FIG. 3A) a semiconductor package system 300 comprising a semiconductor substrate 105, and further discloses (see, for example, paragraph [0028]) the top semiconductor surface 107 comprising an active region having active circuitry 109(a) and 109(b). An encapsulation material 312 at least partially encapsulates the semiconductor substrate 105 and a portion of the active region, the encapsulation material 312 has a cavity extending through to an upper surface of the active region. The redistribution layer structure 327 is positioned over an upper surface of the encapsulation material 312, and includes a conformal layer 327 lining a bottom surface and sidewalls of the cavity and extending partially above the upper surface of the encapsulation material 312. A dielectric material 319 is disposed above the conformal layer 327 and above portions of the upper surface of the encapsulation material 312 without the conformal layer 327, the dielectric layer 319 filling the cavity, wherein at least a portion of the RDL 327 is in electrical contact with the active region of the semiconductor device through the conformal layer 327. Fazelpour does not specifically disclose the conformal layer being a conformal metal layer. However, Stacey discloses (see, for example, Figure 1, and paragraph [0038]) a semiconductor package system comprising a conformal metal layer 4. It would have been obvious to one of ordinary skill in the art to have a conformal layer being a conformal metal layer in order to provide high electrical conductivity between the semiconductor substrate and other regions of a semiconductor package system.
Regarding claim 22, see, for example, FIG. 3A wherein Fazelpour discloses the dielectric material 319 including a single dielectric layer.
Regarding claim 23, see, for example, FIG. 3A wherein Fazelpour discloses a solder ball 310(a). In Figure 1, Stacey discloses a conformal metal layer 4/8/7 that extends above the upper surface of an encapsulation material 3, portions of the conformal metal layer disposed within the dielectric material 5 and portions of the conformal metal layer extending, at least partially, above an upper surface of the dielectric material 5. Further, it would have been obvious to one of ordinary skill in the art to have portions of the conformal metal layer disposed within the dielectric material and portions of the conformal metal layer extending, at least partially, above an upper surface of the dielectric material in order to have a contiguous material that avoids discontinuities and/or defects, and thereby reduce effects such as noise, high impedance, etc.
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fazelpour US 2011/0204515 A1 in view of Stacey US 2012/0199967 A1 as applied to claims 1, 22, and 23 above, and further in view of Scanlan et al. US 2016/0086825 A1. Fazelpour in view of Stacey does not disclose an insulating layer encapsulating the semiconductor substrate and at least a portion of the encapsulation material, the insulating layer is disposed on a bottom surface of the encapsulation material and on a bottom surface of the semiconductor substrate, wherein the bottom surface of the encapsulation material is coplanar with the bottom surface of the semiconductor substrate. However, Scanlan discloses (see, for example, FIG. 19) a semiconductor package system 300 comprising and encapsulation material 366, and an insulating layer 384. In paragraph [0135], Scanlan discloses the insulating layer includes a dielectric film. It would have been obvious to one of ordinary skill in the art to have an insulating layer encapsulating the semiconductor substrate and at least a portion of the encapsulation material, the insulating layer is disposed on a bottom surface of the encapsulation material and on a bottom surface of the semiconductor substrate, wherein the bottom surface of the encapsulation material is coplanar with the bottom surface of the semiconductor substrate in order to protect the bottom surface of the semiconductor substrate.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, and 21-23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
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Eugene Lee
January 27, 2026
/EUGENE LEE/Primary Examiner, Art Unit 2815